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Tommy Thorn wrote: > On May 28, 12:40 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > >>Brian Drummond wrote: >> >>>On Mon, 28 May 2007 07:34:24 +1200, Jim Granville >>><no.s...@designtools.maps.co.nz> wrote: >> >>>>Frank Buss wrote: >>>><snip> >> >>>>If this runs slower, one of my pet ideas for FPGA cores, is to design >>>>them to run from SerialFLASH memory. Top end ones (winbond) run at >>>>150MBd of link speed, so can feed nearly 20MB/s of streaming code. >>>>Ideally, the core has a short-skip opcode, as the jump in such memory >>>>has a higher cost. >> >>>Or a "four address instruction" like the Pilot Ace, with SerialFlash in >>>place of a tube full of mercury? >> >>You've lost me ? >>-jg > > > Me too, but this looks relevant > > http://research.microsoft.com/~GBell/Computer_Structures__Readings_and_Examples/00000213.htm Wow, that's quite impressive. A 1MHz clock, back in 1951! I had not thought of Serial Data, only Serial code access, as those speeds are getting tolerable, and the pin/pcb savings are massive. Most FPGAs have some SRAM, and uC projects commonly need less DATA than Code, but it raises a good point: Serial data _could_ also be used, and the Ramtron FRAM devices would be good candidates - up to 64K bytes of Data, in 20MHz SPI. So, you'd set that up on separate pins. -jgArticle: 119876
On May 28, 2:33 pm, "Altera User" <altera_u...@nospam.com> wrote: > I've tried using the "interface" construct in a Quartus-II project, but I > can't tell if it's working the way it is supposed to. > I tried declaring an interface like the following: > > [...] > > What am I doing wrong? You are doing tons wrong ;) The interface specifies the collection of signals, and a modport declaration inside the interface specifies the direction of those signals, which is what I believe what you wanted to achieve. The following snippet should help you get started, but you'll find a wealth of information online that can describe how to use interfaces much better than I ever could... in a short-time frame that is. interface cpu_if; logic [15:0] cpu_addr; logic cpu_write; logic cpu_read; logic [15:0] cpu_wdata; logic [15:0] cpu_rdata; modport vga ( input cpu_addr, input cpu_write, input cpu_read, input cpu_wdata, output cpu_rdata ); modport cpu ( output cpu_addr, output cpu_write, output cpu_read, output cpu_wdata, input cpu_rdata ); endinterface // cpu_if -- Edmond Cot=E9Article: 119877
Oh no. RIP Rodney.Article: 119878
Can I use the CRC hardcores in Virtex5 to implement a 128-bit input CRC module? and how? Thanks a lot.Article: 119879
On 25 May, 16:46, Pablo <pbantu...@gmail.com> wrote: > On 25 mayo, 16:51, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On 25 Mai, 16:45, Pablo <pbantu...@gmail.com> wrote: > > > > On 25 mayo, 12:32, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 25 Mai, 12:20, Pablo <pbantu...@gmail.com> wrote: > > > > > > I have a SMT338 board. This is a FPGA module and now I want to add a > > > > > DDR SDRAM to my system. I have the ucf file provided by the company > > > > > but in this file I don't find ddr_feedback clock. What it means?. I > > > > > suppose that this pin is neccesary, but there is no pin called > > > > > "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" > > > > > y "ckn" but these signals are used by the fpga to the ddr. > > > > > > Has anyone the solution?. > > > > > > Regards > > > > > there are different IP cores, some use the extra feedback pin some > > > > dont. > > > > > boards that have the extra pin are better as they are easier to work > > > > with. > > > > > if you happen to have a board with no feedback pin then you need > > > > either use IP core > > > > that does not utilize the feedback, or make some workaround to the > > > > existing IP core > > > > so you can still use it. > > > > > Antti > > > > Do you know for some core without feedback?.- Zitierten Text ausblenden - > > > > - Zitierten Text anzeigen - > > > please look > > > opb_mch_sdram > > connect to... what > But I have to use a DDR core.- Hide quoted text - > > - Show quoted text - I'm curious,you have a sundance product, but haven't asked sundance for the answer.....Article: 119880
Dear group: PacoBlaze 2.2 has been released. This version solves some bugs that were still lurking in the stack and interrupt manipulation. The cores have also received more testing, and more debug information has been added to simulations enabled with the HAS_DEBUG macro. Instructions also have now a one-hot encoding format that is used when USE_ONEHOT_ENCODING is defined. Unfortunately, the compatibility with Icarus Verilog is broken but I am still working on it. The KCAsm assembler has been tweaked a bit to accept constructs in the form of the original KCPSM assembler, so that most PSM files should be accepted with little or no modification. The PacoBlaze web site is at http://bleyer.org/pacoblaze, where you can find more information and links to the source distribution. I can't end this post without referring to the tragic and unexpected loss of Rodney Smith. My deepest condolences to his family and friends. He was one of the pioneers and pillars of this industry that has vamped digital design in a new era. He will be really missed. Warmest regards. -- PabloBleyerKocik / "I wish I could sleep in a warm sleeping bag. pablo / No matter what happens I am going to climb McKinley." @bleyer.org / -- Naomi Uemura, 1984Article: 119881
On May 28, 9:07 pm, Duane Clark <junkm...@junkmail.com> wrote: > Pablo wrote: > > > So the process is the following: > > > 1=BA. I design my powerpc model with a generic memory core. This produce > > the CLK_DDR_FEEDBACK pin. > > 2=BA I don't use this pin and (in ISE) I change the system_stub.vhd like > > you have said. > > That is the way I do it. I always use top level ISE projects, and embed > EDK systems in them. I don't know how it would be done in a straight EDK > top level project. > > The clock signal should be going off the FPGA through some PCB traces > and back onto the FPGA feedback pin. If that pin does not exist on the > board, the method I showed will at least run it through an output and > input buffer, so the only part that is missing is the time it takes to > go through the PCB traces. That should be relatively unimportant, in > part because that time will be virtually a constant. Could you recommend me some manual/tutorial/book to learn how to use ISE projects. I am able to embed a EDK system in a ISE, but I only see the ports components and how these map. I am working on how to edit the ISE project as you have said. I work with Xilinx 8.2 and I think that in this version you cannot edit cores and things like you say. ThanksArticle: 119882
On May 28, 5:00 pm, "Slim" <S...@sliml.com> wrote: > What is the proper word that describes the total delay in a system from > analog input to digital output (including phase shift time in analog and > digital filters, calculations + other data transport times)? > > Propagation delay time, latency or other? Slim, I think the most appropriate one would be "System Latency". Just recall that, Latency is the time measurement for an output to occur from the triggered input. Hope this answers! Thanks, Harsh.Article: 119883
On 29 mayo, 09:29, colin <colin_toog...@yahoo.com> wrote: > On 25 May, 16:46, Pablo <pbantu...@gmail.com> wrote: > > > > > On 25 mayo, 16:51, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 25 Mai, 16:45, Pablo <pbantu...@gmail.com> wrote: > > > > > On 25 mayo, 12:32, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > On 25 Mai, 12:20, Pablo <pbantu...@gmail.com> wrote: > > > > > > > I have a SMT338 board. This is a FPGA module and now I want to add a > > > > > > DDR SDRAM to my system. I have the ucf file provided by the company > > > > > > but in this file I don't find ddr_feedback clock. What it means?. I > > > > > > suppose that this pin is neccesary, but there is no pin called > > > > > > "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" > > > > > > y "ckn" but these signals are used by the fpga to the ddr. > > > > > > > Has anyone the solution?. > > > > > > > Regards > > > > > > there are different IP cores, some use the extra feedback pin some > > > > > dont. > > > > > > boards that have the extra pin are better as they are easier to work > > > > > with. > > > > > > if you happen to have a board with no feedback pin then you need > > > > > either use IP core > > > > > that does not utilize the feedback, or make some workaround to the > > > > > existing IP core > > > > > so you can still use it. > > > > > > Antti > > > > > Do you know for some core without feedback?.- Zitierten Text ausblenden - > > > > > - Zitierten Text anzeigen - > > > > please look > > > > opb_mch_sdram > > > connect to... what > > But I have to use a DDR core.- Hide quoted text - > > > - Show quoted text - > > I'm curious,you have a sundance product, but haven't asked sundance > for the answer..... Who has said that I haven't asked sundance for the answer?.Article: 119884
Pablo Bleyer Kocik wrote: > Dear group: > > PacoBlaze 2.2 has been released. This version solves some bugs that > were still lurking in the stack and interrupt manipulation. The cores > have also received more testing, and more debug information has been > added to simulations enabled with the HAS_DEBUG macro. Instructions > also have now a one-hot encoding format that is used when > USE_ONEHOT_ENCODING is defined. Unfortunately, the compatibility with > Icarus Verilog is broken but I am still working on it. > > The KCAsm assembler has been tweaked a bit to accept constructs in > the form of the original KCPSM assembler, so that most PSM files > should be accepted with little or no modification. > > The PacoBlaze web site is at http://bleyer.org/pacoblaze, where you > can find more information and links to the source distribution. Hi Pablo, Can you add a simple table of Options/Resource, along the lines of the one here ? http://www.latticesemi.com/Mico8 -jgArticle: 119885
Dear All, I just wonder if there is a simple way to calculate IFFT based on FFT results? I was trying to configure xilinx FFT coregen v3.1 to perform IFFT operation, but no matter how hard I tried, the result is the same as FFT. Strange! The timing is exactly based on the FFTv3.1 datasheet. Assert fwd_inv_we ='1', and fwd_inv=' 0', and then de-assert fwd_inv_we. If this problem can not be solved, I have to calculate IFFT based on the result of FFT. Has anyone experienced this before? Cheers, YaoArticle: 119886
Thanks for your responses ! I'm happy people replied. The I have checked and read 90% of what is available on the Xilinx ML505 home page (Antti's Link). But my problem is that none of these contain test projects. They all have some precompiled code that I can't post edit (i.e. ACE files). I can only load these directly via their CF card interface. I have contacted Xilinx to see if they can give me a test project file with some VHDL/VERILOG code in it so that I can start for there. I want to learn about updating the FPGA with some of my own code. But first I want to have some code that I can get hands on experience with. Is there anything like a HELLO WORLD program for FPGAs ? I know it depends on my board layout, but I do have the UCF file that has the pin assignments. But putting this together in the project is starting to confuse me. any help would be really appreciated ! Thamks, Claire.Article: 119887
On May 28, 4:48 pm, Patrick Dubois <prdub...@gmail.com> wrote: > Hello, > > Does anyone else have problems with MPMC2 + flash bootloader in EDK > v9? > > I started a design on the FX12 mini-module using the ethernet echo > server reference design from Avnet. I then added a flash bootloader > functionality by taking the flash controller from another Avnet > reference design. Unfortunately this combination doesn't work for some > reason. > > A webcase with Xilinx (opened for one month) did not offer a solution > for this issue. Avnet however was quicker to respond, they > acknowledged the problem, quoting : "The bootloader design in EDK > 9.1.02 using the MPMC2 core has some issues.". They sent me a modified > echo server design using the PLB DDR controller instead of the MPMC2 > and it works. Unfortunately the perfomance suffers. > > I have yet to understand what the particular issue is. It is not clear > if this is a flaw intrinsic to MPMC2 or if it's related to the FX12 > mini-module. I'd like to know about others experiences with the MPCM2 > and/or mini-module. > > Thanks! > > Patrick Dubois Hi Patrick, I am working with a FX12 MiniModule and MPMC2. I have tried lots of variations for FLASH booting. I have not implemented OPB_EMC in my latest design (under EDK 9.1) since I have not enough logic resources. My experience from EDK 8.2: in core connect architecture (no MPMC2) Flashwriter and booting works with OPB_EMC and PLB_EMC (uses more logic resources). The Flashwriter.tcl had to be modified from 8.1 to 8.2 because some of the functions changed. In MPMC2 architecture the Flashwriter fails but I was able to boot from flash if programmed from other HW (i.e. CoreConnect). If you find any more detail please let me know. Cheers, GuruArticle: 119888
On May 27, 8:10 am, Rob Barris <rbar...@mac.com> wrote: > Subject says it all - would like to hear from people using the SUZAKU > modules, how well they work, what toolchain / development hardware you > use, etc. > > http://www.atmark-techno.com/en/products/suzaku > > Especially interested in learning what the workflow is for iterating on > a design that has an embedded MicroBlaze, does the inclusion of the > soft-core CPU add a lot of turnaround time during recompilation of a > design into a bitstream? Or is that part mostly static and unlikely to > slow down debugging & iteration. > > And any pointers to appropriate JTAG interfaces for USB2 or Ethernet > would be appreciated too. > > Rob > > -- > Posted via a free Usenet account fromhttp://www.teranews.com I was also looking at that boards, but not purchased yet. I like the uClinux implementation (japanese are crazy about linux) and VMware development tools encapsulation. I would also like to hear a response from the users. Otherwise for JTAG use Xilinx PlatformCable USB, it is worth 150$. Cheers, GuruArticle: 119889
On 29 Mai, 10:55, "Claire Murphy" <clairemurphs...@hotmail.com> wrote: > Thanks for your responses ! I'm happy people replied. > > The I have checked and read 90% of what is available on the Xilinx ML505 home page (Antti's Link). But my problem is that none of these contain test projects. They all have some precompiled code that I can't post edit (i.e. ACE files). I can only load these directly via their CF card interface. your problem is you can not find information what is made available for you as example http://www.xilinx.com/products/boards/ml505/pcie.htm thrre are zip files with project verilog sources, http://www.xilinx.com/products/boards/ml505/ibert.htm there are design files as well http://www.xilinx.com/products/boards/ml505/bsb.htm this pages SHOULD be the most interesting, but as xilinx webmaster is on vaccation again ?! then this page is EMPTY ??? xilinx uhuuu, please fix this NOW so I really do not understand how come you can not load the ZIP files with project source code from the reference design pages for ML505??? the ML505 BSB is currently missing but there is lots of other demo projects for ML505, just take any of them and try proceed from there? AnttiArticle: 119890
Hi Claire, http://www.xilinx.com/products/boards/ml505/bsb.htm This will create a system for you that will test many of the components on the board. You will need EDK in order to implement the design. Just download the system and follow the information from the web link. The VHDL files for more peripherals that is used in the design is available in the EDK installation. The fee-based cores VHDL files are encrypted but the others are non-encrypted. Most peripherals are not fee-based. Göran This will show how to create a system "Claire Murphy" <clairemurphs223@hotmail.com> wrote in message news:eea6fec.2@webx.sUN8CHnE... > Thanks for your responses ! I'm happy people replied. > > The I have checked and read 90% of what is available on the Xilinx ML505 > home page (Antti's Link). But my problem is that none of these contain > test projects. They all have some precompiled code that I can't post edit > (i.e. ACE files). I can only load these directly via their CF card > interface. > > I have contacted Xilinx to see if they can give me a test project file > with some VHDL/VERILOG code in it so that I can start for there. > > I want to learn about updating the FPGA with some of my own code. But > first I want to have some code that I can get hands on experience with. > > Is there anything like a HELLO WORLD program for FPGAs ? I know it depends > on my board layout, but I do have the UCF file that has the pin > assignments. But putting this together in the project is starting to > confuse me. > > any help would be really appreciated ! > > Thamks, Claire.Article: 119891
> Is there anything like a HELLO WORLD program for FPGAs ? I know it depends on my board layout, but I do have the UCF file that has the pin assignments. But putting this together in the project is starting to confuse me. > > any help would be really appreciated ! > > Thamks, Claire. hello world (VHDL) LED <= '1'; /// NET LED = "xxx"; # please lookup ucf or manual are you looking for this? AnttiArticle: 119892
On 29 Mai, 11:31, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > Hi Claire, > > http://www.xilinx.com/products/boards/ml505/bsb.htm > > This will create a system for you that will test many of the components on > the board. Hi Goran that was quick - just a few minutes ago that URL opened an empty page !!! but now the EDK design is already there, nice ;) AnttiArticle: 119893
Thanks for everyone's help. You've pointed me in the right direction. I need to get my hands on EDK then it seems. btw. Goran <http://www.xilinx.com/products/boards/ml505/bsb.htm> in FireFox gives me errors ! Thanks Goran & AnttiArticle: 119894
Hallo, I have same problem and no solution for that. I have looked around whole Internet but with no effect. The problem comes also during EDK 8.2 PowerPC Tutorial in Virtex-4 journey that is supposed to be bug free. Is not it? Because I am going to operate with APU/FCM, the simulation feature is higly necessary for me! Do you have any idea how to solve the problem please? Thank for answer Jan KrakoraArticle: 119895
To specify the problem, I thought the "Fatal: (vsim-3348)" one. Sorry JanArticle: 119896
Hi, I want to implant a ICD into my Spartan 3 dev board. I need to program some Microchip PICs, and I wondered if I could use the FPGA, instead of buying an ICD board. Has someone already seen that ? Thanks, FabienArticle: 119897
On 29 Mai, 12:38, "fabien....@gmail.com" <fabien....@gmail.com> wrote: > Hi, > I want to implant a ICD into my Spartan 3 dev board. I need to program > some Microchip PICs, and I wondered if I could use the FPGA, instead > of buying an ICD board. > Has someone already seen that ? > > Thanks, > Fabien all is possible, but its faster and cheaper to get some ICD2 clone AnttiArticle: 119898
On Tue, 29 May 2007 07:40:21 +1200, Jim Granville <no.spam@designtools.maps.co.nz> wrote: >Brian Drummond wrote: > >> On Mon, 28 May 2007 07:34:24 +1200, Jim Granville >> <no.spam@designtools.maps.co.nz> wrote: >> >> >>>Frank Buss wrote: >>><snip> >> >> >>>If this runs slower, one of my pet ideas for FPGA cores, is to design >>>them to run from SerialFLASH memory. Top end ones (winbond) run at >>>150MBd of link speed, so can feed nearly 20MB/s of streaming code. >>>Ideally, the core has a short-skip opcode, as the jump in such memory >>>has a higher cost. >> >> >> Or a "four address instruction" like the Pilot Ace, with SerialFlash in >> place of a tube full of mercury? > >You've lost me ? >-jg In some designs of that era, three address instructions were common, source1, source2 and dest, very like the register addresses in a RISC. The innovation here was a fourth address; for the next instruction, coded to appear out of the delay line (or drum memory) just when it was needed. Important because the next location in program memory would have flashed past, and you'd have to wait for the memory's cycle time (or a whole drum revolution) before it came round again. Apparently it was a headache to hand-code for maximum performance, or "offered great scope for programmer ingenuity" :-) but worthwhile for heavily used code. (I believe it had the first floating point library, coded this way) But it could still be useful for streaming instructions from serial memory. - BrianArticle: 119899
On Tue, 29 May 2007 10:48:51 +1200, Jim Granville <no.spam@designtools.maps.co.nz> wrote: >Tommy Thorn wrote: >> On May 28, 12:40 pm, Jim Granville <no.s...@designtools.maps.co.nz> >> wrote: >> >>>Brian Drummond wrote: >>>>Or a "four address instruction" like the Pilot Ace, with SerialFlash in >>>>place of a tube full of mercury? >>> >>>You've lost me ? >>>-jg >> >> >> Me too, but this looks relevant >> >> http://research.microsoft.com/~GBell/Computer_Structures__Readings_and_Examples/00000213.htm > >Wow, that's quite impressive. A 1MHz clock, back in 1951! "it is not thought wise to design for higher speeds than this as yet" http://www.alanturing.net/turing_archive/archive/p/p01/P01-001.html (from 1945) May 1950 according to http://www.npl.co.uk/publications/metromnia/issue8/ which has some details. Apparently both code and data, but the "fourth address" was specifically to optimise code location. Surprisingly small, according to http://www.scienceandsociety.co.uk/results.asp?image=10303412 - Brian (wondering how many tubes you can fit in a CLB)
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