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The cheapest layout I have ever done cost $1200. That board had 6 IC's (one an XC4005) and ran at 1MHz, double sided, no internal layers. I think the total time I spent on that project from concept to finished design (meaning a production prototype was working to customer satisfaction) was about 100 hours. Maybe I'm not real fast, but this design seems MUCH more complicated, I can't imagine too many folks are able to crank it out in less time than I did this other project. BTW, I farmed out the layout of that project, so the hours of that designer are not included, just those that I spent interacting with her. Anyway, the short answer is, you're dreaming about the cost and the number of hours. Ben "Gregory C. Read" wrote: > > I agree that 30-40 hours is a little ridiculous. Especially since it is to > include the layout, which you didn't include in your list. > > -- > Greg > xxxgread@voicenet.com > (Remove the 'xxx' to send Email) > > S. Ramirez wrote in message ... > > Does anyone in this newsgroup realistically think that they can do the > >work below in 30-40 hours? Of course I would have to inquire to find out > >the details in order to make an estimate of what is really required. But > >just reading what this company wants, I see four main tasks: 1) design and > >schematic capture of the board, 2) design and HDL/schematic capture of the > >FPGA, 3) simulation of maybe the board and certainly the FPGA, and 4) lab > >testing/debug. I personally do not think that I can do all of the above > >tasks in 30-40 hours. > > At least they have a detailed block diagram. > > How about yous guys/gals? Can anyone do this work based on what's > >written below? > >-Simon Ramirez, Consultant > >-Synchronous Design, Inc. > > > > > > > >"Walt" <walt_white@southwestsoftware.com> wrote in message > >news:v98x5.31686$I6.182833@news1.rdc1.az.home.com... > >> Hello, > >> > >> We are looking for a freelance designer who can help us develop a > >> daughterboard module. This work will involve the schematic capture and > >> layout of the PCB in (preferably in Protel), and the programming of the > >> SpartonII FPGA. The hardware design will be based on a detailed block > >> diagram of the board that we provide, along with some key part numbers > and > >> other needed information. The board includes some A/Ds, D/As and a DDS. > >> The work should take between 30 to 40 hrs and can be done at your > >location. > >> > >> The project deliverables will be Protel design files, the FPGA design > >files, > >> and any documentation used to create the design. All rights and claims > to > >> any work on this project at all times is unequivocally the property and > >> intellectual property in origin and by any extension with all rights and > >> privileges reserved to Southwest Software & Systems LLC (3S). > >> > >> Payment for the work will be a flat fee of $2000.00 plus a royalty of > 5.0% > >> of the sale price for each board, and the boards will sell about $675ea > >and > >> volume is expected to be a few hundred (For example, assuming a 200 board > >> volume, the total payment for the hardware design would be: $2000.00 + > >0.05 > >> x $675.00/Board x 200Boards = $8,750). Additionally, there could be > >similar > >> follow-up designs. > >> > >> If you are interested and qualified to do this work, please contact me as > >> soon as possible, we are ready to begin immediately. > >> > >> Regards, > >> > >> Walt White > >> Southwest Software & Systems LLC > >> www.southwestsoftware.com > >> > >> > >> > >> > > > >Article: 25801
I agree with what you say, having sone a few design jobs for people, but any customer who pays the full hourly or daily cost of a custom design and agrees to this >(2) make sure you get him to sign >*your* contract, in which you keep your own IP is a fool. It is a recipe to get shafted (by the developer) - its happened to me a few times and now I insist on getting all sources, makefiles, all rights to the sources etc. Obviously the developer is free to reuse the stuff for other people, I won't mind that. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 25802
sounds a bit high to me. What did you put in for how frequently nodes are switching? Gary Watson wrote: > > OK, does 1300 mW of 2.5 volts sound about right for a XC2S150 which is > pretty much filled up with a 8 bit microprocessor and its software, plus a > bunch of glue logic, running at 20 MHz? That's the output of the Xilinx > power estimator program, if I understand how to use it. > > -- > > Gary Watson > gary2@nexsan.com > Nexsan Technologies Ltd. > Derby DE21 7BF ENGLAND > http://www.nexsan.com > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:39C69C1B.AD13EF81@xilinx.com... > > Gary, > > > > It is trivial, really. > > > > Go to the power estimator page, and fill out the estimator with as many > educated > > guesses as you can for a V150. Be really over conservative (more IO's, > more > > CLB's, higher percentage of switching, etc). > > > > Look at how much current is predicted. > > > > http://www.xilinx.com/cgi-bin/powerweb.pl > > > > Make sure you are not exceeding the power dissipation for the device. > > > > The XC2S150 will be less current that the 150 due to the process > improvements. > > We will have more data on that it the future. > > > > The estimator is based on actual lab measurments of designs. It is a vast > > improvement over any power estimation for FPGAs I have seen before. We > > correlate its results against a number of customer reference designs, > > > > Austin > > > > Gary Watson wrote: > > > > > I know it's difficult to predict the power requirements of Xilinx parts, > but > > > what's a safe 2.5V regulator to use for the internal supply of a > XC2S150? > > > The data sheet is most unhelpful in figuring this out. Since I plan to > roll > > > out this product in phases over the next year, I can't say what all my > > > internal logic might be doing down the road, so I'm happy to over-spec > the > > > regulator to a reasonable degree. > > > > > > By the way, I'm getting quoted over 10 UK pounds ($14) for the config > prom > > > for this puppy (XC18V01S20C). Is there a cheaper way to do this? This > prom > > > increases the cost of using a Spartan II by 50%! > > > > > > -- > > > > > > Gary Watson > > > gary2@nexsan.com > > > Nexsan Technologies Ltd. > > > Derby DE21 7BF ENGLAND > > > http://www.nexsan.com > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25803
I'd be willing to host it on my website if we can get some synergy creating the material. eml@riverside-machines.com.NOSPAM wrote: > > Thanks for the corrections on Synplify sync reset. What I should have > said was that there was a problem with coding up both a clock enable > and a sync reset on a F/F; I had a meeting with a rep in May who told > me this (haven't tried it myself), which means that you can't code up > 6-in functions on a Virtex F/F. On the other hand, you can do this > with Spectrum, and it can be very useful. > > This type of issue comes up fairly frequently, but there's no simple > way to find out if a particular synthesiser supports feature X on > family Y, or if it messes up a particular code template, or generates > twice as much hardware as required, or whatever, short of trying it > for yourself. > > It occurs to me that it would be useful to pool the information that > we do have, and to find a structured way of getting the information > that we don't have, so that this information gets into the public > domain. This would involve, as a starting point, writing or collecting > various code templates, passing them around to anyone who has the > appropriate tools and is willing to help (possibly anonymously), and > collecting the results on a website. > > Is anyone interested in doing this? If there's a critical mass, I > could try setting up a mailing list and a web site and repository, > hopefully using existing resources from eda.org, seul.org, > sourceforge, or whatever. > > The sort of information that I think would be useful would be, for a > given synth and a given family: > > * support of global resources such as resets and clocks > * support for architecture features such as clock enables, (a)sync > resets, extra CLB muxes, carry chains > * language-specific features: language conformance, user-defined and > vendor-specific attributes, standard and unusual templates, > initialisation functions > * support for low-level design constraints > * whatever you can think of > > There's a potential issue with vendors, who may believe that > publishing this information contravenes an individual licence > agreement. However, these tend to explicitly prohibit "benchmarking" > operations, rather than anything else. Benchmarking, as such, wouldn't > necessarily be covered. Most of the issues covered above are simply > functionality issues. > > What do you all think? Anyone willing to help? > > Evan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25804
I came to the same conclusion looking at the code, but I am far from fluent in Vital. So riddle me this batman: why does turning off the timing checks seem to make the problem go away? Perhaps I am just fooling myself (now that's a s scary thought) Andy Peters wrote: > > Joel Kolstad wrote: > > > > "K. Orthner" <korthner@hotmail.nospam.com> wrote in message > > news:8FAEA273Dkorthnerhotmailcom@158.202.232.7... > > > Joel, I'm not sure about this, but won't turning off the "timing checks > > on" > > > generic only disable the timing checks? What it won't do is prevent the > > > instantiated components from having delays. > > > > > > Or am I mistaken here? > > > > Ummm... that's a very good question. I'm off in this nasty place known as > > San Jose at the moment, but from recollection... I think you're right that > > the instantiated components will still have delays, but I also think that > > turning timing checks off will solve Andy's original problem in that it's > > the timing check that's causing everything to be one clock off in the first > > place. > > > > Hopefully someone else can chime in to confirm this. With my design, > > turning timing checks off made everything "work," but there definitely is > > still a 100ps delay on a ClkBufGDLL that is instantiated. > > Joel, > > Disabling the timing checks does NOT eliminate the 100 ps (actually, > 0.10 ns, which you might think would be the same thing, but you'd be > wrong) delay. If you look closely at the model, there's a wire delay > for all of the input signals (but not the clock); that delay does not go > away if you disable timing checks. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25805
In article <39c883c9.10575851@news.dial.pipex.com>, eml@riverside-machines.com.NOSPAM wrote: > (2) make sure you get him to sign > *your* contract, in which you keep your own IP, (3) make sure your > contract specifies a staged payment scheme, and that you're never in a > situation in which you've done *any* work without being paid for it, > (4) make sure you get paid more if the spec changes, Could you possibly publish a sample of such a contract? And one more question to all. It seems that there is a lot of people here who are involved in some freelance work. How did you get your first contract? I would like to earn some extra cash by doing freelance work (hardware/FPGA design) but I can't find any! Anyone has too much and wants to share? :) Thanks in advance, /Mike Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25806
most of the synthesis tools generates schematics. try using the FPGA express as a stand alone, you should be able to get the schematic. regard spyng erika_uk@my-deja.com wrote: > hi, > > can F2.1i generate the schematic from vhdl (or edif) entry. > If no, is there any tool which does so > > Regards > > --Erika > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 25807
This problem is very similar to one I am having, but i am using an xchecker. My problem only occurs with JTAG, the correct bitgen parrameters are used, and the correct mode is selected. The JTAG programmer software says the programing was succesful, but done does not go high. (Done does go high if hardware debugger is used).Article: 25808
Stephen, Is there a chance that as soon as configuration is complete, that the JTAG clock stops? (I'm not fmiliar with XChecker.) After the configuration is compelte, the FPGA needs a couple of extra clock cycles to initialize itself and set the DONE output. In the bitstream generation stage, after place and route, you can select how many clock cycles until DONE is high. Hope this helps. _Kent stepheningram@hotmail.com (Stephen Ingram) wrote in >This problem is very similar to one I am having, but i am using an >xchecker. My problem only occurs with JTAG, the correct bitgen >parrameters are used, and the correct mode is selected. The JTAG >programmer software says the programing was succesful, but done does not >go high. (Done does go high if hardware debugger is used).Article: 25809
Hi, I have the same INIT Problem too. I' m using FPGA-Express 3.3 and tried to compile the sample code from XILINX XAPP 130. My EDIF-Netlist doesn't contain the initialization code and therefore the translate tool warns me about some undefined properties. I think this belongs to the Synopsys dc_script_begin preprocessor directive. I'm not sure if it is supported by FPGA-Express 3.3. Does anybody know? Thanks Thomas "Gerhard Griessnig" <grie@sbox.tu-graz.ac.at> wrote in message news:39AE25D3.A4E1D696@sbox.tu-graz.ac.at... > Hi, > > I have a problem concerning the usage of Foundation 2.1i, SYNOPSIS, > Virtex300 and Block RAM. The RAM is initialized with attribute INIT_00 > ... > > The initialization with attributes (INIT_00, ..) works fine after > Implementation (timing simulation). But after Synthesis (without > Implementation) the Ram isn't initialized > and the simulator doesn't show any changes (all mem locations at 0). It > seems like synthesis ignores the attributes. > > > A second problem: > > How can I force SYNOPSIS to use Virtex's block ram. The code fragment > for SYNPLICITY looks like this: > > architecture block_ram of block_ram is > > type mem_t is array (0 to 31) of std_logic_vector(199 downto 0); > > signal bk_ram : mem_t; > attribute syn_ramstyle of bk_ram : signal is "block_ram"; -- key to > force usage of block ram in virtex devices. (synplify tool) > : > > begin > : > bk_ram(conv_integer(ADDR_i)) <= D_i; > > : > > How can above code be adapted to SYNOPSIS? > > > THANKS Gerhard >Article: 25810
Hi Ray, I think I put in about 25%, which I suppose is a bit on the high side. The thing is, there's only three chips on this board, the Xilinx FPGA, the config prom, and an unrelated chip which runs on 3.3v. I have tons of 5 volts available, so I just figured to use a LM3962 which is good for 1.5 amps of 2.5 volts, and is dirt-cheap and readily available. I just want to find a regulator that's likely to work for pretty much anything I decide to throw into the FPGA... -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com "Ray Andraka" <ray@andraka.com> wrote in message news:39C94E57.CF9A9248@andraka.com... > sounds a bit high to me. What did you put in for how frequently nodes are > switching? > > Gary Watson wrote: > > > > OK, does 1300 mW of 2.5 volts sound about right for a XC2S150 which is > > pretty much filled up with a 8 bit microprocessor and its software, plus a > > bunch of glue logic, running at 20 MHz? That's the output of the Xilinx > > power estimator program, if I understand how to use it. > > > > -- > > > > Gary Watson > > gary2@nexsan.com > > Nexsan Technologies Ltd. > > Derby DE21 7BF ENGLAND > > http://www.nexsan.com > > > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > > news:39C69C1B.AD13EF81@xilinx.com... > > > Gary, > > > > > > It is trivial, really. > > > > > > Go to the power estimator page, and fill out the estimator with as many > > educated > > > guesses as you can for a V150. Be really over conservative (more IO's, > > more > > > CLB's, higher percentage of switching, etc). > > > > > > Look at how much current is predicted. > > > > > > http://www.xilinx.com/cgi-bin/powerweb.pl > > > > > > Make sure you are not exceeding the power dissipation for the device. > > > > > > The XC2S150 will be less current that the 150 due to the process > > improvements. > > > We will have more data on that it the future. > > > > > > The estimator is based on actual lab measurments of designs. It is a vast > > > improvement over any power estimation for FPGAs I have seen before. We > > > correlate its results against a number of customer reference designs, > > > > > > Austin > > > > > > Gary Watson wrote: > > > > > > > I know it's difficult to predict the power requirements of Xilinx parts, > > but > > > > what's a safe 2.5V regulator to use for the internal supply of a > > XC2S150? > > > > The data sheet is most unhelpful in figuring this out. Since I plan to > > roll > > > > out this product in phases over the next year, I can't say what all my > > > > internal logic might be doing down the road, so I'm happy to over-spec > > the > > > > regulator to a reasonable degree. > > > > > > > > By the way, I'm getting quoted over 10 UK pounds ($14) for the config > > prom > > > > for this puppy (XC18V01S20C). Is there a cheaper way to do this? This > > prom > > > > increases the cost of using a Spartan II by 50%! > > > > > > > > -- > > > > > > > > Gary Watson > > > > gary2@nexsan.com > > > > Nexsan Technologies Ltd. > > > > Derby DE21 7BF ENGLAND > > > > http://www.nexsan.com > > > > > > > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com >Article: 25811
I'm having trouble installing the CAE Libraries under Solaris. The
progress indicator has been sitting still for 24 hours, but the
advertisement banners are running. I hate bloatware stuff like
netscape/java for installation when a /bin/sh would have done the job.
All I want is some ASCII files (Synopsys and Cadence libraries) off
the CD.
Anybody else experienced similar problems?
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 25812
Mike,
Typically I never give away work to someone that I don't know well.
This is simply to protect my reputation.
I can understand why you can't find any freelance work, though. It's
staring you right in the face, and you don't even know it!
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
> And one more question to all. It seems that there is a lot of people
> here who are involved in some freelance work. How did you get your first
> contract? I would like to earn some extra cash by doing freelance work
> (hardware/FPGA design) but I can't find any! Anyone has too much and
> wants to share? :)
>
> Thanks in advance,
>
> /Mike
Article: 25813This is a multi-part message in MIME format. --------------19DF1CBC557F74BBB06783C1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello, is there any Support for performing Incremental routing using Xilinx Foundation 3.1 series tools. I know we can do a modular based design and perform Incremental synthesis. Thanks and regards Anup --------------19DF1CBC557F74BBB06783C1 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:+61-7-38761962 tel;work:+61-7-33658849 x-mozilla-html:TRUE url:www.elec.uq.edu.au/~anup org:University of Queensland;Computer Science & Electrical Engineering version:2.1 email;internet:anup@elec.uq.edu.au adr;quoted-printable:;;47/401, Dept. of CSEE, UQ, =0D=0A=0D=0A;St.Lucia, Brisbane ;Queensland;4072;Australia fn:Anup end:vcard --------------19DF1CBC557F74BBB06783C1--Article: 25814
eml writes:
>> First bit: source - byte 5 - bit0
>> Last bit: CRC - byte 0 - bit7
>>
>> Is above correct?
> I don't think so. The addresses are Ok, with the first bit (byte 5/bit
> 0) being the I/G bit. The length field also goes high byte first. The
> bits of the CRC polynomial are shifted out in the order x**31 first,
> x**0 last. I would call the last bit out byte 0 bit 0, but I guess it
> could be called byte 0 bit 7 by some.
Well at least in my MII code, the CRC is shifted right as it is shifted
out, i.e. bit 0 first. I guess it depends how you define the CRC. I've
seen it defined both ways around. Here's one I use that definitely works:
macro expr crc32_initial = (unsigned 32) 0xffffffff;
macro expr crc32_polynomial = (unsigned 32) 0xedb88320;
macro expr crc32_remainder = (unsigned 32) 0xdebb20e3;
macro expr crc32_update (crc, bit) =
((unsigned 32) crc >> 1) ^ ((crc [0] ^ bit) ? crc32_polynomial : 0);
macro expr crc32_update_4_bits (crc, bits) =
(((unsigned 32) crc >> 4)
^ ((((crc [0] ^ bits [0]) ? (crc32_polynomial >> 3) : 0)
^ ((crc [1] ^ bits [1]) ? (crc32_polynomial >> 2) : 0))
^ (((crc [2] ^ bits [2]) ? (crc32_polynomial >> 1) : 0)
^ ((crc [3] ^ bits [3]) ? (crc32_polynomial >> 0) : 0))));
enjoy,
-- Jamie
Article: 25815Hi Gary, I want to read a data sheet on the LM3962. I went to National Semi and only found a LP3962. http://www.national.com/pf/LP/LP3962.html How does this differ from the LM ? Who makes the LM. Also what are you doing about the VCCO ? DanArticle: 25816
We have a synthesizable HC11 CPU core available for download. See http://www.gmvhdl.com/hc11core.html for details. --Scott Thibault Green Mountain Computing Systems, Inc. http://www.gmvhdl.comArticle: 25817
Sorry, typo, meant a LP not LM. Am using the same type of part for 3.3v for VCCO... -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com "Dan" <daniel.deconinck@sympatico.ca> wrote in message news:QDoy5.278783$1h3.6003390@news20.bellglobal.com... > Hi Gary, > > I want to read a data sheet on the LM3962. > > I went to National Semi and only found a LP3962. > > http://www.national.com/pf/LP/LP3962.html > > How does this differ from the LM ? Who makes the LM. > > Also what are you doing about the VCCO ? > > Dan > > > >Article: 25818
Rick, It sounds like you might only have the design entry and synthesis tools installed and not the fitter tools. Once you've installed the fitter tools, the default device will still be 'virtual device' but you can right click on it and change it. And yes, we'll still talk to you on the phone. :) 1-800-255-7778. Carl rickman wrote: > "Tobias F. Garde" wrote: > > > > rickman wrote: > > > > > > I am trying to get the Xilinx Web Pack up and running on my machine and > > > am having trouble. > > > > > > The first problem I had was the fact that the install did not seem to > > > handle properly the path in the shortcut as I put it under the "Program > > > files" directory and it needed quotes around it to be able to > > > incorporate the space in the path. > > > > > > The next problem I have is trying to access the help. Many of the items > > > in the help window cause errors like "Can not find or run the program or > > > file 'dkxilinx.hlp'". It also could not find a current version (or any > > > for that matter) of "hhcntl.ocx". > > > > > > > Rick, > > > > The problems may still be related to your - very unorthodox :) - choice > > of install path for the Xilinx S/W. Even though the installer accepts a > > path with spaces in it, the S/W does not necessarily support it. I had > > that problem when installing the 3.1i S/W. > > > > I recommend that you check if the missing files are actually present on > > your system. If this is the case, an uninstall followed by a new install > > to the default path may do the trick. BTW, in my case, the uninstall was > > a bit difficult, because the uninstall info could not be found due to > > the spaces in the path... > > > > Tobias F. Garde > > ASIC Development Engineer > > Tellabs Denmark A/S > > I understand that. In fact I gave up and tried to uninstall the > software, but the uninstaller has the same problem with the path! So I > just deleted it and installed it in the default directory (which I had > to enter since the new default was to the "Program Files" directory! It > is simply amazing how little QC there is in this stuff. > > But the bottom line is that I still could not get the device types to > show up. So I gave up and reinstalled Foundation 1.5i from an old job I > had done a couple years back. That runs, but it won't let me synthesize > my VHDL. So I am back to square one. At least I can syntax check the > code. > > I expect my customer to provide a copy of the current tools at which > point I will be able to get Xilinx involved (assuming they even talk to > you on the phone anymore). > > I guess I could try to talk the customer into using the Lucent parts. At > least I can get the tools to work in less time than it takes to get the > design to work. > > Don't mind me, I am just frustrated. I'll be ok tomorrow. :-( > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 25819
I'm looking for a simple uart core. Can anyone point me to a free core that works? I'm targeting a Spartan II, and using VHDL. The only thing I found at Xilinx's site was something for a Coolrunner. The code was not device specific, so I tried it out. Unfortunately, it is woefully inadequate (the parity doesn't work right, not completely synchronous, data is inverted, etc.). I have the miniuart from opencores.org, but it is way more than I need. I going to pare down the miniuart, but thought I'd check to see if there was anything else available. Thanks, JohnArticle: 25820
Have you looked at what coregen offers? There are several different UART cores listed for Spartan and at least one for Virtex, which I believe should work in Spartan II. They are not free though... -- ============================ Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: 1 (613) 271-0044 ext.231 Fax: 1 (613) 271-3007 http://www.squarepeg.ca John Fielden <john.fielden@abcmotorola.com> wrote in message news:8qdih8$58n$2@schbbs.mot.com... > I'm looking for a simple uart core. Can anyone point me to a free core that > works? > > I'm targeting a Spartan II, and using VHDL. The only thing I found at > Xilinx's site was something for a Coolrunner. The code was not device > specific, so I tried it out. Unfortunately, it is woefully inadequate (the > parity doesn't work right, not completely synchronous, data is inverted, > etc.). > > I have the miniuart from opencores.org, but it is way more than I need. I > going to pare down the miniuart, but thought I'd check to see if there was > anything else available. > > Thanks, > > John > >Article: 25821
One time, I found that cleaning the CD helped.
In article <ylueaed2rnsv.fsf@scimba.dolphinics.no>,
petter@scimba.dolphinics.no wrote:
>
> I'm having trouble installing the CAE Libraries under Solaris. The
> progress indicator has been sitting still for 24 hours, but the
> advertisement banners are running. I hate bloatware stuff like
> netscape/java for installation when a /bin/sh would have done the job.
> All I want is some ASCII files (Synopsys and Cadence libraries) off
> the CD.
>
> Anybody else experienced similar problems?
>
> Petter
> --
>
________________________________________________________________________
> Petter Gustad 8'h2B | (~8'h2B) - Hamlet
http://www.gustad.com
> #include <stdio.h>/* compile/run this program to get my email address
*/
> int main(void) {printf ("petter\100gustad\056com\nmy opinions
only\n");}
>
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Article: 25822EOMArticle: 25823
I've finally gotten sick of just simulating a CORDIC block, and synthesized it to a Xilinx XC4010XL-3 FPGA. I'm using some fairly ancient Xilinx Foundation Series 1.5 software (not even 1.5i.) But I've run into a slight snag. The CORDIC algorithm is supposed to be 'fast' thanks to a shift/add iterative cycle (no multiplication.) I synthesized to an Xess XS40-010+ board, and looked at the placement report. To my surprise, roughly 50% of the CORDIC's area is consumed by the arithmetic-right-shifter. Is this correct?!? The CORDIC block works, but the resource-consumption was way way over my estimate. (I admit I have *no* prior experience with FPGA.) In short, my 8-bit CORDIC block + VGA-display circuit consume 96% of the XC4010XL's CLBs. My cordic block uses a single 8-bit adder (with muxes on each input to rotate between the X,Y,Z accumulators.) The inputs and outputs on the adder are registered, of course. With some pipelining, the adder is never idle. Here's where the shifter sits : | X or Y | | adder input| | register | ---> arithmetic shifter -> XOR-array -> | register | (The XOR-array is used to implement subtraction.) The shifter itself has 8-bit data input and output. A 3-bit 'rotate' word specifies the #bits to right-shift. The upper bits are filled with 0 or 1, depending on the input-data's sign (MSB.) The shifter is entirely combinational logic. Are FPGA architectures just not efficient at implementing single-cycle (barrel) arithmetic-shifters? I'm about ready to redo the shifter using a shift-register + counter (sequentil logic implementation.) This maps better, but takes multiple-cycles to compute.Article: 25824
Hello, I have a problem with simulation of model after implementation. It's a model of tri state data bus in verilog. The code is below: module DataBusBuffer(D,D_IN,READ_C0,READ_C1,READ_C2,WRITE_2_C0,WRITE_2_C1,WRITE_2_C2,WRITE_2_CWR,D_OUT); inout [7:0] D; input [7:0] D_IN; input READ_C0; input READ_C1; input READ_C2; input WRITE_2_C0; input WRITE_2_C1; input WRITE_2_C2; input WRITE_2_CWR; //----------------------------------DECLARATION of OUTPUTS----------------------------------------- output [7:0] D_OUT; //------------------TRANSFER from INTERNAL BUS to DATA BUS---------------------------------------------- assign D=(READ_C0 || READ_C1 || READ_C2) ? D_IN : 8'bz; //------------------TRANSFER from DATA BUS to INTERNAL BUS---------------------------------------------- assign D_OUT=(WRITE_2_C0 || WRITE_2_C1 || WRITE_2_C2 || WRITE_2_CWR) ? D : 8'bz; endmodule I do not know how write a testbench into model after implementation.I have a testbench, but it works only for behawioral simulation. Please about help P.S If you can help me, I will send you the files, because i do not know how attach the files into post: data_bus_im.v -model after implement data_bus_im.sdf data_bus_s.v - model after synthesis data_bus.v -model behavioral tb_data_bus.v - testbench Tomek
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