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What? are you trying to suggest that software developers are really just like normal people??I find that a bit hard to believe.Article: 79901
Antti, What is M, and what is D? Austin Antti Lukats wrote: > Hi > > I am using FX only: > > Inst_m125: m125 PORT MAP( > CLKIN_IN => sysclk, > CLKFX_OUT => clk, > CLKIN_IBUFG_OUT => open, > CLK0_OUT => open, > LOCKED_OUT => open > ); > > V4LX25-10, in Xilinx Clocking Wizard > setting "Max speed" > fin fout > LOW 24-120 24-160 > HIGH 120-280 160-280 > > setting "Max Range" > fin fout > LOW 16-84 16-112 > HIGH 84-168 112-168 > > as you see the maximum frequency when using > 100MHz reflck in is 168MHz ! for -10 speed grade > actually its 160 as there is no M/N ratio that producdes 168 > > :( > > Antti > > > > > > > "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag > news:%hJTd.23$vt.355@news-west.eli.net... > >>From p 29 of the DS302 v1.4 Virtex 4 Data Sheet: DC and Switching >>Characteristics, the output clocks from the DCM in the *high frequency > > mode* > >>shows 210-280 MHz capable FX outputs (for the slower -10 device) to pick > > up > >>where the *low frequency mode* drops off. The input for the high > > frequency > >>mode can be as low as 50 MHz if the DFS mode is all that's used. >> >>100 MHz in, 100*M/N out up to 280 MHz in the -10 device. >>Check to make sure you're 1) working in HF mode and 2) you're not using > > the > >>standard outputs - just the DFS. >> >> >>"Antti Lukats" <antti@openchip.org> wrote in message >>news:cvnl3m$102$01$1@news.t-online.com... >> >>>Hi >>> >>>there are lots of PR news about how much better, etc.. >>> >>>but doing a very simple task with V4 I was really surprised: >>> >>>to test max clock for an XC9572XL-5 (cuctomer needs 125MHz) >>>I used V4 development board as programambel clock source. >>>100Mhz comes in, goes to DCM and goes out. >>>nothing else >>> >>>with V4LX25-10 the maximum frequency that the DCM was possible to set > > was > >>>168MHz! >>> >>>changing the speed grade to -11 allowed to set fout to 180MHz, >>>but even that seems kind low for the performance leader ??? >>> >>>The DCM could generate a max freq of 315MHz, but that case the input >>>frequency >>>is required to be more than 120MHz, and my development board has only >> >>100Mhz >> >>>oscillator useable :( >>>hopefully I am missing something and higher frequencies are actually >>>possible too. >>> >>>ok this time the 180MHz was sufficient for our testing - >>> >>>XC9572XL-10 (max freq in datasheet 125MHz) did work very well >>>until input freq 150Mz, with 180MHz the first flip started to divide by > > 3 > >>>surprisingly deliver very clean 60MHz clock. >>> >>>Another "nice" thing the first XC95 PLD we used was not supported by >>>Impact 6.3 !!! Xilinx has silently dropped support of some PLDs from >>>latest ISE/impact - the XC9536 device was recognized as >>>XC9536_unsupported !! by impact and it did not program it. >>>funny is that the development board where this PLD was also >>>holds a large logo of Xilinx, ah well just another thing to know... >>> >>>Antti >>> >>> >> >> > >Article: 79902
Antti, Would not be the first time I have seen a bug in the wizard. Austin Antti Lukats wrote: > "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag > news:cvnovq$bjl4@cliff.xsj.xilinx.com... > >>Antti, >> >>Was this in the software tools alone? Sounds like you tried it on a pcb? > > > thanks for long answer, well I used the lazy approuch ie Xilinx Clock Wizard > and in that tool its not possible to get more than 160MHz from 100MHz input. > > in order to get around it pumped up the device speed grade to higher and > selected > the maximum that was possible (that was 180MHz) > > and I did measure that 180MHz as output signal and used that signal to feed > a PLD > I did not try to set the DCM params by hand. > so I dont know how much the chip actually could perform, I do belive that it > could way higher than the 160MHz (or 315) > > its just that the Xilinx Clocking Wizard made me wonder big time why I cant > enter values for higher frequncies when I want too! There should be an > super-user checkbox that allows to enter out spec values as well. > > Antti > >Article: 79903
Hello to anyone! I'm designing SD host controller core and I have some question to someone who known about it. I've made SD controller with 1 bit data line and I want to make 4 bit data line interface with SD, but all the same after sending to SD Card ACMD6, data received by 1 wire. I'm doing next: (wait for 90 clock) -> CMD0 -> CMD55 -> ACMD41 (with repeate) -> CMD2 -> CMD3 -> -> CMD7 (with RCA) -> ACMD6 (4 bit) -> CMD17 One date line mode does work but 4 data line doesn't work. Any ideas? Thanks!Article: 79904
On Fri, 25 Feb 2005 09:34:35 -0800, Austin Lesea <austin@xilinx.com> wrote: >Rick, > >You have my answer associated with the right question, yes. > >Further, loading does not matter as we are fully buffered everywhere. >Load as much as you like, delay does not change (on the BUFG)by more >than a few tens of ps. Thanks - RickArticle: 79905
"Antti Lukats" <antti@openchip.org> wrote in message news:cvioa6$n6q$03$1@news.t-online.com... > Hi > > just a few FPGA related news > > Actel > > ProAsic PA3 Engineering samples PA3 250 (not 600E !!) will be available Q3 > NO WAY to get any engineering silicon before that. > Q3 may be the last day of Q3 so Q4 end of year seems as more realistic. > production volumes few weeks later ? > > PA4 (PA3+) - even as it was on the roadmap more than years ago > the roadmap is no less clear than before, eg no fixed plans at all > > Altera > > Was there! This time there really was Altera directly and not some rep > pretending to be Altera. I got a look at the Cyclone Cubicum and did > see what I expected to see, halfway hidden was the FTDI chips that > is used in Altera USB Blaster. I am 99% sure thats FT245BM so > making DIY Altera USB Blaster cable should only a matter of > writing the VID/PID to the EEPROM and connecting JTAG to the FT245 > ok, maybe a litte more > > at EBV stand there was PCIexpress board with Altera GX on it, but > when I wanted to know is it available for purchases then the answer > was YES! After asking second time another guy did check it out for > me and then it was not so much YES any more, there was no answer > it will be inquired, etc... most likely not available. > > There was also a real nice Altera Cyclone 2 board with > 3 USB host and 1 USB device connectors and lots of other things > price EUR 249 should be available already > > Lattice > > was there in a tinybooth. > but nevertheless was interesting - one thing new to me was the > Block RAM in 5000M PLDs so far I have never paid attention to that. > > the "xp" thing, well all unofficial, the best info I was able to squeeze > was > that a press announcement about it is expected in less than 2 months > and that the xp is basically EC/ECP with added Flash on chip, there > should be possible to indirect self reprogramming by connecting the > JTAG pins externally back to the FPGA fabric. > > ------- > overall: lots of embedded linux stuff, > pretty nice is linux inside RJ45 jack (price 99EUR) > > Philips: > as second manufacturer has 3by3 mil 10 pin MLP packaged > microcontroller (SiLabs was first long time ago) > > Ti > > PTH04070w: 3A SMPS module 11 by 14 mm, pretty nice for FPGA VCCINT > > > Antti > > Antti, Did you check out the ERIC5 core from Entner Electronics? How did it look? I'm pretty sure they had a booth there. Thanks, KenArticle: 79906
"Jan Bruns": >is there a way to get delay-info on resource-basis? >I'd like having the output of "XDL -report -pips" >annotated with delay(functions). The purpose is to identify >fast resources to ease up the design of macros such as those, >XST tries to detect when syhthesising HDL and to gain my personal >learning-curve about fpga-design (I don't see HDL-compilers do this=20 >for me). >I'm tired of writing just-a-few-slice-designs, wait a minute or >two for the toolchain to print out a result, then modify the test, >and again wait for the toolchain, and all this just to find out, what=20 >leaving a carry-chain or whatever might cost. >Any ideas, how to get "XDL -report -pips" annotated with useful >delay-estimates? None? Remember the purpose is to rapidly find rough estimtes for delays of small, clearly defined circuits within an fpga (so don't take that ASCII-file to serious). I mean, it might be easy to classify wires by length and the number of pips directly on a wire. So it might even be easy to=20 find a roughly estimated phsical model of a net, given that driver's and line's (strength, capacitance per length-unit,...) properties (and maybe such of the inputs) are given. So maybe some physical parameters about routing resources would do, for that ASCII-file. Gruss Jan BrunsArticle: 79907
On Fri, 25 Feb 2005 10:03:11 -0800, "RobJ" <rsefton@abc.net> wrote: >I've also tried inluding a verilog >description of the port list for the block in the project, which ISE >recognizes and then the instantiated block is no longer unkown, but when I >run XST I get some bizarre errors. Should work Ok; XST doesn't need to know anything about your module apart from it's I/F. How are you declaring the module in your Verilog code? What error messages are you getting?Article: 79908
I can't really use pipelining here. The MAC is all combinationnal; i receive inputs at time 0, and I need an answer by time x. I don't see how pipelining would help. Thanks, DaveArticle: 79909
Wierd story, been along time since I went to junk stores, l used to buy Plasma display tubes, TTL & cmos rams 20yrs ago but after getting into VLSI (at Inmos on the Transputer) never actually built anything outside the chip. But FPGAs allow an old VLSI guy without his own fab to do something only a company with a Fab could do 5-10yrs ago. I contemplated trying to turn MicroBlaze and perhaps Nios into Transputer replacements by adding on extra HW but came away thinking it would be better to start over with sail set in the right direction day 1. The benchmarks posted in the "NiosII Vs MicroBlaze thread" for Leon, MicroBlaze & Opencores 1200 would seem to justify my pt but I am not complete yet. Good luck with your MPP endevours too! regards johnjakson at usa dot com The Transputer Will be back (T2 movie)Article: 79910
gretzteam wrote: > I can't really use pipelining here. The MAC is all combinationnal; i > receive inputs at time 0, and I need an answer by time x. I don't see > how pipelining would help. What is x? If x is one clock cycle then you need either faster logic or a lot more of it. I believe this can be done easily with a three cycle pipeline, so that you get an answer out every cycle, which each one taking three cycles. -- glenArticle: 79911
I am trying to use a Spartan 3 in my design. The power requirements and current requirement are going to vary according to applications. According to a TI website for Sparatan 3, the VCCINT (1.5v) has the current range from 300mA to 10A, and for VCCO(3.3V) the current range is from 50mA to 3A. For VCCAUX(2.5V) the current is maxed at 300mA. Has anyone used such high currents when using a Spartan 3. I will be implementing soft-cores and will be utilizing most of the core. So I am expecting a heavy load on the FPGA. I just wanted to be able to estimate the current that would be required, so I can choose the correct Voltage Regulators. Many of the voltage regulator specify the current limits as 1-2.5A, which may not meet the requirement for upper limit of the current requirement for Spartan -3. I did post a previous topic regarding chossing a voltage regulator,but I wanted to be more specific on the issue at large. Thanks for your help. -YajuArticle: 79912
Yaju, Use our Power Prediction web tool to esitmate your actual power. The 'problem' with FPGAs, is that they will use whatever power you tell them to: so we (and TI) have no idea how much power they will need to do your job (after all, it is your job to do, and we don't know what that is). http://www.xilinx.com/cgi-bin/power_tool/power_Spartan3 Austin Yaju N wrote: > I am trying to use a Spartan 3 in my design. > > The power requirements and current requirement are going to vary > according to applications. According to a TI website for Sparatan 3, > the VCCINT (1.5v) has the current range from 300mA to 10A, and for > VCCO(3.3V) the current range is from 50mA to 3A. For VCCAUX(2.5V) the > current is maxed at 300mA. > > Has anyone used such high currents when using a Spartan 3. > > I will be implementing soft-cores and will be utilizing most of the > core. So I am expecting a heavy load on the FPGA. I just wanted to be > able to estimate the current that would be required, so I can choose > the correct Voltage Regulators. Many of the voltage regulator specify > the current limits as 1-2.5A, which may not meet the requirement for > upper limit of the current requirement for Spartan -3. > > I did post a previous topic regarding chossing a voltage regulator,but > I wanted to be more specific on the issue at large. > > Thanks for your help. > > -Yaju >Article: 79913
Yaju N wrote:
> I will be implementing soft-cores and will be utilizing most of the
> core. So I am expecting a heavy load on the FPGA. I just wanted to be
Which Spartan-3? A -1500 part will consume a lot more current than the
-200 part for designs which use "most of the core."
What clock frequency? Check out the Xilinx power utility (online).
What type of utilization? SRL functionality consumes more power than
standard LUT.
2.5v rail should be easier to estimate if you're only using it for
VCCAUX. (I think) it's only used for the DCMs and configuration logic.
Play with the power utility to determine ballpark figures or even upper
bounds. It'll give you a general feel for how the thing will be sucking
down current.
Jake
Article: 79914"Evan Lavelle" <abuse@[127.0.0.1]> wrote in message news:5n2v11hkdm9sej3im4h4cc4e25rsfopfah@4ax.com... > On Fri, 25 Feb 2005 10:03:11 -0800, "RobJ" <rsefton@abc.net> wrote: > >>I've also tried inluding a verilog >>description of the port list for the block in the project, which ISE >>recognizes and then the instantiated block is no longer unkown, but when I >>run XST I get some bizarre errors. > > Should work Ok; XST doesn't need to know anything about your module > apart from it's I/F. > > How are you declaring the module in your Verilog code? What error > messages are you getting? Hi Evan - Here how the NGO module is instantiated: ip_block ip_block_inst( .port0(port0_wire), .port1(port1_wire) ); // synthesis attribute box_type of ip_block is "black_box"; When I instantiate the ip_block verilog interface in ISE instead of the NGO file, here is what I get: ========================================================================= * HDL Compilation * ========================================================================= Compiling source file "../src/ip_block.v" Module <ip_block> compiled Compiling source file "../src/ip_block_wrapper.v" Module <ip_block_wrapper> compiled No errors in compilation Analysis of file <ip_blobk_wrapper.prj> succeeded. ========================================================================= * HDL Analysis * ========================================================================= ERROR:HDLCompilers:87 - ../src/ip_block_wrapper.v line 270 Could not find module/primitive 'ip_block' Any help appreciated. If I understood exactly what XST needs I could figure this out, but so far no go. Thanks, Bob S.Article: 79915
Hi, I want to create an SVF file. I have read this documentation and it said that I need to open a shell and invoke "jtagprog", I did that but didn't work. I have also tried to find the graphical user interface tool in Project Navigator, but no luck. Does anyone know why? Thanks, ALArticle: 79916
Antti, >> at EBV stand there was PCIexpress board with Altera GX on it, but >> when I wanted to know is it available for purchases then the answer >> was YES! After asking second time another guy did check it out for >> me and then it was not so much YES any more, there was no answer >> it will be inquired, etc... most likely not available. At Sasco we could have given you a resounding and repetitive YES regarding availability of a PCI Express board with a GX on it. We'll have to get to agree on price though - it comes bundled with a PCI Express core ;-) Best regards, BenArticle: 79917
Yaju, remember, this is CMOS which (until recently) consumed no static power at all. The size of the chip and the size of the design does not matter, the power comes from clocking the logic. And the current or power is proportional to the clock rate. Things have become more complicated in 130 and 90 nm technology, where we have a significant amount of leakage current and power that is independent of utiliation and clock frequency, but increases very much with higher teperature. Except for the leakage current, the power is design-dependent, i.e. your design! Peter Alfke, Xilinx ApplicationsArticle: 79918
You'll need to declare a black_box module that is compiled along with your design. This gives information about the port direction and port width. The instance declaration that you provided does not contain such information. module ip_block ( port0, port1 ); input port0; output port1; endmodule // synthesis attribute box_type of ip_block is "black_box"; RobJ wrote: > "Evan Lavelle" <abuse@[127.0.0.1]> wrote in message > news:5n2v11hkdm9sej3im4h4cc4e25rsfopfah@4ax.com... > >>On Fri, 25 Feb 2005 10:03:11 -0800, "RobJ" <rsefton@abc.net> wrote: >> >> >>>I've also tried inluding a verilog >>>description of the port list for the block in the project, which ISE >>>recognizes and then the instantiated block is no longer unkown, but when I >>>run XST I get some bizarre errors. >> >>Should work Ok; XST doesn't need to know anything about your module >>apart from it's I/F. >> >>How are you declaring the module in your Verilog code? What error >>messages are you getting? > > > Hi Evan - > > Here how the NGO module is instantiated: > > ip_block ip_block_inst( > .port0(port0_wire), > .port1(port1_wire) > ); > // synthesis attribute box_type of ip_block is "black_box"; > > When I instantiate the ip_block verilog interface in ISE instead of the NGO > file, here is what I get: > > ========================================================================= > * HDL Compilation * > ========================================================================= > Compiling source file "../src/ip_block.v" > Module <ip_block> compiled > Compiling source file "../src/ip_block_wrapper.v" > Module <ip_block_wrapper> compiled > No errors in compilation > Analysis of file <ip_blobk_wrapper.prj> succeeded. > > > ========================================================================= > * HDL Analysis * > ========================================================================= > ERROR:HDLCompilers:87 - ../src/ip_block_wrapper.v line 270 Could not find > module/primitive 'ip_block' > > Any help appreciated. If I understood exactly what XST needs I could figure > this out, but so far no go. > > Thanks, > Bob S. > > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 79919
Looks like the ppc405_v1_00_a and jtagppc_cntlr_v1_00_a has been removed. You can upgrade to the next rev of the core by simply updating the "PARAMETER HW_VER =" line in the MHS for each of the pcores. You have jtagppc_cntlr_v1_00_b and ppc405_v2_00_b available as options. Thanaporn wrote: > I found 2 version of this reference design on Xilinx website. > > ftp://ftp.xilinx.com/pub/applications/xapp/xapp661.zip > (Use for EDK3.2) > > http://www.xilinx.com/bvdocs/appnotes/xapp661.zip > (Use for EDK6.1) > > Anyone know is the version for EDK6.3 is available? I choose the one > for EDK6.1 and try to open the "system.xmp" file by EDK6.3, the error > was found as below.. Can anyone suggest how to fix it? > > Congratulations!! Your project has been successfully updated to EDK 6.3 > PM_SPEC -- Xilinx path component is <E:/EDA/EDK> > WARNING:MDT - > K:\DG_IP\xapp661_2\pcores\clk_startup_v1_00_a\data\clk_startup_v2_1_0.mpd:3 Options > can not be specified in the same line as "BEGIN <ipname>" > > WARNING:MDT - > K:\DG_IP\xapp661_2\pcores\plb_icap_top_v1_00_a\data\plb_icap_top_v2_1_0.mpd:3 Options > can not be specified in the same line as "BEGIN <ipname>" > > WARNING:MDT - > K:\DG_IP\xapp661_2\pcores\plb_mgtbert_v1_00_a\data\plb_mgtbert_v2_1_0.mpd:3 Options > can not be specified in the same line as "BEGIN <ipname>" > > ERROR:MDT - Can not find valid MPD for Ip ppc405 1.00.a > INFO:MDT - Check the following for possible causes of not finding MPD: > - If HW_VER is specified in MHS, it must follow literal form X.YY.Z > - There is no Ip with given name > - Ip exists but not that version > - Ip (directory) exists but 2.1.0 MPD file is not available > - Ip exist in myip directory (only pcores is supported) > > ERROR:MDT - Can not find valid MPD for Ip jtagppc_cntlr 1.00.a > INFO:MDT - Check the following for possible causes of not finding MPD: > - If HW_VER is specified in MHS, it must follow literal form X.YY.Z > - There is no Ip with given name > - Ip exists but not that version > - Ip (directory) exists but 2.1.0 MPD file is not available > - Ip exist in myip directory (only pcores is supported) > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 79920
RobJ wrote: > > ERROR:HDLCompilers:87 - ../src/ip_block_wrapper.v line 270 > Could not find module/primitive 'ip_block' > Is the .ngo file in the project directory ? If not, is the path to that directory listed in XST->Process Properties->Synthesis Options->Cores Search Directories ? BrianArticle: 79921
I believe you're refering to synthesis of the HDL code for the cores listed in the MHS. This should improve with EDK7.1. As we have improved the way we call XST in platgen. There were some memory leaks due to the iterative call to xst's api. As short term workaround, you should be able to comment out some pcores in your MHS. Then synthesize the system through platgen. As you get to a point to where you can pass through platgen successfully, reintroduce the pcores into the MHS. Platgen's cache mechansim will copy over the previously synthesized cores, and synthesize the newly introduced cores. vasudev wrote: > Dear Friends, > > This is Vasudev Kulkarni, a new member. > > I am working on EDK6.3i, my code is not getting synthesized.... Infact, it > gives an error, "memory conflict, system virtual memory is low" as saying. > My system has 512 MB ram, and 40GB Hard disk capacity, and moreover, my > code is a small random number generator.... > > Please, suggest what to do to synthesize the code. > > Thanks, > Vasudev Kulkarni > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 79922
I am using a Spartan 3 the PQ 208 package. The maximum input current available to the board is going to be 2.5A. I am just concerned whether that will be good enough. I am planning on using a 50Mhz oscillator on the board, similar to the one one the Spartan 3 demo board. I am not sure what my application is going to be. I am currently developing the board as a part of my Master's research. So I will be experiementing with different designs on the board. I just wanted to finalise the board so that the FPGA would be a ready to go product, without having to worry about the power and current. The online estimation tool requires some very specific information about the prospective design or application which I may not be able to accurately predict at this point. But I guess I will give it a try. I guess what I would be looking for if I have missed an "CRITICAL" current or power specs, which might render my board useless if I implement some amazingly futuristic design or application. Is power and current specification a very important issue at all, as I feel I might be speding too much time on something trivial? I am planning on just throwing in the new TPS7xxx buck regulator hoping it will work fine. Other than that I guess my advisor suggests sticking to the Linear Dropout Regulators as used in those Demo Board, since they have been in use for a while and hopefully they work fine. Yaju y a j u at b y u eduArticle: 79923
There's details on the use INOUT ports through EDK. Using the following syntax in the mpd file: PORT TXRX_IO = "", DIR = INOUT, THREE_STATE = FALSE, IOB_STATE = BUF This tells platgen not to expand the _I/_O/_T tri-ports. Read psf_rm.pdf (6.3i) for details. "Microprocessor Peripheral Definition"->"Design Considerations"-> "Tri-state (InOut) Signals" TonyF wrote: > I have designed a slave OPB peripheral, simulated with VCS to check for > the correct functionality and imported it into EDK. All was fine. > > In EDK, when generating the netlist, the HDL code is synthesized using > XST (Xilinx Synthesis Tool), so that the netlist can be generated. > > The problem I'm having is that there is an "inout" port in my user logic > that should go/come all the way up to/from the top level but for some > reason, when XST generates an HDL wrapper to my user logic, it expects > my sub-module to have 1 input and 2 output ports (see the error below) > instead of just the one inout port, as if I had to use directly the > input/outputs of an IOBUF instead of just one inout, e.g.: > > // this is just an example: > IOBUF txrx > ( > .I ( TXRX_IO_I ), // input > .IO ( TXRX_IO ), // inout > .O ( TXRX_IO_O ), // output > .T ( TXRX_IO_T ) // ouput enable > ); > > In my code I have something like this: > > // port declaration > inout TXRX_IO; > > assign TXRX_IO = TxEn? 1'bz:0; // output, pull up assumed > > if (CanRead) > Read_reg <= TXRX_IO; // input > > This is a very simple and elegant Verilog code that infers a tristate > buffer. Surely I should not have to change my design to use the 3 extra > ports instead of just the one inout. > > Also, in my *.mhs file I clearly stated that it should be an external port: > # Global Ports > PORT TXRX_IO = txrx, DIR = IO # txrx connects to the > peripheral's # TXRX_IO port > > > If you have any clues about how this can be solved, I'll appreciate if > you could post them in here. Many thanks. > > TonyF > > > > XST error message: > ------------------------------------------------ > Running XST synthesis ... > INFO:MDT - The following instances are synthesized with XST. The MPD > option IMP_NETLIST=TRUE indicates that a NGC file is to be produced > using XST synthesis. IMP_NETLIST=FALSE (default) instances are not > synthesized. A batch file, synthesis.sh, has been created that allows > you to synthesize those instances in your specified synthesis tool of > choice. > > opb_txrx_0_wrapper (opb_txrx_0) - > C:\EDK_examples\v2pro_eval_mgt2\system.mhs:397 - Running XST synthesis > ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 64 Module > 'opb_txrx' does not have a port named 'TXRX_IO_I' > ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 65 Module > 'opb_txrx' does not have a port named 'TXRX_IO_O' > ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 66 Module > 'opb_txrx' does not have a port named 'TXRX_IO_T' > ERROR:MDT - HDL synthesis failed! > > > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 79924
Hi, I have never worked in Serbia, but since I am originally from there I can tell you what I heard about the salaries (I can't vouch for the accuracy of these numbers). Basically, if you are a top notch engineer you are looking at 1K-1.5K euro; As a beginner-intermediate 500-1K.The cost of living in Serbia is a lot lower than in Western Europe, so with 1K euro you could live a pretty nice life (rent ok apartment, eat out, go out a lot, etc.). With 500 euro you could live relatively modestly. Ljubisa Bajic "KCL" <kclo4_NO_SPAM_@free.fr> wrote in message news:<421ee94b$0$19330$8fcfb975@news.wanadoo.fr>... > Hi, > > I would like to how much money does an engineer win in Serbia (more exactely > Belgrade) ? Because I'd like to make a VIE in a French companie wich have a > design center there. > > Regards > > Alexis
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