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> Because you're so concerned about cost, I'll assume you have a very high > production. While I am not high production, the extra cost becomes significant for some assemblies. If we get away from FPGA's and enter into the world of small inexpensive microcontrollers in equally small boards, adding a programming connector is expensive in more than one way. Typical connectors used for JTAG programming can dwarf microcontrollers and expand the PCB. There's also the wear-and-tear on the programmer side of the ribbon cable if you are doing a few hundred boards at a time. I guess I am looking for a solution that we can adopt across new designs and keep life simple. Although the financial cost of connectors might not be all that significant, there's a lot more beyond raw cost that makes them undesirable. Thanks for the link to the paper describing the "soft touch" test connector. It sounds like a very good solution for test and troubleshooting needs. -MArticle: 126026
On Nov 10, 1:07 pm, Michael Gernoth <m...@gernoth.net> wrote: > Hi, > > On Sat, 03 Nov 2007 22:04:14 -0000, roger wrote: > > I have installed the usb-driver fromhttp://www.rmdir.de/~michael/xilinx > > and I have managed to light up the green led to the usb download cable > > on the spartan 3e starter kit. The green led is going black every 6-8 > > second and then green again. > > I have not heard of this behaviour previously. For me this seems to > indicate that the cable gets dis- and reconnected all the time. > Do you see reoccuring dis-/reconnects in "dmesg". > > > I don't manage to get a connection to the board using Impact. lsusb > > gives me the following: > > > Bus 005 Device 012: ID 03fd:0008 Xilinx, Inc. > > [...] > > can't get device qualifier: Operation not permitted > > What are the permissions on /dev/bus/usb/005/012 (or the current > location of the cable)? This error might show there is a permission > problem. You did add the MODE-line to an udev rules-file? > > > and Impact says: > > > Connecting to cable (Usb Port - USB21). > > Checking cable driver. > > File version of /usr/share/xusbdfwu.hex = 1025(dec), 0401. > > libusb-driver.so version: 2007-10-08 15:43:55. > > Cable connection failed. > > If you preload libusb-driver-DEBUG.so instead of libusb-driver.so you > get a much more detailed output, which could tell why impact does not > find the device (which according to your lsusb-output has the correct > firmware loaded). > > Regards, > Michael Hi Michael, The permissions on /dev/bus/usb/005/016 is: crw-rw-r-- 1 root root 189, 512 2007-11-12 18:37 001 crw-rw-rw- 1 root root 189, 527 2007-11-12 21:45 016 from the dmesg output you can see that the cable jumps around between different buses: [14746.456000] usb 5-2: new high speed USB device using ehci_hcd and address 14 [14746.588000] usb 5-2: configuration #1 chosen from 1 choice [14746.972000] usb 5-2: USB disconnect, address 14 [14748.984000] usb 1-2: new full speed USB device using uhci_hcd and address 10 [14749.124000] usb 1-2: not running at top speed; connect to a high speed hub [14749.148000] usb 1-2: configuration #3 chosen from 1 choice [14778.480000] usb 1-2: USB disconnect, address 10 [14780.092000] usb 5-2: new high speed USB device using ehci_hcd and address 16 [14780.224000] usb 5-2: configuration #2 chosen from 1 choice Any idea why I get this behaviour? Thanks! /RogerArticle: 126027
On Nov 12, 3:30 pm, m <martin.use...@gmail.com> wrote: > > Because you're so concerned about cost, I'll assume you have a very high > > production. > > While I am not high production, the extra cost becomes significant for > some assemblies. If we get away from FPGA's and enter into the world > of small inexpensive microcontrollers in equally small boards, adding > a programming connector is expensive in more than one way. Typical > connectors used for JTAG programming can dwarf microcontrollers and > expand the PCB. There's also the wear-and-tear on the programmer side > of the ribbon cable if you are doing a few hundred boards at a time. > > I guess I am looking for a solution that we can adopt across new > designs and keep life simple. Although the financial cost of > connectors might not be all that significant, there's a lot more > beyond raw cost that makes them undesirable. > > Thanks for the link to the paper describing the "soft touch" test > connector. It sounds like a very good solution for test and > troubleshooting needs. > > -M Also don't assume that gold plating increases the board cost significantly. We've been using ENIG (electroless nickel/immersion gold) on all of our production boards for some time now. We initially changed to ENIG due to process problems with white tin, but stuck with it when we realised that the cost differential was small. This is not the same sort of plating you would need on an edge connector finger. Connectors need at least 15 microinches of gold plate to be reliable. The ENIG plating is very thin, but enough to increase the board's shelf life if you don't build them up right away. And the "pogo" style pins are non-wiping so you should still get several programming cycles out of the ENIG's minimal plating. Regards, GaborArticle: 126028
On Mon, 12 Nov 2007 12:52:43 -0800, roger wrote: > On Nov 10, 1:07 pm, Michael Gernoth <m...@gernoth.net> wrote: >> What are the permissions on /dev/bus/usb/005/012 (or the current >> location of the cable)? This error might show there is a permission >> problem. You did add the MODE-line to an udev rules-file? > The permissions on /dev/bus/usb/005/016 is: > > crw-rw-rw- 1 root root 189, 527 2007-11-12 21:45 016 That is ok. > from the dmesg output you can see that the cable jumps around between > different buses: > > [14746.456000] usb 5-2: new high speed USB device using ehci_hcd and > address 14 > [14748.984000] usb 1-2: new full speed USB device using uhci_hcd and > address 10 > [14780.092000] usb 5-2: new high speed USB device using ehci_hcd and > address 16 > > Any idea why I get this behaviour? There is probably a problem communicating at USB 2.0 with the cable and it falls back to USB 1.1 but then gets reconnected to the 2.0 hub. Try 'rmmod ehci_hcd' (as root) which disables the USB 2.0 part and see if it is stable at USB 1.1. If it is, try swapping the USB A-B cable. Regards, MichaelArticle: 126029
Hi, I recently read that asynchronous FIFOs have certain clock latency. Can somebody please explain a bit about why is there a latency, or delay, before the data can be read from an asynchronous FIFO? I would also appreciate if you can point me to some reference material. Thanks.Article: 126030
On Nov 12, 5:46 pm, RaKa <rakesh.hemn...@gmail.com> wrote: > Hi, > > I recently read that asynchronous FIFOs have certain clock latency. > Can somebody please explain a bit about why is there a latency, or > delay, before the data can be read from an asynchronous FIFO? I would > also appreciate if you can point me to some reference material. > > Thanks. Latency in asynchronous FIFOs relates to the Empty and Full flags, and really to their trailing edges. Take the Empty flag: It is obviously started by a Read operation, but is terminated by a Write operation. It is of interest only to the Read operation. That means the trailing edge of Empty is generated by one clock, but must be interpreted by the other. That means it has to be re-synchronized, and that takes time. Especially if the careful designer worries about metastability. So the latency you mention is for the trailing edge of the Empty flag (and the Full flag). Outside Full and Empty, there is no reason for any latency, since (or should I say if) the FIFO is being implemented in a dual-ported RAM, using two independent address counters. You may want to read the FIFO section of the Xilinx Virtex-5 BlockRAM User Guide. Peter Alfke, Xilinx ApplicationsArticle: 126031
Hi , Is it possible to implement signal declared as bidirectional (i.e.,inout) in FPGA.For example i have to declare bidirectional data bus D[7:0].should i use as two separate unidirectional? regards, fazalArticle: 126032
hi fnds, i am working on implementing MAC protocols on fpga...i am a bit stuck in the way to start the process, like, how to give 2 simultaneous inputs to an fpga? and how to detect if collision has occured or not? so, if anyone can help pls post a reply...Article: 126033
On Nov 13, 10:20 am, fazulu deen <fazulu.v...@gmail.com> wrote: > Hi , > > Is it possible to implement signal declared as bidirectional > (i.e.,inout) in FPGA.For example i have to declare bidirectional data > bus D[7:0].should i use as two separate unidirectional? > > regards, > fazal Fazal, Are you a student or what ? There must be some one around you to reply to your queries. And keep one thing in mind: always study some text book before posting a question. I cannot understand why some one is willing to make himself a "Butt of ridicule" in each and every of his post. /EldonArticle: 126034
It is possible. In sub-modules, I prefer to use seperate input and output signals. At the top level, I use the language's bidirectional signal type and drive it with a value when output is enabled and with z's when the output isn't. The bidirectional port always drives the input set of signals. Synthesis tools will implement this however is best for your partcular device. ---Matthew Hicks > Hi , > > Is it possible to implement signal declared as bidirectional > (i.e.,inout) in FPGA.For example i have to declare bidirectional data > bus D[7:0].should i use as two separate unidirectional? > > regards, > fazalArticle: 126035
On Nov 13, 10:37 am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > It is possible. In sub-modules, I prefer to use seperate input and output > signals. At the top level, I use the language's bidirectional signal type > and drive it with a value when output is enabled and with z's when the output > isn't. The bidirectional port always drives the input set of signals. Synthesis > tools will implement this however is best for your partcular device. > > ---Matthew Hicks > > > Hi , > > > Is it possible to implement signal declared as bidirectional > > (i.e.,inout) in FPGA.For example i have to declare bidirectional data > > bus D[7:0].should i use as two separate unidirectional? > > > regards, > > fazal Thanks for your suggestions..Article: 126036
Andrew Greensted wrote:
> Q3: As for bit ordering, I'm pretty sure this is correct:
> I'm reading the generated binary file (array.bin) 1 byte at a time and
> shifting the MSB first. I'm also shifting some dummy data (DIN='1')
> after the bitstream.
Well, I was sure I had the bit ordering right, but it would seem not!!!
Shifting in the LSB first, on a byte-by-byte basis made is work.
So just in case any one else has the same problem in the future:
I've got 3 Spartan3E XC3S500E in slave serial mode daisy-chained together.
I'm using an Atmel AVR (ATMega644) running at 3.3V with a 10MHz clock.
(The bit file is held on an SDCard)
The slave serial controls are connected to the AVR.
DOUT (from fpga 3) is input to the AVR
DIN (to fpga 1) is output from the AVR
DONE is input to the AVR
CCLK is output from the AVR
INIT_B is input to the AVR
PROG_B is output from the AVR
For the Spartan3E, all signals apart from the PROG_B are 3.3V tolerant,
so these can be connected directly to the AVR.
DONE is 2.5V high, but the AVR should read this as a '1' (Just with a
lower noise threshold)
PROG_B needs to be 2.5V high, so it needs some kind of level
translation, I used a SN74LVC1G07DCK (Farnell 128-7544). It's an open
drain driver. use this with a 4.7k
All FPGA DONE signals are common (with a 330R pull-up)
All PROG_B signals are common (with a 4.7k pull-up)
All INIT_B signals are common (with a 4.7k pull-up)
A binary file is created using the following command:
promgen -w -p bin -u 0 device1.bit device2.bit device3.bit -o array.bin
It is loaded like this:
for each byte in the bin file
// Get byte
byte = next byte from bin file;
// Iterate through each bit
for each bit 0 to 7
// If bit=1 set DATA high (Keep PROG_B high during config)
if (byte & 0x01) data = PROG_B | DATA_AVR2FPGA;
else data = PROG_B;
// output data
output data;
// set CCLK high
data = data | CCLK;
// output data and CCLK
output data;
byte >>= 1;
end for
end for
Hope all that helps someone
Andy
Article: 126037austin wrote: > Philip, > > Yes, this was in part a reply to you, but I had marked the thread > "ignore" as I had already made a note to contact the support group, and > find out what we were doing. > > C.A.F. is a good place to ask if others have the same problem: yes. > And, unlike a webcase, Peter and I do read all of the postings (even if > we do not choose to reply). I'm sure I'm not the only one who appreciates this! You and Peter are a valuable presence here. > In the past, we did not have a specific link for questions that > professors used, but as of last week, now we do. So, for your > professor, it should be easier to enter a XUP webcase now. Thanks, I'll discuss it with him. > The only rumor I have heard is that now that we have software releases > on DVDs, they are more susceptible to scratching and damage if left > without their covers, and may be ruined much more easily than a CD would > be. So, if those DVDs were left out, and got tossed about, they may > well be scratched, and won't work. It was straight out of the box and into the computer, but it may have been damaged in transit. -- Philip Potter pgp <at> doc.ic.ac.ukArticle: 126038
Frequently when doing simulation of a design I'll change time constants so I can run the simulation in a reasonable timescale. I like to keep things simple so to date this has mostly involved commenting out the 'proper' value with a -- XXXX comment at the end of the line. When I want to do a real workd build a search for -- XXXX throughout the design should allow me to quickly find the values that need changed and comment them back to their correct values. Except I keep forgetting. Over the years this has caused hours of lost work until I have realised what I've done. I've thought of including a generic in all my modules by default to indicate whether simulation or real world build is being done, this could be propogated down from the top of a design to select which values are being used. Another solution would be a script to search the source directory commenting out --XXXX lines and uncommenting -- YYYY lines (for example). But why re-invent the wheel.... Does anyone have a clever (simple) structured way of ensuring that temporary simulation values aren't included when doing real world builds? Thanks for any pointers, Nial.Article: 126039
>Does anyone have a clever (simple) structured way of ensuring that >temporary simulation values aren't included when doing real world builds? This isn't a real solution, but sometimes hacks are good enough. grep -r XXXX . That will find them all. As long as there aren't many you can check them by eye. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 126040
>>Does anyone have a clever (simple) structured way of ensuring that >>temporary simulation values aren't included when doing real world builds? > > This isn't a real solution, but sometimes hacks are good enough. > > grep -r XXXX . > > That will find them all. As long as there aren't many you can check > them by eye. Aye Hal, I have windows Grep on my PC so can create a tool in Textpad to do this and capture the results fairly easily. The problem is that I keep forgetting to check. :-( Nial.Article: 126041
>Are you a student or what ? >There must be some one around you to reply to your queries. And keep >one thing in mind: always study some text book before posting a >question. > >I cannot understand why some one is willing to make himself a "Butt of >ridicule" in each and every of his post. Since you seem to be arguing against newsgroups, why are you here? You say that "There must be some one around you to reply to your queries". Well, maybe (like me) he works alone. Do you seriously imagine that the whole world is like the small one that you live in? Ask some of the sales engineers here. You might be surprised to find that not everyone who works with FPGAs is a student or works in a large company, surrounded by willing mentors and a library of relevant books. On that subject, which "some text book" do you suggest that he consult? My own experience is that most of the good-quality material in this field is provided by manufacturers. These answer many, but not all of the questions which you seem to feel have an obvious answer. As an FPGA novice, I found a similar difficulty with the question which he asks. The solution is straightforward, but wasn't made explicit in the manuals which I read. I thought it out for myself, but I don't think I'd be "a butt of ridicule" if I asked others about it, especially if I showed that I'd given it some thought. We all have holes in our knowledge. The contributors here who make me snigger are not those asking relevant questions. They are those still working like we did 30 years ago, in the easy environment of a big company and not having noticed that the rest of the world has moved on.Article: 126042
>> > Hi , >> >> > Is it possible to implement signal declared as bidirectional >> > (i.e.,inout) in FPGA.For example i have to declare bidirectional data >> > bus D[7:0].should i use as two separate unidirectional? >> >> > regards, >> > fazal > >Thanks for your suggestions.. > > Here I give you an advice. Read the related FPGA datasheets then you will know what there are in a FPGA. It is the resources in a FPGA determine what function a FPGA can implement. Best regards Leon,Article: 126043
Hello all, I am trying to make the PORT B of a BRAM visible in EDK ver.6.2i . The only ports can make visible from PORT B is only the CLK. have you any idea how to do the rest ports of BRAM PORT B visible? regardsArticle: 126044
On Tue, 13 Nov 2007 10:12:02 -0000, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:
>Frequently when doing simulation of a design I'll change time
>constants so I can run the simulation in a reasonable timescale.
>But why re-invent the wheel....
>
>Does anyone have a clever (simple) structured way of ensuring that
>temporary simulation values aren't included when doing real world builds?
constant ddr_reset_time : integer := 200 us / clk_period; -- cycles
constant sim_reset_time : integer := 2 us / clk_period; -- cycles
function reset_time return integer is
variable temp:integer := ddr_reset_time;
begin
-- pragma synthesis off
temp := sim_reset_time;
-- pragma synthesis on
return temp
end;
...
reset_counter <= reset_time;
- Brian
Article: 126045Philip Potter wrote: > Hi there, > > We just received EDK 9.2 but there seems to be an error in the install. > I tried to install it and got the error message "F:\idata\drop28.zip.xz > error in zipfile". The installer continued after this message, with the > percentage progress bar continuing to rise, but at some point afterwards > the windows closes and leaves me with a half-installed EDK install. > > I took a screenshot of the error message here: > http://www.doc.ic.ac.uk/~pgp/edk9.2error.png I got to the bottom of this in the end. I took the DVD out of the drive and it had more scratches on it than was healthy. The ISE disk that came with EDK also had plenty of scracthes, and we'd never taken it out of the case! I wonder what could have caused them? -- Philip Potter pgp <at> doc.ic.ac.ukArticle: 126046
Philip Potter schrieb: > I got to the bottom of this in the end. I took the DVD out of the drive > and it had more scratches on it than was healthy. The ISE disk that came > with EDK also had plenty of scracthes, and we'd never taken it out of > the case! I wonder what could have caused them? The same is true for the EDK9.1 disk that I received about two weeks ago, though mine is readable. Regards, AndreasArticle: 126047
In comp.arch.fpga, dilip <dilip.manu@gmail.com> wrote: > hi fnds, i am working on implementing MAC protocols on fpga...i am a > bit stuck in the way to start the process, like, how to give 2 > simultaneous inputs to an fpga? and how to detect if collision has > occured or not? > so, if anyone can help pls post a reply... Are you talking about Ethernet? If so, you need an analog frontend to interface with the cable, you can not directly connect the cable to the FPGA. Easiest (and only?) option is to use an Ethernet PHY. The PHY handles the analog stuff, speed negotiation, collisions and other stuff. Connect it (or multiple) to your FPGA using the MII (or RMI) interface. Read the PHY datasheet and google for other ethernet information sources. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 126048
On Nov 13, 7:46 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 13 Nov 2007 10:12:02 -0000, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > >Frequently when doing simulation of a design I'll change time > >constants so I can run the simulation in a reasonable timescale. > >But why re-invent the wheel.... > > >Does anyone have a clever (simple) structured way of ensuring that > >temporary simulation values aren't included when doing real world builds? > > constant ddr_reset_time : integer := 200 us / clk_period; -- cycles > constant sim_reset_time : integer := 2 us / clk_period; -- cycles > > function reset_time return integer is > variable temp:integer := ddr_reset_time; > begin > -- pragma synthesis off > temp := sim_reset_time; > -- pragma synthesis on > return temp > end; > > ... > > reset_counter <= reset_time; > > - Brian Nice trick Brian; I'll have to remember that... I would use a generic, passed up to the top level, with a default value defined for synthesis. Then when you instantiate the top level module in your testbench for simulation, override the default value with a generic map. This can be done for one or a whole group of generics. If you use a group of generics, you can define them as elements of a record type in a package, and every entity takes that generic record. That way when you want to add a generic for some lower level entity, you just have to add it's element to the record definition, then set it at the top (default and testbench), and use it at the leaf level where needed. The record definition acts like a conduit through which you can pass anything you want. AndyArticle: 126049
On Nov 13, 5:21 am, "commone" <deche...@yahoo.com.cn> wrote: > >> > Hi , > > >> > Is it possible to implement signal declared as bidirectional > >> > (i.e.,inout) in FPGA.For example i have to declare bidirectional > data > >> > bus D[7:0].should i use as two separate unidirectional? > > >> > regards, > >> > fazal > > >Thanks for your suggestions.. > > Here I give you an advice. Read the related FPGA datasheets then you will > know what there are in a FPGA. It is the resources in a FPGA determine > what function a FPGA can implement. > > Best regards > > Leon, Not exactly... You can code a bidirectional tri-state bus for most synthesis tools, and when targeting devices without that capability, they will convert it to multiplexers. That said, unidirectional tri-state bus descriptions have some particular advantages when dealing with mutual exclusiveness of the select lines. Synthesis assumes that tri-state enables on a bus are mutually exclusive, whereas coding a non-priority multiplexer with separate enable bits is sometimes difficult. But bidirectional internal signals are almost always better when implemented as separate unidirectional buses, tri-state or not. Andy
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