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Hi,
I think you problem comes from the your following lines (Your read and
write process is bad too):
DATA <= DATA_OUT when (RD_N = '0') else (others => 'Z'); -- line OK
DATA_IN <= DATA when (WR_N = '0') else DATA_IN; -- BAD
Like this, your synthesizer would not understand your bidirectional
logic. You do not need to add conditions on DATA_IN <= DATA, because
DATA_in is ever DATA !!! Your condition WR_N = '0' comes only in your
write process.
I would like write :
DATA <= DATA_OUT when (RD_N = '0') else (others => 'Z'); -- line OK
DATA_IN <= DATA; -- line OK
--------------------------------------------------------------
In VHDL, my first rule is to do smallest process as possible !
--------------------------------------------------------------
In your case, the read part and write part need to be placed in two
different process.
Read process is an asynchronous process, you do not need flip-flops, but
just a big mux
Write process is a an synchronous process
your code will be :
----------------------------------------
-- write process
----------------------------------------
process (CLK, RESET) begin
if(RESET = '1') then
REG1_DATA <= (others => '0');
REG2_DATA <= (others => '0');
elsif(CLK'event and CLK = '1') then
if (WR_N = '0') then --bus write
case ADDR(9 downto 0) is
when REG1_ADDR =>
REG1_DATA(15 downto 0) <= DATA_IN;
REG2_DATA(15 downto 0) <= REG2_DATA(15 downto 0);
when REG2_ADDR =>
REG1_DATA(15 downto 0) <= REG1_DATA(15 downto 0);
REG2_DATA(15 downto 0) <= DATA_IN;
when others =>
REG1_DATA <= (others => '-');
REG2_DATA <= (others => '-');
end case;
end if ;
end if ;
end process ;
-----------------------------------------
-- read process
-----------------------------------------
process (RD_N, ADDR, REG1_DATA, REG2_DATA) begin -- read process
if (RD_N = '0') then --bus read
case ADDR(9 downto 0) is
when REG1_ADDR =>
DATA_OUT <= REG1_DATA(15 downto 0);
when REG2_ADDR =>
DATA_OUT <= REG2_DATA(15 downto 0);
when others =>
DATA_OUT <= (others => '0'); -- <--high imp. is
not declared here
end case;
else DATA_OUT <= (others => '0');
end if;
end process;
end BEH;
When writing VHDL bus, register, and others ... you need to think
HARDWARE ...
Regards
Laurent Gauch
Amontec
www.amontec.com
___________________________________________________________
Introducing prototyping Boards based PCI and Stand-alone for rapid
FPGA/ASIC developments!
M Schreiber wrote:
> Hello,
> I am having a problem implementing a bi-directional bus within a
> Xilinx virtex 2 part. I have read through the numerous postings and
> have not found a clear answer. I have implemented a bus that works
> fine in simulation, but when it is synthesized, fpga express says it
> cannot determine the port type and replaces it with an output port
> (FPGA-pmap-18). My architecture consists of a set of registers that
> exist in separate vhdl blocks. The designs synthesizes normally and
> functions normally on a virtex 2 demo board when the registers reside
> in the same block. When I split them up, I run into the above
> problem. I ran across someone else's post, that said I need to use a
> mux to have an internal bi-directional bus, is this true? Also at one
> point in the back-end xilinx tool I got a message asking me to set
> XVK_MAP_ALLOW_BUS_CONTENTION environment variable. Any help would be
> greatly appreciated. I have included a simplified sample of one of
> the vhdl blocks.
> Thanks in Advance,
> Mike Schreiber
> Hardware Engineer
> mschreiber75@yahoo.com
> entity SLAVE_1 is
> port (
> ADDR : in std_logic_vector (9 downto 0); --8-bit
> address bus, temporarily 9-bit
> DATA : inout std_logic_vector (15 downto 0); --8-bit
> data bus
> RD_N : in std_logic; --read signal, active-low
> WR_N : in std_logic; --write signal, write is
> active-low
> RESET : in std_logic; --system reset
> CLK : in std_logic; --system clock
> BLOCK_SELECT_N : in std_logic --block select enable
> );
> end SLAVE_1;
>
> --}} End of automatically maintained section
>
> architecture BEH of SLAVE_1 is
> signal DATA_IN : std_logic_vector(15 downto 0);
> signal DATA_OUT : std_logic_vector(15 downto 0);
> signal DUMMY_REG : std_logic_vector(15 downto 0);
> --Internal Registers
> signal REG1_DATA : std_logic_vector(15 downto 0);
> signal REG2_DATA : std_logic_vector(15 downto 0);
> --address range: 0x00 - 0x1f, block address: 1
> constant REG1_ADDR : std_logic_vector := "0000000000"; --address of
> described register
> constant REG2_ADDR : std_logic_vector := "0000000001"; --address of
> described register
> begin
> -- <<enter your statements here>>
> DATA <= DATA_OUT when (RD_N = '0') else (others => 'Z');
> DATA_IN <= DATA when (WR_N = '0') else DATA_IN;
> process (CLK, RESET, ADDR, DATA) begin --read write process
> if(RESET = '1') then
> REG1_DATA <= (others => '0');
> REG2_DATA <= (others => '0');
> elsif(CLK'event and CLK = '1') then
> if (WR_N = '0') then --bus write
> case ADDR(9 downto 0) is
> when REG1_ADDR =>
> REG1_DATA(15 downto 0) <= DATA_IN;
> REG2_DATA(15 downto 0) <= REG2_DATA(15 downto 0);
> when REG2_ADDR =>
> REG1_DATA(15 downto 0) <= REG1_DATA(15 downto 0);
> REG2_DATA(15 downto 0) <= DATA_IN;
> when others =>
> REG1_DATA <= REG1_DATA;
> REG2_DATA <= REG2_DATA;
> end case;
> elsif (RD_N = '0') then --bus read
> case ADDR(9 downto 0) is
> when REG1_ADDR =>
> DATA_OUT <= REG1_DATA(15 downto 0);
> when REG2_ADDR =>
> DATA_OUT <= REG2_DATA(15 downto 0);
> when others =>
> DATA_OUT <= (others => 'Z'); --high imp.
> data bus
> end case;
> else
> DUMMY_REG <= DUMMY_REG;
> end if;
> end if;
> end process;
> end BEH;
>
Article: 45026
If you are using Xilinx VirtexII or Altera Stratix, these devices have
embedded multipliers which you can instantiate to accomplish this task. If
you are using some other device you'll have to construct your own. The
compilers, if they, infer a multiply at all (only some do) do not produce
anything particularly fast. You have a better shot at getting what you want
by using the core generators from the respective vendor to generate a placed
multiplier macro. You can also build your own, in which case I encourage you
to visit the multipliers page on my website for a discussion of optimal
structures for FPGAs.
Reala wrote:
> Dear all,
>
> I would like to design a 32 bit multiplier (16bit X 16bit) for MCU.
> The multiply operation for MCU is one cycle only.
> Normally, the multiply operation is about 4 cycles. It is a difficult task
> for me.
> Is there any special method to make a smaller size multiplier with single
> cycle do this?
> Moreover, if i write this by verilog, can the complier take care this kind
> of task? or depend on the source file of my design? or must do this by
> schematic
> design?
>
> Anyone have idea to do this? Thank a lot.
>
> Reala
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45027Today, we've a Spartan with a PLX. We would like to introduce Logicore in Spartan to replace PLX but IO aren't the same (excuse me for my english... I'm french). Do you know an interface to use my old VHDL program (with PLX IO) with a logicore without modification ? Thanks a lot, BROTO LaurentArticle: 45028
Paul wrote: > Hi All, > Are there any security features in FPGA's that I can use to protect > software? Yes, check out Virtex-2. It uses triple DES keys so the rom data is encrypted when you get the product into the field. You need to talk to the Xilinx guys to find out how to get the keys into your chips tho. Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45029
Hi everyone I am using synplify 6.2.4 to synthesis and Quartus II to P&R after all done, I found there are some combinational loops in my design, but the report is based on the postsyn netlist, not on the RTL source, so How can I know which part of my design cause these loops? Best RegardArticle: 45030
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> schrieb im Newsbeitrag news:YJJW8.349$Gr3.1222@amstwist00... | Check out the Altera University program | (http://www.altera.com/education/univ/unv-kits.html). The basic board has | both an SRAM-based FPGA (10K20) and a CPLD (MAX7128). These boards (plus | software) are available for really low prices for university students. | | You can do quite a few things with that board. If it seems to do what you | want it to, you can order it in germany by going to the following web page: | | http://www.altera.com/education/univ/program_regions/unv-germany.html Hi Ben! That sounds quite well. I'll have a look at it ... Thanks, StevenArticle: 45031
Did you just try my solution, in my first answer ??? Take time to do it, and you will anderstand : you just need two process, one write process, one read process. Or try to draw the schematic of what you need(flip-flop, mux, ...) YOU NEED TO SEE THE SCHEMATIC WHEN YOUR ARE WRITING VHDL CODE Laurent Gauch www.amontec.com M Schreiber wrote: > Hari Devanath <harid@xilinx.com> wrote in message news:<3D2B4A93.D6A6727D@xilinx.com>... > >>Hi Mike, >>Make sure that all signals declared as bidirectional are actually used as >>both input >>and output. See (Xilinx Solution 3296) for more details. >> >>The above warnings usually occur when there are multiple three-state >>inferences >>driving the inout signal. Rather than choosing one three-state to place in >>the IOB, >>Express will place all the three-state using internal TBUFs then use a >>standard >>OBUF at the IOB. Examine your HDL to be sure the bidirectional structure is >>explicit. >> >>Hari. >> >>M Schreiber wrote: >> >> >>>Hello, >>> I am having a problem implementing a bi-directional bus within a >>>Xilinx virtex 2 part. I have read through the numerous postings and >>>have not found a clear answer. I have implemented a bus that works >>>fine in simulation, but when it is synthesized, fpga express says it >>>cannot determine the port type and replaces it with an output port >>>(FPGA-pmap-18). My architecture consists of a set of registers that >>>exist in separate vhdl blocks. The designs synthesizes normally and >>>functions normally on a virtex 2 demo board when the registers reside >>>in the same block. When I split them up, I run into the above >>>problem. I ran across someone else's post, that said I need to use a >>>mux to have an internal bi-directional bus, is this true? Also at one >>>point in the back-end xilinx tool I got a message asking me to set >>>XVK_MAP_ALLOW_BUS_CONTENTION environment variable. Any help would be >>>greatly appreciated. I have included a simplified sample of one of >>>the vhdl blocks. >>>Thanks in Advance, >>> Mike Schreiber >>> Hardware Engineer >>>mschreiber75@yahoo.com >>>entity SLAVE_1 is >>> port ( >>> ADDR : in std_logic_vector (9 downto 0); --8-bit >>>address bus, temporarily 9-bit >>> DATA : inout std_logic_vector (15 downto 0); --8-bit >>>data bus >>> RD_N : in std_logic; --read signal, active-low >>> WR_N : in std_logic; --write signal, write is >>>active-low >>> RESET : in std_logic; --system reset >>> CLK : in std_logic; --system clock >>> BLOCK_SELECT_N : in std_logic --block select enable >>> ); >>>end SLAVE_1; >>> >>>--}} End of automatically maintained section >>> >>>architecture BEH of SLAVE_1 is >>> signal DATA_IN : std_logic_vector(15 downto 0); >>> signal DATA_OUT : std_logic_vector(15 downto 0); >>> signal DUMMY_REG : std_logic_vector(15 downto 0); >>> --Internal Registers >>> signal REG1_DATA : std_logic_vector(15 downto 0); >>> signal REG2_DATA : std_logic_vector(15 downto 0); >>> --address range: 0x00 - 0x1f, block address: 1 >>> constant REG1_ADDR : std_logic_vector := "0000000000"; --address of >>>described register >>> constant REG2_ADDR : std_logic_vector := "0000000001"; --address of >>>described register >>>begin >>> -- <<enter your statements here>> >>> DATA <= DATA_OUT when (RD_N = '0') else (others => 'Z'); >>> DATA_IN <= DATA when (WR_N = '0') else DATA_IN; >>> process (CLK, RESET, ADDR, DATA) begin --read write process >>> if(RESET = '1') then >>> REG1_DATA <= (others => '0'); >>> REG2_DATA <= (others => '0'); >>> elsif(CLK'event and CLK = '1') then >>> if (WR_N = '0') then --bus write >>> case ADDR(9 downto 0) is >>> when REG1_ADDR => >>> REG1_DATA(15 downto 0) <= DATA_IN; >>> REG2_DATA(15 downto 0) <= REG2_DATA(15 downto 0); >>> when REG2_ADDR => >>> REG1_DATA(15 downto 0) <= REG1_DATA(15 downto 0); >>> REG2_DATA(15 downto 0) <= DATA_IN; >>> when others => >>> REG1_DATA <= REG1_DATA; >>> REG2_DATA <= REG2_DATA; >>> end case; >>> elsif (RD_N = '0') then --bus read >>> case ADDR(9 downto 0) is >>> when REG1_ADDR => >>> DATA_OUT <= REG1_DATA(15 downto 0); >>> when REG2_ADDR => >>> DATA_OUT <= REG2_DATA(15 downto 0); >>> when others => >>> DATA_OUT <= (others => 'Z'); --high imp. >>>data bus >>> end case; >>> else >>> DUMMY_REG <= DUMMY_REG; >>> end if; >>> end if; >>> end process; >>> end BEH; >>> > > I took a look at the xilinx solution 3297, but i am not sure if that > applies in this case. I also took a look at the hdl and the only port > that I am using as a bi-directional port is the DATA port, and it is > being used a bi-directional signal (as far as I can see). Maybe I can > clarify the configuration, I didn't do a very good kob the first time. > __________ > DATA <->----------------|DATA | > | | | > | | Reg1 | > | |__________| > | > | ___________ > |________|DATA | > | | > | Reg2 | > |__________| > From the above fantastic drawing you can see an example of how the > blocks are layed out. Basically I instantiate two of the VHDL modules > (included in the 1st post), into the top level. All of the DATA ports > are declared as inout. There is also an address bus (ADDR) that is > run to all of the blocks in the design that allows data to be > written/read to/from the different registers. Basically the design is > a standard memory mapped i/o interface to a 16-bit micro-controller > (standard signals RD, WR, EN, ADDR, DATA, etc). Should I just create > a MUX and make all of the signals uni-directional, and take care of > the addressing in both the mux and the individual lower level blocks > that contain the registers? Also if this was the case the interface > to the micro-controller would have to be bi-directioanl at some point. > Am i going to run into the same problem again? thanks for the help > Mike >Article: 45032
It looks like a fud message. We have recently heard fhat there are some fud msg spreading in the fields too. V2P's RocketIO transceivers are highly functional. Therefore, if you still have any issue or question, please contact your FAE and Xilinx Hotline. Thanks. -Winnie ------------------------------------------------------------ My posts in this news group represent only personal opinion ------------------------------------------------------------ dano1@attglobal.net wrote: > Is it true that the multi-channel fifo-allignment for the SERDES is not > functional in the VII-PRO? Does anyone know what the isue is in detail? Can > two channels be aligned ? > > Thanks, > DanArticle: 45033
Hakon, Before Virtex II, one needed to delay the LOCKED signal before releasign the reset of the next DLL. This is no longere required in Virtex II, or later parts. This was a start up from the reset condition in the cascaded DLL issue. Austin Hakon Lislebo wrote: > Thank you Austin, that was just what I wanted to know. I also am > curious about one more thing: > > When to DCM's or DLL's are cascaded, Xilinx have introduced a SRL16 > shift register between LOCKED on the first DLL to RST on the second. > Does that mean that the clock coming out from the first DLL is not > completely OK when its LOCKED output goes high? > > Hakon > > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D2AF5DB.39F513A@xilinx.com>... > > Hakon, > > > > In the Virtex, Virtex E, Spartan II, and Spartan IIE, LOCKED may > > occasionally go low due to asynchronous gaps in the input clock, and then > > go high again. One has to catch the falling edge of LOCKED to be sure the > > DLL is not locked. If the input clock stops altogether, LOCKED stays high > > (it is a synchronous state machine). > > > > This was changed in Virtex II, and Virtex II Pro, so that once low, LOCKED > > can not go high again until it is RESET. If the clock in stops, the > > CLK_IN_STOPPED status bit goes high (LOCKED will stay high as in the > > previous families). If the CLKFX stops, the CLKFX_STOPPED status bit goes > > high until reset (and again, LOCKED stays high). > > > > So a healthy DCM = LOCKED AND NOT(CLK_IN_STOPPED OR CLKFX_STOPPED). > > > > Austin > > > > Hakon Lislebo wrote: > > > > > Hi, I mean that I have read that the Xilinx DCM - LOCKED output stays, > > > or goes high again after the DCM has lost lock. Is that correct? Does > > > anybody have a link to some documentation? > > > > > > Thank you > > > Regards > > > Hakon LisleboArticle: 45034
Thank you for your input. What did you mean by IIRC? What does it stand for? John_H <johnhandwork@mail.com> wrote in message news:<3D2B225E.A37A684A@mail.com>... > You have the right primitive, indeed. > > If you have a good synthesizer, you can infer the lookup as well. > Synplify has been doing the distributed dual-ports for me nicely (as long > as I define a write enable), even duplicating when I need more than one > read channel (a tri-port?). > > IIRC, the Xilinx data sheets do a good job of illustrating the timing for > the read-write violation. > > > Antony wrote: > > > Hello, > > > > I'm trying to implement a LUT (16 deep, 8 bits wide), which should be > > able to be programmed its content while the data is been read. I know > > that I can't read data from a location while I'm writing to the same > > location - this could be a memory read-write violation. > > > > Obviously, using two of them and muxing the read and write is the > > easiest option. I'm trying to find out if there are any other ways of > > doing this. I'm wondering if the use of Distributed SelectRam > > (RAM16X1D) could help me. > > > > Any suggestions are greatly appreciated. > > > > Antony.Article: 45035
Jeff Mock wrote: > If you want to keep SDRAM contents across reconfiguration for debug > purposes on the bench I think this will work okay, but it the > product's operation depends on it I don't think this will work. > > The SDRAM needs to have all of its rows refreshed every 64ms, which > is probably too quick to do a reconfiguration. If you are doing a > distributed refresh where you refresh single rows at regular time > intervals, there will be some row in the SDRAM micro-seconds away > from needing to be refreshed when reconfig starts. > > The refresh spec is very conservative, especially at room temperature, > so the refresh issue is probably not a problem on the bench, but will > hurt over temperature and voltage. > > jeff > To cover all cases it would probably be best to put the SDRAMs into self-refresh mode just before starting the re-config (do this by performing an auto-refresh command with CKE = low) then hold CKE low with a pulldown during re-config.Article: 45036
Hi I would like to implement a DPLL in FPGA, using VHDL. The input to DPLL is a 2.048MHz clock, and I want output is like: N*64KHz, well N=1 to 31. Could anybody give me a clue? Any comments is appreciated. FrankArticle: 45037
Anthony Ellis wrote:
>
> Hi,
>
> I am struggling with a post map simulation of a Xilinx design with a
> bidirectional I/O port. The I/O port has an output register, input register
> and tristate control all defined with the IOB attribute. Looking at the map
> results the I/O implementation seems match what I expect. However, the
> mapping processes does issue warnings that IOBUF's are being added and that
> a simulation mismatch may occur - and my testbench does just this.
>
> Looking at the simprims logic it seems that the I/O port is implemented
> internally to the device as the pullup primitive, input register, output
> register are connected one level in from the actual chip I/O signal. This
> chip I/O signal has an X-BUF and X-TRI buf inserted before the output pin -
> making it now purely an output?
>
> I can't see why this is as the registered input is used all over (so cannot
> be removed) and the functional simulation works fine.
>
> Anthony.
I am not sure what exactly is going on, but my guess will be
that you might have tri-state buffers buried inside a submodule (i.e.,
Tri-state buffers are not on the top module.), and also you are keeping
the design hierarchy during synthesis (i.e., Not flattening the design
hierarchy during synthesis.)
Assuming what I said is the case which I am not sure, what you can do is
you can flatten the design hierarchy during synthesis which will result
in tri-state buffers and associated registers getting "bubbled up" to
the top module which will get automatically converted to IOBUF or OBUFT
by XST.
The only problem of flattening design hierarchy during synthesis in XST
is that, if you have blackboxes in your design (i.e., Mixed language
design or using IP cores supplied in a netlist format.), XST will likely
mess up the synthesis (I have observed valid FFs getting mysteriously
disappearing from the netlist generated.).
In case you cannot flatten the design hierarchy because you are using IP
cores that requires you to keep the design hierarchy or to avoid the
fatal bug of XST I just mentioned, all you can do is to instantiate I/O
pad library primitives like OBUFT or IOBUF in your code.
If the design hierarchy is not flattened during synthesis in XST, XST
cannot seem to "bubble up" regular tri-state buffers (i.e., In Verilog
"assign My_Signal = My_Signal_OE ? 1'bz : My_Signal_Output;") unless you
use OBUFT or IOBUF.
Xilinx seems to have been aware of this problem of XST, but has done
nothing for years . . .
Another thing you may want to try before simulating your design
will be to take a look at the netlist generated by XST.
There you should be able to see if XST is indeed inferring IOBUFs.
(Synthesis report will also mention it, too.)
If you are using ISE 3.x's XST, you should have no problem reading the
EDIF netlist.
However, if you are using ISE 4.x's XST, Xilinx will tell (lie to) you
that all XST can do is it can only generate an encrypted netlist (.NGC)
and not an EDIF netlist.
I posted a posting in this newsgroup a few months ago that ISE 4.x's XST
can actually generate an EDIF netlist.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=aceeac%249fj%241%40newsreader.mailgate.org&rnum=1&prev=/groups%3Fq%3DKevin%2BBrace%2BXST%2BEDIF%26hl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3Daceeac%25249fj%25241%2540newsreader.mailgate.org%26rnum%3D1
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45038I am new to the world of PLDs and FPGAs and need advice on choosing a device and developement kit. My application will be in a portable device and therefore needs to be as low power as possible and small (BGA probably). Xilinx has an application note (#154, #155) where they put an ADC and an DAC in their Virtex FPGA. This would be a highly desirable feature in any device recommended. Another major feature I need is that our data is fed into a Nueral Network currently in MatLab. MatLab can export the algorithm for the ANN in C code, which i would then like to use in the FPGA. I think this would be done by essentially creating a processor on the FPGA (with command architecture) and then compiling the C into assembly and downloading into a Program Memory for the processor? The data rate for this particular application will probably not be very high, but I would like to use FPGA technology in future projects where speed is critical (ultrasonic measurements, impedence, etc.). I would like to pay <~$1000 for a developement board. All of your advice and opinions are welcome. If you need more info, please email me and I will answer to the best of my ability. Thanks in advance Daniel Westerheim Research EngineerArticle: 45039
A DPLL is going to need a master clock considerably higher than the highest
output frequency you wish to produce. In your case, 31*64K is just shy of your
2.048 MHz clock, so it isn't going to work very well. That said, if you just
want a programmable clock frequency generated from your master clock (one picked
to be at least 10-20x), direct digital synthesis is probably the best way to
go. That is basically an accumulator that accumulates fractional phase. The
output frequency is N*Fc/(2^bits) where N is the increment value, bits is the
number of bits in the accumulator and Fc is the master clock frequency. You do
need to be aware that there is a jitter of up to one cycle of the master clock
on the output depending on the increment value (this is unavoidable if you are
generating a non-integral clock from another and still having the output clock
transition as a result of edges on the input clock). The AVERAGE frequency is
determined by the above equation and can be resolved to any precision you want
by adding bits to the accumulator.
Frank Zhifeng Yuan wrote:
> Hi
> I would like to implement a DPLL in FPGA, using VHDL. The input to DPLL is a
> 2.048MHz clock, and I want output is like: N*64KHz, well N=1 to 31.
> Could anybody give me a clue?
> Any comments is appreciated.
>
> Frank
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45040IIRC is shorthand for "If I Recall Correctly." It confused me at first, too, but I see it so much on the newsgroups that I got lazy. At least I don't use "u" as a word!Article: 45041
IIRC = "If I Remember Correctly" Peter Antony wrote: > Thank you for your input. > > What did you mean by IIRC? What does it stand for? > > John_H <johnhandwork@mail.com> wrote in message news:<3D2B225E.A37A684A@mail.com>... > > You have the right primitive, indeed. > > > > If you have a good synthesizer, you can infer the lookup as well. > > Synplify has been doing the distributed dual-ports for me nicely (as long > > as I define a write enable), even duplicating when I need more than one > > read channel (a tri-port?). > > > > IIRC, the Xilinx data sheets do a good job of illustrating the timing for > > the read-write violation. > > > > > > Antony wrote: > > > > > Hello, > > > > > > I'm trying to implement a LUT (16 deep, 8 bits wide), which should be > > > able to be programmed its content while the data is been read. I know > > > that I can't read data from a location while I'm writing to the same > > > location - this could be a memory read-write violation. > > > > > > Obviously, using two of them and muxing the read and write is the > > > easiest option. I'm trying to find out if there are any other ways of > > > doing this. I'm wondering if the use of Distributed SelectRam > > > (RAM16X1D) could help me. > > > > > > Any suggestions are greatly appreciated. > > > > > > Antony.Article: 45042
If you want to produce a Fractional-N interface that's ITU-T compliant, you'll need to look at the allowable jitter specs and decide if you want a real external PLL or a fast digital frequency synthesizer like Ray suggested. If you don't care about compliance, all you need to concern yourself with is how much jitter can your system tolerate. If you can tolerate any and all jitter, a gated clock might be your best approach, grabbing the data from the timeslots as the timeslots occur. If you grab 10 of the 32 (effective) channels, you'll pulse 80 bits out of the 256 bit frame for a 650kHz effective rate. The question is how smooth do you need it? The 25MHz minimum frequency for the DLL input might sound annoying, but the intent is for good digital behavior and not for a good analog PLL. Frank Zhifeng Yuan wrote: > Hi > I would like to implement a DPLL in FPGA, using VHDL. The input to DPLL is a > 2.048MHz clock, and I want output is like: N*64KHz, well N=1 to 31. > Could anybody give me a clue? > Any comments is appreciated. > > FrankArticle: 45043
I think the license file could also be tied to the hard drive serial number. When I upgraded the hard drive in my machine *poof* modelsim no longer worked saying I didn't have a valid license file. I tried unistalling and reinstalling and obtaining a new license file from Xilinx none of which worked. Eventually I had to put the old drive back in my machine (under a different drive letter) and change the license search path to include the old drive. I can at least run ModelSim now, but it complains when I run it that I only have a 30 day evaluation license. Somehow the license software knows that things have changed. I've tried looking in the registry for related entries but could figure out where they were. I sure would like to know what the procedure is to keep ModelSim working when you upgrade your hard drive or network adapter. Rob "Holger Kleinegraeber" <olgi42@web.de> wrote in message news:agc97u$kouhe$1@ID-69700.news.dfncis.de... > > "Derrick Cheng" schrieb: > > > invalid, such that I could not perform the simulation. > > I got the license file from the Xilinx, and I installed the license > > successfully with the License program. > > The License is bound to the MAC-Address of your Network card. Did you > registered, downloaded and work with the same computer? > > Greetings, > Holger > >Article: 45044
Virtex 2 Pro? they got rocket IO and integrated PowerPC. or just Virtex and Virtex 2 with MicroBlaze controller "Daniel" <Daniel.Westerheim@Lynntech.com> wrote in message news:ee77cd1.-1@WebX.sUN8CHnE... > I am new to the world of PLDs and FPGAs and need advice on choosing a device and developement kit. > > My application will be in a portable device and therefore needs to be as low power as possible and small (BGA probably). Xilinx has an application note (#154, #155) where they put an ADC and an DAC in their Virtex FPGA. This would be a highly desirable feature in any device recommended. > > Another major feature I need is that our data is fed into a Nueral Network currently in MatLab. MatLab can export the algorithm for the ANN in C code, which i would then like to use in the FPGA. I think this would be done by essentially creating a processor on the FPGA (with command architecture) and then compiling the C into assembly and downloading into a Program Memory for the processor? > > The data rate for this particular application will probably not be very high, but I would like to use FPGA technology in future projects where speed is critical (ultrasonic measurements, impedence, etc.). I would like to pay <~$1000 for a developement board. > > All of your advice and opinions are welcome. If you need more info, please email me and I will answer to the best of my ability. > > Thanks in advance > > Daniel Westerheim > Research EngineerArticle: 45045
Dear Ray, Thank you for your help. Reala "Ray Andraka" <ray@andraka.com> wrote in message news:3D2C1A15.DE690DAD@andraka.com... > If you are using Xilinx VirtexII or Altera Stratix, these devices have > embedded multipliers which you can instantiate to accomplish this task. If > you are using some other device you'll have to construct your own. The > compilers, if they, infer a multiply at all (only some do) do not produce > anything particularly fast. You have a better shot at getting what you want > by using the core generators from the respective vendor to generate a placed > multiplier macro. You can also build your own, in which case I encourage you > to visit the multipliers page on my website for a discussion of optimal > structures for FPGAs. > > Reala wrote: > > > Dear all, > > > > I would like to design a 32 bit multiplier (16bit X 16bit) for MCU. > > The multiply operation for MCU is one cycle only. > > Normally, the multiply operation is about 4 cycles. It is a difficult task > > for me. > > Is there any special method to make a smaller size multiplier with single > > cycle do this? > > Moreover, if i write this by verilog, can the complier take care this kind > > of task? or depend on the source file of my design? or must do this by > > schematic > > design? > > > > Anyone have idea to do this? Thank a lot. > > > > Reala > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 45046
Oh right, self-refresh mode, I didn't think of that. I take it all back, it's probably quite doable if you put the SDRAMs in self-refresh mode... Rick Filipkiewicz <rick@algor.co.uk> wrote in message news:<3D2C97BB.6CB15AEC@algor.co.uk>... > > To cover all cases it would probably be best to put the SDRAMs into self-refresh mode just before starting the > re-config (do this by performing an auto-refresh command with CKE = low) then hold CKE low with a pulldown > during re-config.Article: 45047
I have encountered the same question as Jone_H's. I want to know how to instantiate the luts with a vhdl module?Article: 45048
Laurent,
I tried your first solution and it works fine with one of my
blocks, but when I connect them together in a bus orientation, fpga
express cannot figure out the port type (DATA port) for some reason.
I had access today to another colleague's synthesis tool (Sympilfy)
and I ran one of earlier versions of code through it with good results
( few warnings, but the code seems to run well on the xilinx demo
board). So I am not sure what the problem is with fpga express, I am
going to keep working at it and see if I can get it to work with FPGA
express. Thanks again for your assiatence. I will let you know what
happens.
Thanks,
Mike
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