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echo wrote: >> Have you actually contacted Xilinx? They have version back to the very >> early days of FPGAs. >> >> > Thanks for the response. Yes we did contact Xilinx and they do not have > earlier versions. In any case have retrogressed to using 6.3 now and are > hoping that it all works out. I'm sorry, but this doesn't make sense. We (Xilinx) can provide an EDK 8.1i release if necessary. We would prefer not to unless there as a really good reason to do so as the later version of the software would be much better choice. But, your original post mentioned that you were targeting a MK325 board which is a Virtex-II Pro X FF1704 RocketIO Characterization Platform and that you needed EDK to be able to program this board. Why do you need to use EDK at all for this board as it has very little to do with the use of the PPC405 that is in the device? The current generation of iMPACT and ChipScope should all be able to download images into these devices. Ed McGettigan -- Xilinx Inc.Article: 122826
Symon, Well, all I can say, is that this is an attempt to improve our service. As everyone here knows, c.a.f. is open to everyone, and anyone, and there is no censorship (so most Xilinx employees will not post here). It was felt that a true Xilinx sponsored forum might be beneficial - allow direct communication. Obviously, Peter and I feel a little odd, as we felt we were doing a good job here on c.a.f. (Perhaps we are, but more is needed?). But, in defense of those who feel that a "real Xilinx forum" has value, I am going to advise folks to give it a try. After all, if people use it, and find it valuable, then it serves a purpose. If it is of no utility, it will die a natural 'Internet Death', and go away. Take it as an opportunity. After all, there will be 'real' applications engineers and hotline folks who will be monitoring this new forum (whose job it is to make customers happy). For every post here, I must consider my competition is reading every word, and just waiting to pounce. That does not allow me the freedom that some other forum might offer. AustinArticle: 122827
On Aug 7, 5:37 pm, "Symon" <symon_bre...@hotmail.com> wrote: > Hey Guys, > Did any of you get an email like this last weekend(see below)? > What a crock! Like a mug, I signed in tonight with my regular Xilinx login, > to check it out. Not exactly popular yet... Sigh, just what we need, more places to look for info. Granted the noise level here is high, but the signal is even lower at vendor specific "web forums". The Altera one is particularily horrid with multiple subdivisions, all with near-zero contents. Alas, this is not going aways as marketing department want to "control" the information and with a web forum they can pull articles that doesn't follow the party line. (I'm not paranoid, I've seen the inside of such forums). Grumble, TommyArticle: 122828
austin <austin@xilinx.com> writes: > there is no censorship (so most Xilinx employees will not post here). Could you explain this? It sounds like Xilinx employees are afraid of people giving their honest opinions of Xilinx's posts.Article: 122829
Symon wrote: > Hey Guys, > Did any of you get an email like this last weekend(see below)? <snip> I got an invite to the forum, too. Interesting point: they used the email I haven't used in a year and didn't duplicate to the address I've been using since. I'd love to see more EDK issues go to the forum since those are Xilinx-specific issues. I remember when Xilinx had their own forum. I'd check posts there and on the newsgroup when I first started perusing the boards. It didn't seem the forum was very helpful back then with some of the questions asked in both places anyway. If Xilinx-specific issues can be handled on the forum, more power to everyone who uses it! I don't think I'll bother signing on. Besides - my next chip has to be brand A. :-/ I got the pricing and experience from brand X but someone else across the country got the pricing and experience to take me back down a road from my distant past. Oh well. I *was* originally going to use Lattice for the project, anyway. :-) - John_HArticle: 122830
Symon wrote: > Anyway, if you post here on CAF and didn't get an email, clearly you're not > a 'significant' contributor. I wonder what one has to do to be significant? My take on 'significant' was that anyone with a pulse was asked ! ;) -jgArticle: 122831
austin wrote: > Symon, > > Well, all I can say, is that this is an attempt to improve our service. > > As everyone here knows, c.a.f. is open to everyone, and anyone, and > there is no censorship (so most Xilinx employees will not post here). ?? > For every post here, I must consider my competition is reading every > word, and just waiting to pounce. That does not allow me the freedom > that some other forum might offer. Not sure I follow the reasoning. Surely ANY forum could have lurkers, but perhaps the Altera lurkers are less likely to point out 'excessive arm waving' in a closed Xilinx forum, and thus users miss out on an important reality check. That could be exactly what you meant by 'waiting to pounce' [..on bogus claims?]. I can see that may be an advantage to Xilinx spin, but how is that an advantage for a customer ? -jgArticle: 122832
Hi, I am having some trouble with implementing several serial links per IO Bank in Virtex5. An IO bank is about the same size as a clock region. Each clock region has 4 BUFIO and 2 BUFR available. I am trying to implement 4 serial links by utilizing 4 BUFIOs and 2 BUFRs in one clock region and the 2 other BUFRs from a neighboring clock region. However, everytime I try to specify the clock region for the BUFIO and BUFR I get mapping errors. The UCF looks like: #Locations for BUFIO INST "RX/BUFIO" AREA_GROUP = "BUFIO_0"; AREA_GROUP "BUFIO_0" RANGE = CLOCKREGION_X0Y3; #Location for BUFR INST "RX/BUFR" AREA_GROUP = "BUFR_0"; AREA_GROUP "BUFR_0" RANGE = CLOCKREGION_X0Y2; I get an error message during mapping where it says that the structure is locked and the relative placment of the locked logic violates the desired structure. The problem was found due to the relative placement of BUFIO and BUFR. I wonder if anyone has tried to do similar implementations or have come across such problems. Basically, Im trying to find out if I can use the BUFR from the neighboring clock region and how to assign them. Thank you in advance, AidaArticle: 122833
Thank you!:-)Article: 122834
I think that scattering the ressources makes them less useful. The only benefit I can see over c.a.f is the access to more Xilinx engineers. But that is something that the combination of WebCase/ AnswersDatabase fulfills allready. Instead of fragmenting the newsgroup I would have thought that adding real new functionality that the newsgroup can't solve would have been more useful. Some suggestions of Web 2.0 features for Xilinx that come to mind: - allow users to add comments to answer records I spend a lot of time browsing through answers, and sometimes I find answers that are related but not linked, or solutions that also apply to other bugs, not immediately listed, or incomplete answers, or better solutions to the same bug, or find out that the same solution also applies to other versions of the software not listed in the original record - allow users to write their own answer records. This process could be moderated - have a bug tracker I often stumble over problems that I immediately have a workaround for, but that should be fixed in later versions of the software anyway. I sometimes file a webcase noting that the case can be closed immediately once it is escalated to the developers. However, I believe there is both more incentive to posting bug, and also more opportunity to help the softwaredevelopers to understand a bug, if the processing of the bug is visible, like it is in open source projects. Also, other users can find the bug in the database and can add their test cases, etc. Kolja SulimmaArticle: 122835
UART core with USB-Serial Converters for PC is a good combination, which can support data rates of upto 921kbps. I have used this combination for 460kbps and it worked fine for me. A little care might be required for implementing UART core, you might have to remove the internal divide by 16 based UART clock if implemented at all, and have to go for a counter running directly from the crystal (system clock). On Aug 6, 9:54 pm, EEngineer <mari...@gmail.com> wrote: > On Aug 6, 4:04 am, makhan <mansoor.nas...@gmail.com> wrote: > > > > > On Aug 6, 7:43 am, EEngineer <mari...@gmail.com> wrote: > > > > On Aug 5, 7:34 am, fpgauser <fpgaengineerfrankf...@arcor.de> wrote: > > > > > Do you need real time access, or more debug information? > > > > > I would take a serial connection (open cores has them) and an > > > > intelligent PC COM software. There are several which are able to > > > > completely receive large data streams. So there is not much work to > > > > do. Possibly you need a level converter like the MAX x232. You may > > > > also want to transform the rams into dual port mems to easier access > > > > them. > > > > For now 115kbits/s would be OK for me as the design I am testing needs > > > to send a content of 16Kb BRAM data at a time, transfer time of > > > several seconds would be fine. But when I expand my design USB > > > transfer would be much better but I am not sure yet how much more > > > complicated would be to make use of the USB port on my FPGA. > > > > -Dan > > > Hi, > > > You might want to consider using chipscope pro, provided if you have > > BRAMs for its storage. Chipscope will store your signals in real time > > (at FPGAs clock speed) and after capturing, display them on its > > analyser. You will be severly limited by the amount of BRAM though. > > Given enough block ram you can store upto 16k samples of a signal. If > > you insert single logic analyser core (ILA core), then you can store > > upto 256 signals for display later. You can trigger your signals at > > any combination or desired point. > > I have been using chipscope before, evaluation version, I found out > that it works up to 16K samples which was exactly what I needed. The > problem was that the whole procedure was tedious for the amount of > tests I wanted to perform. I needed to transform the downloaded data > file with matlab in order to get the desired format so I could > calculate PSNR. Chipscope is good for debugging where you have to > watch many signals (you can capture up to 256 at a time) but it is not > convenient to download the data from the FPGA. > > > Putting USB in a system is a complete new project with its > > complexities. You will need an external protocol negotiator (since you > > wouldn't want to write your own IP). So a microcontroller with all the > > issues resolved may offer a solution and USB data in form of FIFOs > > which can then be interfaced with the FPGA for data readout. You will > > require a PCB redesign in that case. Cypress, Microchip etc. offer > > microcontrollers with USB hardwired USB Protocol resolvers inside. > > I guess that Ethernet interface requires similar steps to implement as > USB? > Maybe I will just go for open cores and UART then, and do the faster > interfaces later down do road, when I need faster data rates. > > -Dan > > > > > Hope this helps. > > > Mak- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text -Article: 122836
On Aug 8, 3:30 am, austin <aus...@xilinx.com> wrote: > As everyone here knows, c.a.f. is open to everyone, and anyone, and > there is no censorship (so most Xilinx employees will not post here). It is really easy to set up an interface server that allows xilinx to moderate posts to c.a.f by its employees. Kolja SulimmaArticle: 122837
You can read my tutorial. http://www.fpgafromscratch.com SvenArticle: 122838
You may find some information here. http://www.fpgafromscratch.com SvenArticle: 122839
I don't know about the plb_ddr core but the opb_ddr core starts auto referesh automatically after reset. See my blog : http://svenand.blogdrive.com/archive/48.html SvenArticle: 122840
On Aug 8, 1:29 am, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi, > > > > PFC wrote: > > >> I can only transmit through the board data at a maximum rate of 1Mbps. > >> Anything more than that is lost. > > > You mean "to the board", not "through", yes ? > > >> eg. When i transmit at 1.4Mbps, 400Kbps of data is lost, etc. > >> And when I try to transmit at data rates over 3Mbps, I get on > >> Hyperterminal the error messege that the Rx Fifo is full. > > > Well, I have never used Virtex4, but I have used a FPGA board > > (Suzaku) with LAN91c111 MAC chip. > > This, running Microblaze/ucLinux, achieved an ethernet bandwidth > > of... 2 Mbps. Yes, that's a bit more than 200 kilobytes per second, ie. > > ridiculous. > > Be fair - a major problem in Suzaku's configuration is the lack of DMA > on the ethernet MAC. A simple fix would be to add an opb_dma controller > to the system, and reconfigure the ethernet driver to use it. > > With the Xilinx EMAC core, full DMA, data realignment engine and > checksum offload we see sustained 50Mbps throughput on MicroBlaze Linux > systems at 100MHz. > > You are right that there is OS overhead, however the Linux kernel does > as little packet copy as possible - once off the MAC to main memory > (unavoidable), then once from kernel to user space. If you use > sendfile() then it's zero copy. > > No operating system will get high performance on a badly bottlenecked > hardware architecture! > > Regards, > > John I agree with John: When your HW suits your needs then you can concentrate to the SW part. The best HW solution for you is a modified a Xilinx Gigabit System Reference Design (aka GSRD2) which was originally built for ML403 board. It uses Multiport Memory Controller, fast LL DMA engine for TEMAC connection. With this system running on a Avnet V4FX12 MiniModule (pretty much the same as your board) I have achieved performance of 740 Mbit/s at 1.5k packets and 850 Mbit/s using 7k packets at streaming raw ethernet data to a PC. Some japanese guy put a Linux 2.6 on this design and achieved 350 Mbit/s TCP performance. The problem I am faced now is a PPC data caching errata - when turned off the performance is significantly lower, when turned on errors in DMA descriptors appear. I still do not what to do about it. If you need a GSRD2 HW design do not hesitate to contact me. Cheers, GuruArticle: 122841
Hi friends, I am working in the field of microelectronics particulary int the field FPGA's/mircontroller based products. I want to persue my Ph.D in France. But I don't have any information about French universities well known for microelectronics systems(reconfigurable computing/ digital communication/DSP/Embedde systems). Please guide me in this regard because it is crucial for my career. thanks, Muhammad Ihsan BaigArticle: 122842
Sorry, I misunderstood. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (low). Better find a way to keep CKE low. See : http://svenand.blogdrive.com/archive/53.html SvenArticle: 122843
On Aug 5, 4:20 pm, drop...@gmail.com wrote: > Hi. > I'm looking for a company who implement various algorithms using FPGA > accelerators. Who can take part of some software code and rework it > completely to make working FPGA accelerator in form, maybe, PCI card > or PC-card. > If such information may be considered as advertising in this group, > please email me: drop...@gmail.com You might want to give give Nallatech (http://www.nallatech.com) a shot. I believe they have a range of FPGA computing platforms.Article: 122844
G'day (o;
As I started development on the Mico32 DSP board I've setup
a site concentrating on my current work:
- u-boot bootloader for the Mico32 DSP ECP2 board
- JTAG flasher tool based on openwince
As Lattice will come out with a uClinux distribution later
on this year there will be sure more work for it by means
of drivers and moving their Eclipse-centric distribution
to a "make xconfig" way (o;
See: http://www.mico32.org/
cheers
rick
ps: One Lattice employee already made a donation (o;
My "thank you" to him...
Article: 122845Recently, I read the source code of OR1200. But I am a little confused about the Exception part. When a exception occurs, the correct execution PC value is found and stored in the "epcr" register. And the "except_type" is set correctly. Then in the next clock, all the instructions in the pipeline are flushed. At the same time, the PC value is set to the exception handling address according to the different exception types in the or1200_genpc.v. However, I don't understand why the FSM in the or1200_except.v almost set the "extend_flush" signal for 5 clocks. It seems not necessary. Does anybody know the answer?Article: 122846
DJ, Xilinx has policies about employees communicating in any public forum (like any company). Anything posted here by an employee has to be in compliance with Xilinx policies. Violation of these policies is grounds for dismissal. One has to "keep their cool" and be fully aware that regardless of the provocation, there are lines we can not cross. Most employees would rather not deal with this. There are about five employees (total) that accept the risks, know the rules, and post here. Peter and I keep track of all Xilinx employees who post, and discuss the requirements with them. In a discussion group that we directly control, we have more options. 'Honesty' has nothing to do with it. Austin DJ Delorie wrote: > austin <austin@xilinx.com> writes: >> there is no censorship (so most Xilinx employees will not post here). > > Could you explain this? It sounds like Xilinx employees are afraid of > people giving their honest opinions of Xilinx's posts.Article: 122847
Jim, That was not clear. I see now that statement was confusing (rambling, etc.). 1. it is a public forum 2. there is no censorship 3. Xilinx has policies for communication in public forums (the general rule: it is not allowed whatsoever) 4. we are a very large target (and there are some who enjoy bashing us) Take each item above as an independent statement. Every post made is re-read at least six times, and then edited (sometimes removing stuff, and even often deleting the whole thing). AustinArticle: 122848
Perhaps, But, if the policy is that no Xilinx employee should be communicating in any pubic forum without permission and review, why bother? Creating a non-public forum may have benefit. AustinArticle: 122849
Tommy, I encourage everyone to vote with their keyboards: to post, or not to post. On c.a.f. or on a private forum. Your choice. Peter and I will remain over here in c.a.f. land (unless everyone leaves). Austin
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