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In an earlier thread complaining about the state of the Xilinx website, Antti (by mistake?) signed off with a URL thus: Antti micro-SD adapter for digilent/xilinx boards: http://docs.google.com/View?docID=ddn2thkw_27fwvkvh At this URL there was a screen shot and text indicating that DOSFS had been ported for use in EDK. Is the microSD adapter and this port available? John RobbinsArticle: 122651
On 2 Aug., 12:24, jcr_...@xplornet.com wrote: > In an earlier thread complaining about the state of the Xilinx > website, Antti (by mistake?) signed off with a URL thus: > > Antti > micro-SD adapter for digilent/xilinx boards:http://docs.google.com/View?docID=ddn2thkw_27fwvkvh > > At this URL there was a screen shot and text indicating that DOSFS had > been ported for use in EDK. > > Is the microSD adapter and this port available? > > John Robbins YES Everything is available, details to follow shortly. the DOSFS 1.03 is now configurable as EDK library and can be used with different block device drivers AnttiArticle: 122652
On Wed, 25 Jul 2007 07:59:04 -0700, austin <austin@xilinx.com> wrote: [re: webcase] >I have to use it as well! In fact, to get answers, I file a webcase. >It is faster than any other method (unless I know exactly who has the >answer, in which case I may call them, or email them. But with ~ 3,000 >employees, that is pretty hard to do). I sincerely hope you get better turnround times! >I apologize in advance for any difficulties, but please continue to >check back: it will be back, and be back better than before. I heard back from Xilinx; it will be assigned to an engineer today. - BrianArticle: 122653
On 2 Aug., 12:24, jcr_...@xplornet.com wrote: > In an earlier thread complaining about the state of the Xilinx > website, Antti (by mistake?) signed off with a URL thus: > > Antti > micro-SD adapter for digilent/xilinx boards:http://docs.google.com/View?docID=ddn2thkw_27fwvkvh > > At this URL there was a screen shot and text indicating that DOSFS had > been ported for use in EDK. > > Is the microSD adapter and this port available? > > John Robbins Hi John, I pushed it a bit and voila http://code.google.com/p/dev-kit/downloads/list the dosfs EDK library package is online the adapters itself are also ready and available shortly some for SD card low level access drivers AnttiArticle: 122654
On Wed, 01 Aug 2007 11:30:08 -0700, Mike Treseler <mike_treseler@comcast.net> wrote: >Jonathan Bromley wrote: > >> I don't understand what's going on in your Xilinx models. I >> can't believe they put out code that doesn't work with >> zero delays. > >They do. So did micron with their sdram models. Could it be their way of making sure designers pay special attention to avoiding clock skew? :-) - BrianArticle: 122655
On Wed, 01 Aug 2007 06:36:14 -0700, Sebastian Goller <sego@hrz.tu-chemnitz.de> wrote: >Hi PFC and Brian, > >thanks alot for your answers. I am now about to find out, which RAM >model I can use and ... believe it or not - I have some trouble. ;-) > >The datasheet of the Kingston DIMM says that this is DDR266 with a >clock cycle time of 7.5 ns. CL = 2.5 > >Like Brian already said the RAM modules are Micron products. According >to the Micron datasheets TG -5B G means that this is a RAM module with >a clock cycle time of 5.0 ns. CL = 3.0. Clocking it at 5ns, it would need CL=3.0. I believe this means at 7.5ns it should support CL=2.5 comfortably; check the datasheet to confirm that you can set the Mode Register correctly for the CL value you want. >The only difference is the package which should not be important for >the simulation. So the question is: Can I use this model? I am asking >this question before I give it a try, because I know it will be a lot >of fun to implement this model in my Xilinx EDK design. Is it available in the language you are using? If it's only available in Verilog and EDK is still only VHDL, your simulator needs to support both languages. I don't know why Micron omit some models in VHDL. Otherwise you can still simulate without it, to check for collisions between refresh and access. - BrianArticle: 122656
On Wed, 01 Aug 2007 19:40:40 -0700, Eric Smith <eric@brouhaha.com> wrote: >ghelbig@lycos.com writes: >> My concern is that I don't see a stable replacement in the near >> future. It really isn't fair to Xilinx to have them support the large >> number of popular Linux systems. > >Xilinx supports Red Hat Enterprise Linux 3 and 4; I expect that >they'll add support for RHEL 5 in the near future, if they haven't >already. I've never had any significant problems running software >intended for RHEL on Fedora and Centos (the latter being a clone of >RHEL). Many people report success on Debian, Ubuntu, and other Linux >distributions. It's great that Xilinx support Linux; however getting a complete toolchain around it isn't quite so easy. ModelSim would be an option for simulation, except that for VHDL, they want lots of money for SE. If LE wasn't Verilog-only, Linux would be a more compelling option. I can see I'll have to try GHDL/VTKwave someday soon.. - Brian From laurent.pinchart@skynet.be Thu Aug 02 06:38:24 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!nx02.iad01.newshosting.com!newshosting.com!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.freenet.de!feeder.news-service.com!transit4.hitnews.eu!feeder2.cambrium.nl!feeder5.cambrium.nl!feed.tweaknews.nl!68.142.88.75.MISMATCH!hwmnpeer01.ams!news.highwinds-media.com!kramikske.telenet-ops.be!nntp.telenet.be!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <46b1de50$0$13859$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: Xilinx Webpack 9.2 and Windows 2000 Pro? Newsgroups: comp.arch.fpga Date: Thu, 02 Aug 2007 15:38:24 +0200 References: <7NTri.12212$eY.8991@newssvr13.news.prodigy.net> <KqXri.2771$mZ5.860@newsfe6-win.ntli.net> <1185977601.627708.28900@q75g2000hsh.googlegroups.com> <1185987527.278677.154060@j4g2000prf.googlegroups.com> <m37ioepsk7.fsf@donnybrook.brouhaha.com> <v9n3b3h8orfigk01s14hr39o208un14pft@4ax.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 33 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: c2bfb405.news.skynet.be X-Trace: 1186061904 news.skynet.be 13859 194.78.198.49:52374 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:134548 X-Received-Date: Thu, 02 Aug 2007 09:38:25 EDT (newsdbm02.news.prodigy.net) Brian Drummond wrote: > On Wed, 01 Aug 2007 19:40:40 -0700, Eric Smith <eric@brouhaha.com> > wrote: > >>ghelbig@lycos.com writes: >>> My concern is that I don't see a stable replacement in the near >>> future. It really isn't fair to Xilinx to have them support the large >>> number of popular Linux systems. >> >>Xilinx supports Red Hat Enterprise Linux 3 and 4; I expect that >>they'll add support for RHEL 5 in the near future, if they haven't >>already. I've never had any significant problems running software >>intended for RHEL on Fedora and Centos (the latter being a clone of >>RHEL). Many people report success on Debian, Ubuntu, and other Linux >>distributions. > > It's great that Xilinx support Linux; however getting a complete > toolchain around it isn't quite so easy. ModelSim would be an option for > simulation, except that for VHDL, they want lots of money for SE. > If LE wasn't Verilog-only, Linux would be a more compelling option. > > I can see I'll have to try GHDL/VTKwave someday soon.. You could also try the Xilinx simulator. Many bugs have been fixed in the 9.1i and 9.2i release, and I'm using it for a medium-size project without any trouble. The wave viewer could be improved though, as it still crashes when performing common operations, and zoom support isn't usable at high zoom levels. -- Laurent PinchartArticle: 122657
Hi Guys: I am working on an application where I have a large number (264) inputs to a single Verilog module. Each input is an 8-bit number. I would like to be able to refer to these inputs as members of an array, with a subscript, for ease in handling them in the program. The only way I can see is to set up an array register, then individually assign each and every input to a specific register in the array. This going to be a lot of typing and I'd have to constantly refresh the assignment in the program. Is there an easier way to do this? Can inputs be directly arrayed in Verilog...and, if so, how would they be referred to in an instatiation, etc? I'm working with a Xilinx Spartan-3 and ISE. Thanks for any replies. DonArticle: 122658
On Thu, 02 Aug 2007 08:10:17 -0700, eromlignod <eromlignod@aol.com>
wrote:
>Hi Guys:
>
>I am working on an application where I have a large number (264)
>inputs to a single Verilog module. Each input is an 8-bit number. I
>would like to be able to refer to these inputs as members of an array,
>with a subscript, for ease in handling them in the program.
Are you saying that they start life as an array of 264 reg[7:0]?
Or are you saying that they start life as 264 differently-named
reg[7:0] (or wire[7:0]) signals? If the latter, may I politely
ask what the hell you are doing?
>The only way I can see is to set up an array register, then
>individually assign each and every input to a specific register in the
>array. This going to be a lot of typing and I'd have to constantly
>refresh the assignment in the program. Is there an easier way to do
>this? Can inputs be directly arrayed in Verilog...and, if so, how
>would they be referred to in an instatiation, etc? I'm working with a
>Xilinx Spartan-3 and ISE.
In "classic" Verilog you can't pass arrays of vectors through a
port, so you must create a port that is 8*264 bits wide, and
copy each of your 264 inputs to one 8-bit slice of the array.
A generate loop will allow you to do that easily:
reg [7:0] massive_array_of_signals [0:263];
reg [0:8*264-1] flattened_array;
genvar i;
generate for (i=0; i<264; i=i+1) begin: copier
always @(massive_array_of_signals[i])
flattened_array[8*i +: 8] = massive_array_of_signals[i];
end endgenerate
In SystemVerilog you can put arbitrary arrays on a port, but
I don't think ISE will allow you to do that just yet.
If you have 264 reg[7:0] signals with distinct names, then your
only hope is to make a big vector of them by concatenation:
wire [0:8*264-1] flattened_array;
assign flattened_array = {
the_first_byte,
the_second_byte,
....
the_264th_byte
);
But please, please tell me you're not doing that.....
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 122659On Aug 1, 8:17 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > > There are many ways to get this right. > Mine is to use signals only > in purely structural entities. > > -- Mike Treseler Mike, given that Xilinx did not do this in the unisim package, what do you consider to be the cleanest way to verify functional code that interfaces with these badly written (IMHO) models? Inserting delays on signals, that the synthesis tool is later going to ignore, seems like a horrible band-aid. Does it make any difference to the simulation tool if the primitives are instantiated in parallel with a functional module within a higher level structural module, versus being instantiated within an otherwise functional module? Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 38 Chauncy St #1101; Boston, MA 02111 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 122660
lkjrsy@gmail.com wrote: > Hello. > > I now have 53bit corgen adder in my design. > In order to upgrade the speed, I will do something about 53 bit adder. > so Is there anyone who know which one between Corgen and DSP48 is > faster? > > ps If there is none..... I will test them. > The DSP48 is considerably faster for 53 bits, assuming you are pipelining your add. You will have to cascade two of them to get that width, which means using the lower one as a 35 bit adder to get bit 36 out as a carry out, and adding appropriate delays to the input of the upper and output of the lower sections.Article: 122661
spgoldman@gmail.com wrote: > I currently use Altera Quartus along with ModelSim for FPGA designs > using Verilog. In ModelSim I use the "$random" term to create a > random driver. My company is considering updating its tools so that > we can get code coverage capabilities and possibly automatically > generate block diagrams from the Verilog code. I've looked into Aldec > ActiveHDL and it seems like most of this software provided redundant > functionality to that of Altera Quartus. So strictly from a > simulation and code coverage standpoint which tool is better, > considering that I would like to use Verilog/SystemVerilog for a > random driven, self-checking simulation environment? Does Aldec > support random stimuli in their tool outside of using SystemC? > I use Aldec for nearly all of my simulation (I have a Modelsim PE seat as well). For VHDL, I use the uniform function in Math_real to generate my randoms in testbenches, as that is well supported across different tools, including both Modelsim and Aldec.Article: 122662
Unless you can afford 3 cycles of latency, a DSP based adder will be the slowest option. I have tested a group of 36-bit two input adders that were implemented in HDL via the + operator, using Xilinx LUT based IP, and using Xilinx DSP48 based IP on a Virtex-4. The HDL operator based adder was the fastest for combinational adds (it was only 1MHz faster than the LUT based IP adder with the same resource usage). The added advantage of the HDL adder is that it is portable across FPGAs and much easier to work with. ---Matthew Hicks > lkjrsy@gmail.com wrote: > >> Hello. >> >> I now have 53bit corgen adder in my design. >> In order to upgrade the speed, I will do something about 53 bit >> adder. >> so Is there anyone who know which one between Corgen and DSP48 is >> faster? >> ps If there is none..... I will test them. >> > The DSP48 is considerably faster for 53 bits, assuming you are > pipelining your add. You will have to cascade two of them to get that > width, which means using the lower one as a 35 bit adder to get bit 36 > out as a carry out, and adding appropriate delays to the input of the > upper and output of the lower sections. >Article: 122663
On 1 Aug, 13:10, ctaniguc...@gmail.com wrote: > On Aug 1, 12:52 pm, "Mike Lewis" <some...@micrsoft.com> wrote: > > > > > > > <ctaniguc...@gmail.com> wrote in message > > >news:1185995501.496399.287000@q3g2000prf.googlegroups.com... > > > > Hi, > > > > Has anyone recently done a comparision of the utility of Primetime vs. > > > Xilinx or Altera timing analysis engines? Anyone have an data to > > > support if Primetime actually catches more static timing errors then > > > the FPGA vendor tools. What are the pros / cons of using Primetime > > > for FPGA timing analysis. > > > > Thanks, > > > > Craig > > > I don't think primetime supports the FPGAs .. does it? > > > Mike > > Hi Mike, > Both Altera and Xilinx tools have to option to output a netlist for > primetime and some appnotes. Just not sure if it really will buy me > anything to invest in the tool. I use primetime on the ASIC side but > have not used it for FPGAs. > > Thanks, > > Craig- Hide quoted text - > > - Show quoted text - Craig, At least for Altera, Quartus II definitely has an option to output a PrimeTime netlist with the associated SDC constraints. It also outputs a Tcl script to help you load the libraries. But the timing models are generated to match the timing models used by Quartus, so you don't get any more or less accurate timing results using PrimeTime. When compared to Xilinx tools or the Quartus Classic Timing Analyzer, you probably do get a more advance analysis. Like a good ASIC timing analyzer, PrimeTime is more conservative. For example, in PrimeTime, all clocks are assumed to be related to each other, and the user needs to explicitly enter set_clock_groups or set_false_paths to avoid this. But my experience is that Altera customers who used PrimeTime usually do so because they already have a PrimeTime license (for their ASIC work) and they have a number of scripts that they have written over the years for PrimeTime. Some customers that work with the Department of Defense also use PrimeTime as a secondary verification tool (as I believe they need to show independent verification tools). Note that one reason few use PrimeTime is that the FPGA timing analyzers are consider good enough and you still need to give the place and route tool timing constraints so for both the Xilinx and Quartus flows, you need to enter the timing constraints in the FPGA tools first, and then either have them automatically convert to an SDC or enter them again in an SDC file. For both the Xilinx Timing Analyzer and the Quartus Classic Timing Analyzer, converting the constraints from the respective proprietary format to SDC is extremely difficult (you could even argue impossible). This is because the way the timing engines deal with timing constraints is completely different from one another and when converting to an SDC, the tool needs to make several assumptions. Quartus II makes a very good attempt and can convert most assignments successfully. Last I checked (a few years ago), the Xilinx tool had some limitations in the conversion. Since we introduced the new TimeQuest Timing Analyzer (in V6.0), it is very easy for customers to use PrimeTime. The reason is that the user enters the SDC directly into Quartus II, and the required conversion is mostly about mapping node names (i.e. SDC collections) to match the PrimeTime Netlist Quartus II generates. But the constraint syntax itself is left as is. No assumptions are required. But once you try TimeQuest, you will be surprised by how good the analysis is, and how good the usability is, and finally, how similar it is to PrimeTime. You will likely see no need to re-analyze with PrimeTime. TimeQuest SDC support is basically a perfect match to PrimeTime implementation, and it supports all the advanced constraints that you can think of. FYI, it is critical that we have a perfect match to allow us to support our HardCopy II Structure ASIC design flow where the customer needs to sign-off with TimeQuest, and then a netlist and SDC is generated for the HardCopy Design Center to run the final place and route followed with final sign-off with PrimeTime. The fact that TimeQuest and PrimeTime implementation of SDC match is a big part of our seamless migration. I personally believe TimeQuest has the power of PrimeTime with the usability that Altera is so famous for. -David Karchmer Altera CorpArticle: 122664
Hello, I have a ML403 PPC design (XPS 9.1) that executes code out of DDR. I added 16 KByte of on chip data side BRAM, but the new memory space only seems to read zeroes and ignore writes. I think I checked all the usual suspects: I set the clock ratio to 3 (300 Mhz/ 100 Mhz) through the control register init value, assigned the controller address to a blank space in the PPC's map, I think I've hooked everything up, but still no joy. Same results whether the controller is set for constant BRAM enable on or off, and address range checking on or off. One other strange thing maybe related - after building, there is a system.bmm and system_stub.bmm file in the ./implementation directory. When I tell XPS to download the file, it errors-out about not finding system_bd.bmm. If I just copy one of the existing bmm files to system_bd.bmm it downloads just fine. And no, none of the apps in my project nor bootloop is marked to be loaded into BRAM. I haven't modified the system.mss file, is this an issue? Here is an excerpt from the mhs file: BEGIN ppc405_virtex4 ... BUS_INTERFACE DSOCM = dsocm_v10_0 ... END BEGIN dsocm_v10 PARAMETER INSTANCE = dsocm_v10_0 PARAMETER HW_VER = 2.00.b PARAMETER C_DSCNTLVALUE = 0x85 PORT DSOCM_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END BEGIN dsbram_if_cntlr PARAMETER INSTANCE = dsbram_if_cntlr_0 PARAMETER HW_VER = 3.00.b PARAMETER C_BRAM_EN = 1 PARAMETER C_BASEADDR = 0xE0000000 PARAMETER C_HIGHADDR = 0xE0003FFF PARAMETER C_RANGECHECK = 0 BUS_INTERFACE PORTA = dsbram_if_cntlr_0_PORTA BUS_INTERFACE DSOCM = dsocm_v10_0 END BEGIN bram_block PARAMETER INSTANCE = bram_block_0 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = dsbram_if_cntlr_0_PORTA ENDArticle: 122665
Brian Drummond wrote: > On Wed, 01 Aug 2007 19:40:40 -0700, Eric Smith <eric@brouhaha.com> > wrote: > >> ghelbig@lycos.com writes: >>> My concern is that I don't see a stable replacement in the near >>> future. It really isn't fair to Xilinx to have them support the large >>> number of popular Linux systems. >> Xilinx supports Red Hat Enterprise Linux 3 and 4; I expect that >> they'll add support for RHEL 5 in the near future, if they haven't >> already. I've never had any significant problems running software >> intended for RHEL on Fedora and Centos (the latter being a clone of >> RHEL). Many people report success on Debian, Ubuntu, and other Linux >> distributions. > > It's great that Xilinx support Linux; however getting a complete > toolchain around it isn't quite so easy. ModelSim would be an option for > simulation, except that for VHDL, they want lots of money for SE. > If LE wasn't Verilog-only, Linux would be a more compelling option. The Aldec simulator will do both on Linux, and if you are an independent consultant, for (I think) about the same price as Modelsim LE.Article: 122666
Hi, Who could enlighten me with the followings: I need to interface a SERDES transciever from a VIRTEX5 FPGA with a STRATIX II IO. Things would be easiest if I'll have a Stratix II GX instead of Stratix II, but the GX FPGA has no HARDCOPY II structured Altera ASIC corespondent, so I can't use a GX because of finacial reasons (and huge ball numbers, improper for this design). How could I get an equivalent of 3Gbps SERDES transciever (like GX has) using only high speed differential IO available in STRATIX II? thank you, VasileArticle: 122667
Evnin' Does someone knows of any books or other reading material which covers the design and implementation of forwarding engines and IP route table lookups in FPGA/ASIC? thanx in advance rickArticle: 122668
Yo, Adrian! ;) and Paul and everyone else, that's some great info and is very much appreciated. Since quartus_fit is dominating my runtime (EP2S180 and HC230), and quartus_fit gains the most from extra CPUs, it makes sense for me to go at least to 4 CPUs (I currently only have dual-processor boxes, thus the need to go shopping). Do you know if the HardCopyII fitter also makes use of multiple processors? When Quartus does spawn jobs off to up to 4 processors, can each one of those spawned jobs use up to 4GB? In the case of Quartus supporting a max of 4 processors, at the very least an 8-processor box would allow me to run two copies of Quartus at the same time (e.g., different designs, or different flavors of the same design). 8 processors on 64-bit Linux w/ 16GB of RAM with 32-bit Quartus would seem to be a well-balanced setup if most Quartus jobs remain under 2GB, correct? Since memory access is such a big part of the overall runtime, obviously the faster memory buses on newer machines will help. (Good thing, because the clock speed difference along from an Opteron 250 to a newer Opteron 2218 isn't much of an increase: 2.4GHz to 2.8GHz). Since the databases for big chips get so large (and memory accesses apparently so random), does a larger data cache buy you much? The L1 I&D caches are relatively small on both AMD and Intel, although Opteron is 2x (64K Instr, 64K Data) larger than Intel's. For the L2 cache, Intel's is 2x larger than AMDs on a per-core basis. Since Intel shares two caches between neighboring cores (as you say 1&2 or 3&4 can share quickly, but slow from 1/3 and 2/4), whereas Opterons have a dedicated cache per core, would Opterons see a speedup from less contention for the cache, or a slowdown from having to go outside the local caches in order to share data? (I guess a function of how often the quartus_fit algorithms need to share data, right?) If I were trying to run two Quartus jobs simultaneously on one 8-CPU machine (with NUM_PARALLEL_CPUS = 4 for each run), I would expect competition for external memory to be huge, and thus statistically some benefit to Intel's larger cache. And with more "stuff" cached, that the higher clock speeds on current Intel CPUs might give the runtime advantage to Intel. On the other hand, AMD has the Direct Connect Architecture and HyperTransport, so... I know you vendor guys are reluctant to publish benchmark info, but from the currently-available, mainstream, small-server perspective with 8 processors, I'm kind of pushed toward the following CPU choices: 4 dual-core Opteron 2218's (2.6 GHz, 90nm process, 2MB L2 cache as 1MB dedicated per core ) 4 dual-core Opteron 2220's (2.8 GHz, 90nm process, 2MB L2 cache as 1MB dedicated per core ) 4 dual-core Intel 5160's (3.0 GHz, 65nm process, 1333 MHz FSB, 4MB shared L2 cache) 2 quad-core Intel X5355's (2.66 GHz, 65nm process, 1333 MHz FSB, 8MB L2 cache, shared 4MB per core pair) Of those, is there an obvious bang for the buck advantage (weighted more toward bang than buck) for any one of those in particular? ------- P.S. Those QX6850's are hard to come by; Dell's overclocked XPS720's look sweet, but my company won't spring for overclocked boxes... Thanks again, very very much!Article: 122669
let me step into this discussion - because i also wanna start working with FPGA and i am still not sure, which device/board to use (buy). First i was favouring Altera/Terasic TREX or DE1 board. Then i discussed with s.o., who is using Xilinx FPGAs, and he told me, that Xilinx is providing development kits for linux (ISE&EDK) - whereas Altera doesn't. This sounded nice to me, because i am working with linux. My idea is to use SystemC & gscc writing or re-designing application in CSP-style and targeting a dedicated process to FPGA then. But now my problem: for this i need FPGA board and development kit, which provides some useful (data) IF between a host system (PC) and the FPGA board for streaming data to FPGA (for fast processing) and results back to PC (after having programmed/configured the FPGA). In an ideal world some IF, which can be easily integrated with SystemC (e.g.). I was "assuming" that the FPGA manufacturers development tools provide such (for demo application, etc). Many boards have USB IF, some ethernet. Does anybody have experiences using SystemC, ISE/EDK for CSP-style programming with targeting dedicated processes to FPGA, while the rest is working on linux PC? FrankArticle: 122670
On Jul 27, 3:34 pm, Frank Buss <f...@frank-buss.de> wrote: > Nial Stewart wrote: > > I ran a fairly quick FPGA build through Quartus to get a time for a > > before and after comparison before I did the swap. > > Did you changed the setting "use up to x number of CPUs" (don't remember > the exact name) somewhere in the project settings? > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de is there such a setting for xilinx ise as well? thx, -weiArticle: 122671
On Jul 27, 3:56 pm, Patrick Dubois <prdub...@gmail.com> wrote: > On Jul 26, 6:19 pm, jjohn...@cs.ucf.edu wrote: > > > AMD or Intel? > > ------------------- > > Between AMD & Intel's latest multicore CPUs, > > - Which offers the best integer performance? > > - Which offers the best floating-point performance? > > Specific models within the AMD/Intel family? > > > Assume cost is no object, and each uses its highest-performing memory > > interface, but disk access is (necessary evil) over a networked drive. > > (Small % of total runtime anyway.) > > > Multi-core, multi-processor, or both? 32-bit or 64-bit? Linux vs. > > Windows? >2GB of RAM? > > If cost is no object, then go with the Intel quad-core running at 3 > GHz : QX6850. Each core has 2 MB of L2 cache (8MB total), which is, > according to several reports in this forum, the single most important > factor. > > I would say go with 4GB of ram, although if you're using the biggest > chips, you might need more. Keep in mind that Windows 32-bit will only > be able to use 3GB max of this 4 GB, and each application will only be > able to access 2GB max. So you might consider Windows 64 bits or Linux > 64 bits if necessary. > > Patrick Why only 3GB max of 4GB? thanks, -WeiArticle: 122672
On Aug 2, 9:42 pm, Wei Wang <camww...@gmail.com> wrote: > On Jul 27, 3:34 pm, Frank Buss <f...@frank-buss.de> wrote: > > > Nial Stewart wrote: > > > I ran a fairly quick FPGA build through Quartus to get a time for a > > > before and after comparison before I did the swap. > > > Did you changed the setting "use up to x number of CPUs" (don't remember > > the exact name) somewhere in the project settings? > > > -- > > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de > > is there such a setting for xilinx ise as well? > > thx, -wei Found similar memory recommendations for Xilinx's largest XC5VLX330 FPGA, http://www.xilinx.com/ise/products/memory.htm#v5lx only Linux-64 machines are supported, memory recommendation: typical 7.2GB and peak 10.6GB.Article: 122673
> However, > if I preferred verilog, > or synopsys style vhdl, > or if I just wanted to > wire up some cores, > then it would still be a wash. > > -- Mike Treseler voted as the best FPGA poem :-)Article: 122674
"Wei Wang" <camwwang@gmail.com> wrote in message news:1186091680.680639.251840@z24g2000prh.googlegroups.com... > Found similar memory recommendations for Xilinx's largest XC5VLX330 > FPGA, > http://www.xilinx.com/ise/products/memory.htm#v5lx > only Linux-64 machines are supported, memory recommendation: typical > 7.2GB and peak 10.6GB. This web page needs to be updated: NT64 is also supported, but runtime will be faster on Linux64, so that's what we recommend. Steve
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