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Hi Alan, Alan Fitch <apf@invalid.invalid> wrote: > I used to work for Doulos, and teach SystemC and TML2 - we regularly ran > courses at CERN, but normally VHDL and some Expert VHDL. Something makes > me think you're based at CERN. I used to, has been a fun ride. Too bad I never got the chance to follow a course of yours. It seems now they are more and more pushing for SystemVerilog, while I lately was trying to fight my way with OSVVM which I find more appropriate for that type of community. > Knowing C++ is a definite advantage! Uhm, 'knowing' is actually a bit vague, considering that I strongly believe that in order to 'know' a language it takes ~10 years of practice in the field! (I actually find this reading quite at the point: http://norvig.com/21-days.html) > Have a look at the Doulos website, or email info@doulos.com, I did. BTW I found that A.L.S.E. (http://www.alse-fr.com/about.php) provides the very same course from Doulos, are the instructors coming from Doulos or they are simply acting as a gateaway to Doulos courses? AlArticle: 157101
On 11/10/14 15:27, alb wrote: > Hi Alan, > > Alan Fitch <apf@invalid.invalid> wrote: >> I used to work for Doulos, and teach SystemC and TML2 - we regularly ran >> courses at CERN, but normally VHDL and some Expert VHDL. Something makes >> me think you're based at CERN. > > I used to, has been a fun ride. Too bad I never got the chance to follow > a course of yours. It seems now they are more and more pushing for > SystemVerilog, while I lately was trying to fight my way with OSVVM > which I find more appropriate for that type of community. > I'm afraid it's "the dead hand of the market"... >> Knowing C++ is a definite advantage! > > Uhm, 'knowing' is actually a bit vague, considering that I strongly > believe that in order to 'know' a language it takes ~10 years of > practice in the field! (I actually find this reading quite at the point: > http://norvig.com/21-days.html) > People who know C++ well, and who have some experience of VHDL or Verilog generally get on well with SystemC as "it's just another class library". If you know VHDL/Verilog but don't know any object orientated language it can be "challenging" :-) However knowing Java (for instance) doesn't mean you know C++ of course (though can be quite helpful when learning SystemVerilog!). The Doulos Comprehensive SystemC includes 2 days of C++ at the beginning, aimed at people who know C but not C++. For on-site training the courses can be customised - but trying to compress the equivalent of 2 days C++ + 2 days SystemC + 3 days TLM2 can lead to peoples' brains metaphorically exploding. >> Have a look at the Doulos website, or email info@doulos.com, > > I did. BTW I found that A.L.S.E. (http://www.alse-fr.com/about.php) > provides the very same course from Doulos, are the instructors coming > from Doulos or they are simply acting as a gateaway to Doulos courses? > ALSE have their own instructors. I remember they had one person up-to-scratch with SystemC. Generally they ran the courses in French. They use the same Doulos materials. regards Alan -- Alan FitchArticle: 157102
Hi, >These last few months, I have been slowly moving back to my main interests might be a good idea to spend some time reading what actually exists. I'm no expert on the field but enough to have an opinion :-) that everybody is looking for the holy grail but few if any ideas evolve to the point where they are actually being used by someone else in a product. Have a look at this, for example http://tce.cs.tut.fi/download.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 157103
Hello I am trying to implement a design containing a picoBlaze (source code I hav= e already used numerous times) in a new project with ISE 14.6, and synthesi= s chokes on the numerous INIT parameters that are encased in translate_off/= translate_on directives and should therefore be ignored. Has the directives support changed since previous versions ? Is there some = setting I should have set when creating the project ? NicolasArticle: 157104
I am student of Bachelors and going to start my FYP in some days. I am going into the field of high computation in verilog. These are some projects which I might be doing: 1.the n-body gravitational problem 2.Oceanic modeling 3.Cancer biology modeling Any other projects you might suggest that may be beneficial for me. And also my main aim after Bachelors is to get admission in some US university. Thanks!Article: 157105
And also, I have spartan 6 xc6slx45 kit available in college Lab.Article: 157106
Hi Alan, > > I used to, has been a fun ride. Too bad I never got the chance to follow > > > a course of yours. It seems now they are more and more pushing for > > > SystemVerilog, while I lately was trying to fight my way with OSVVM > > > which I find more appropriate for that type of community. > > > > > > > I'm afraid it's "the dead hand of the market"... Perhaps a shrinking market for Doulos, however, it has been a growing market for us (including in UK). What I do see in SystemVerilog's favor is the vendors are pushing the user community heavily to it since they can make more money with SystemVerilog licenses. OTOH, recently we have had people switching from SystemVerilog to VHDL/OSVVM because their projects could not afford the pricing of a SystemVerilog simulator when OSVVM can do the same thing. Cheers, JimArticle: 157107
Hi, >> verilog. >> These are some projects which I might be doing: >> spartan 6 xc6slx45 kit >>1.the n-body gravitational problem >>2.Oceanic modeling >>3.Cancer biology modeling this is not to discourage you. But please be warned that heavy-duty FPGA implementations as youre planning are *much* and I mean "much" harder than it looks from all those shiny webpages that make it look like Lego bricks because they want to sell you stuff. Here's my proposal: Why don't you implement "Hello world!" in Morse code. Which is ".... . .-.. .-.. --- .-- --- .-. .-.. -.. " Just a blinking LED. Expect that i'll take between a day and two weeks. This includes things that "should" be easy but are not, such as installing ISE 14.7 when you've never done it before, making the JTAG interface work etc. In my personal opinion, the xc6slx45 is an excellent choice to get started. Because a) it does not require a Xilinx license to program it b) I can get one cheaply if you ever need one, i.e. "Numato Saturn" or "Pipistrello" boards, for ~$130..160. c) If it breaks, it's no big deal, compared to a $3000+ board. To learn Verilog, the smallest and cheapest FPGA will do, if you decide to buy one for yourself. The typical feedback from the board is "this doesn't work - go simulate some more". Note, you said "Verilog", not using some intermediate wizardry that generates the code. For the latter, a sxl45 is probably too small (guessing, haven't done it myself). --------------------------------------- Posted through http://www.FPGARelated.comArticle: 157108
>> b) I can get one cheaply if you ever need one heh that was supposed to read "-you- can get one cheaply". I don't run a shop :-) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 157109
nmatringe@gmail.com wrote: > Hello > I am trying to implement a design containing a picoBlaze (source code I have already used numerous times) in a new project with ISE 14.6, and synthesis chokes on the numerous INIT parameters that are encased in translate_off/translate_on directives and should therefore be ignored. > Has the directives support changed since previous versions ? Is there some setting I should have set when creating the project ? > > Nicolas Some older sources use "synopsis translate_on/_off" rather than "synthesis translate_on/_off" syntax. If this is the problem in PicoBlaze, the synopsis syntax may have been deprecated. -- GaborArticle: 157110
awaish2011@namal.edu.pk wrote: > I am student of Bachelors and going to start my FYP in some days. > I am going into the field of high computation in verilog. There has been work for years on doing computationally intensive problems in FPGAs, much of it hasn't worked out very well. One problem is that it is hard to do economically. That is, such that someone will buy the product. > These are some projects which I might be doing: > 1.the n-body gravitational problem > 2.Oceanic modeling > 3.Cancer biology modeling I was once thinking about doing a biology related problem, and decided that I could do it with 2000 of the largest S3 FPGAs. That was still a little too big at the time. There are some interesting projects out there, but you have to compete with the non-FPGA based solutions, and the fact that the actual solution might not be needed. For example, the n-body problem might be useful to those at NASA trying to get rockets to far away planets. But being able to do 0.1% or 1% better (in fuel use or arrival time) isn't worth all that much. You have to be able to do a lot better to make it worth spending money on. > Any other projects you might suggest that may be beneficial for me. > And also my main aim after Bachelors is to get admission in some > US university. Planning ahead is useful. The projects you mention will take teams of researchers years to work on. (You have to include packaging and software and user manuals, so that ordinary people can use them.) For a more reasonably sized project, implement a character based computer terminal. That is, a keyboard, display, and serial port. (Note that many FPGA boards have the hardware to do this.) In years long past, it wasn't an unusual undergraduate project built out of a microprocessor and TTL parts. Now, it should be a reasonable sized FPGA project. You can separately work on the keyboard input, UART (find one on opencores, but you still have to figure out how to use it), and character based raster display. You have to get the timing right for an available video monitor. -- glenArticle: 157111
maybe this still, before someone quotes me later: When I say the FPGA you mentioned is an "excellent choice", I meant for _learning_, as you can use it on your own PC without $2999 license. Not for high performance computing. Spartan 6 is marketed with "delivers an optimal balance of low risk, low cost, and low power for cost-sensitive applications". --------------------------------------- Posted through http://www.FPGARelated.comArticle: 157112
On 10/13/2014 12:09 PM, awaish2011@namal.edu.pk wrote: > I am student of Bachelors and going to start my FYP in some days. I am going into the field of high computation in verilog. These are some projects which I might be doing: > 1.the n-body gravitational problem > 2.Oceanic modeling > 3.Cancer biology modeling > > Any other projects you might suggest that may be beneficial for me. > And also my main aim after Bachelors is to get admission in some US university. > Thanks! How about something a little more practical? I expect there is not much room for improvement for solving gravitational problems much faster or more accurately. Is there really a need? Oceanic modeling is a huge area. You might want to narrow the focus on that one a *lot* more before you try to narrow your list... or just remove it. Cancer biology modeling is also a *huge* area. I do recall some years ago there was a small project at NIH (if I remember correctly) who was working on a real time interactive model of complex molecules. They would model the forces of a molecule and let the researcher use a pair of many degrees of freedom controls to bend and twist the molecule while getting haptic feedback. I'm not sure what happened to this project as I haven't seen anywhere that it became a widely useful tool. Interesting though. An area I find interesting is low power processing. You might consider what it takes to do something with a minimum of power consumption using off the shelf devices. There are a lot of potential applications there. -- RickArticle: 157113
Hi, > >These last few months, I have been slowly moving back to my main > interests > might be a good idea to spend some time reading what actually exists.=20 I am actually an expert on the field (PhD: Development of an application-sp= ecific processor design methodology, awarded June 2008), I have known of th= e TTA/TCE tool albeit this being a latter development. I have already menti= oned TCE in my original post:=20 > and the academic **TCE** and NISC toolsets. So to my knowledge there is no omission of an important ASIP synthesis (or = design) technology in the original post. The TTA/TCE toolset is essentially a collection of passes along with a back= end for a TTA (Transport-Triggered Architecture) architecture that can be c= onfigured and extended. It may be a matter of perspective (or not), since m= apping to a TTA has been a well-studied problem (since the seminal work of = Prof. Corporaal back in the 90s) and in my view it counts as ASIP design/co= nfiguration and not ASIP synthesis. This is a nice addition and some people= do use the toolset. However, it is not processor synthesis per se, at leas= t without the TTA precondition. This is the case since as the TCE developers state:=20 > Processor customization points include the register files, function units= ,=20 > supported operations, and the interconnection network. The Grail is nice to have and an open research subject! I felt compelled to= write about it. Best regards Nikolaos Kavvadias http://www.nkavvadias.com >=20 > I'm no expert on the field but enough to have an opinion :-) that everybo= dy > is looking for the holy grail but few if any ideas evolve to the point > where they are actually being used by someone else in a product. > > Have a look at this, for example > http://tce.cs.tut.fi/download.html =20 >=20 > =09 >=20 > --------------------------------------- =09 >=20 > Posted through http://www.FPGARelated.comArticle: 157114
To follow this up, my own processor, ByoRISC (Build Your Own RISC) is an ex= emplar of ASIP design but not ASIP synthesis, despite the fact that you cou= ld explore and generate custom instructions using my tool YARDstick: http:/= /www.nkavvadias.com/yardstick/ ByoRISC references (I have not made the code available): - http://www.nkavvadias.com/publications/kavvadias_vlsisoc08.pdf - http://arxiv.org/abs/1403.6632 YARDstick references=20 - http://www.nkavvadias.com/yardstick/yardstick_date07_abstract.pdf - http://www.nkavvadias.com/publications/kavvadias_melecon06_cr.pdf - http://arxiv.org/abs/1403.7380 This is why I haven't included it into technologies directly related to ASI= P synthesis, although it is certainly *indirectly* related! Best regards Nikolaos Kavvadias http://www.nkavvadias.com =CE=A4=CE=B7 =CE=A4=CF=81=CE=AF=CF=84=CE=B7, 14 =CE=9F=CE=BA=CF=84=CF=89=CE= =B2=CF=81=CE=AF=CE=BF=CF=85 2014 7:50:57 =CF=80.=CE=BC. UTC+3, =CE=BF =CF= =87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nikolaos Kavvadias =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > Hi, >=20 >=20 >=20 > > >These last few months, I have been slowly moving back to my main >=20 > > interests >=20 > > might be a good idea to spend some time reading what actually exists.= =20 >=20 >=20 >=20 > I am actually an expert on the field (PhD: Development of an application-= specific processor design methodology, awarded June 2008), I have known of = the TTA/TCE tool albeit this being a latter development. I have already men= tioned TCE in my original post:=20 >=20 >=20 >=20 > > and the academic **TCE** and NISC toolsets. >=20 >=20 >=20 > So to my knowledge there is no omission of an important ASIP synthesis (o= r design) technology in the original post. >=20 >=20 >=20 > The TTA/TCE toolset is essentially a collection of passes along with a ba= ckend for a TTA (Transport-Triggered Architecture) architecture that can be= configured and extended. It may be a matter of perspective (or not), since= mapping to a TTA has been a well-studied problem (since the seminal work o= f Prof. Corporaal back in the 90s) and in my view it counts as ASIP design/= configuration and not ASIP synthesis. This is a nice addition and some peop= le do use the toolset. However, it is not processor synthesis per se, at le= ast without the TTA precondition. >=20 >=20 >=20 > This is the case since as the TCE developers state:=20 >=20 >=20 >=20 > > Processor customization points include the register files, function uni= ts,=20 >=20 > > supported operations, and the interconnection network. >=20 >=20 >=20 > The Grail is nice to have and an open research subject! I felt compelled = to write about it. >=20 >=20 >=20 > Best regards >=20 > Nikolaos Kavvadias >=20 > http://www.nkavvadias.com >=20 >=20 >=20 >=20 >=20 > >=20 >=20 > > I'm no expert on the field but enough to have an opinion :-) that every= body >=20 > > is looking for the holy grail but few if any ideas evolve to the point >=20 > > where they are actually being used by someone else in a product. >=20 > > >=20 > > Have a look at this, for example >=20 > > http://tce.cs.tut.fi/download.html >=20 > =20 >=20 > >=20 >=20 > > =09 >=20 > >=20 >=20 > > --------------------------------------- =09 >=20 > >=20 >=20 > > Posted through http://www.FPGARelated.comArticle: 157115
Le lundi 13 octobre 2014 22:56:24 UTC+2, Gabor a =E9crit=A0: > nmatringe@gmail.com wrote: >> I am trying to implement a design containing a picoBlaze (source code I = have already used numerous times) in a new project with ISE 14.6, and synth= esis chokes on the numerous INIT parameters that are encased in translate_o= ff/translate_on directives and should therefore be ignored. >=20 > Some older sources use "synopsis translate_on/_off" rather than > "synthesis translate_on/_off" syntax. If this is the problem > in PicoBlaze, the synopsis syntax may have been deprecated. It seems to me that the documentation mentions "synopsis" as a valid direct= ive, unless I read an old version. Anyway the source actually uses "synthes= is" as a key word. What puzzles me the most is that older projects using the exact same pB sou= rce (I diffed the files) imported into 14.6 implement just fine. NicolasArticle: 157116
Le mardi 14 octobre 2014 10:23:30 UTC+2, nmat...@gmail.com a =E9crit=A0: > What puzzles me the most is that older projects using the exact same pB s= ource (I diffed the files) imported into 14.6 implement just fine. The problem is actually with attributes, not with the generic parameters an= d synthesis directives. I'm still puzzled older design work... An example of error message I get: ERROR:Xst:3154 - "C:\Users\nmatring\Documents\NGC_sniffer\FPGA\src\kcpsm3.v= hd". Line 289. Unable to set attribute "INIT" with value "1" on instance <t= _state_lut> of block <LUT1>. This property is already defined with value "0= " on the block definition by a VHDL generic or a Verilog parameter. Apply t= he desired value by overriding the default VHDL generic or Verilog paramete= r. Using an attribute is not allowed. NicolasArticle: 157117
Silly me... https://www.google.fr/?gws_rd=ssl#q=xilinx+error+xst+3154 My older projects were targetting Spartan 3 and weren't impacted. Case closed. NicolasArticle: 157118
Hello, we have developed IDE for Xilinx's softcore processor PicoBlaze with features like macro assembler, simulator and other various tools. Noncommercial license is free of charge. We'll be glad for any feedback or suggestions of features that you would like to see in next version. www.moravia-microsystems.com/multitarget-development-system/ Regards MMSystems teamArticle: 157119
Hi Jim, Jim Lewis <usevhdl@gmail.com> wrote: [] > What I do see in SystemVerilog's favor is the vendors are pushing the > user community heavily to it since they can make more money with > SystemVerilog licenses. This is one of our concerns as well. While the OSVVM seems covering the needs in terms of functionality, it still lacks the support needed in terms of verification IPs which may be a big plus (or minus). Do you see anything coming soon on that side of the market or people using OSVVM will be forced to develop their own verification IPs? > OTOH, recently we have had people switching from SystemVerilog to > VHDL/OSVVM because their projects could not afford the pricing of a > SystemVerilog simulator when OSVVM can do the same thing. Same here. Management won't provide the necessary means to go buying licenses for SV simulators and on top of that most of our team is hardware oriented. We actually proposed several training courses on OSVVM for next year budget hoping to get at least a couple (and I'm not included!). AlArticle: 157120
Is it possible to run a Vivado simulation in non-project mode? I can't seem to find any documentation on how to do it. ug835 describes which Tcl commands are used for simulation, but not which to use for non-project mode. //Petter -- .sig removed by request.Article: 157121
nmatringe@gmail.com wrote: > Silly me... > https://www.google.fr/?gws_rd=ssl#q=xilinx+error+xst+3154 > > My older projects were targetting Spartan 3 and weren't impacted. > Case closed. > > Nicolas You didn't mention the new target device, but I assume it is 6-series or newer? That's when the "new parser" was introduced. -- GaborArticle: 157122
there are two ways: you can use xvlog and xsim or you can use vivado -mode tcl -source foo.tcl with a foo.tcl which has: create_project -force foo_proj_1 add_files bar.v run -all The second form allows you to restart a simulation after you edit the files. On Tuesday, October 14, 2014 6:05:07 AM UTC-7, Petter Gustad wrote: > Is it possible to run a Vivado simulation in non-project mode? > > > > I can't seem to find any documentation on how to do it. ug835 describes > > which Tcl commands are used for simulation, but not which to use for > > non-project mode. > > > > //Petter > > -- > > .sig removed by request.Article: 157123
vincent.stay@gmail.com writes: Thank you for your reply. > there are two ways: > you can use xvlog and xsim I thought these were available as Tcl commands within Vivado. But I guess xvlog/xvhdl, xelab, and xsim will do what I was looking for. > or you can use > vivado -mode tcl -source foo.tcl > > with a foo.tcl which has: > create_project -force foo_proj_1 > add_files bar.v > run -all > > The second form allows you to restart a simulation after you edit the files. The latter was a project mode script, even though the project overhead seem to be minimal. Again, I think xvlog/xelab/xsim will do what I want. > On Tuesday, October 14, 2014 6:05:07 AM UTC-7, Petter Gustad wrote: >> Is it possible to run a Vivado simulation in non-project mode? >> >> >> >> I can't seem to find any documentation on how to do it. ug835 describes >> >> which Tcl commands are used for simulation, but not which to use for >> >> non-project mode. >> >> >> >> //Petter >> >> -- >> >> .sig removed by request. > Best regards //Petter -- .sig removed by request.Article: 157124
rickman <gnuarm@gmail.com> wrote: > Oceanic modeling is a huge area. You might want to narrow the focus on > that one a *lot* more before you try to narrow your list... or just > remove it. The trouble with all these projects is they're something a GPU could do with much less programming effort (at least to make it work non-optimally). So I'm not sure the advantage of using an FPGA. In an FPGA it's a lot harder to change the architecture if the problem changes (at least if you're writing in Verilog/VHDL it is). > An area I find interesting is low power processing. You might consider > what it takes to do something with a minimum of power consumption using > off the shelf devices. There are a lot of potential applications there. One thing FPGAs are good at I/O. So a nice example is video processing - you take in video from a camera, do something clever to it, and output to a display. There's a lot of data so you have to process it fast, and it's a nice visual demo. It's also easy to debug - you can see what's going wrong on the screen. Likewise other kinds of non-optical data (eg scan data from a 2D sensor of some kind). You can also use audio or other sensors, as long as you have a useful output. Theo
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