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On 4/8/2016 12:14 AM, Jon Elson wrote: > > So, Xilinx is working for me. And, yes, after going to the trouble of > getting comfortable in the Xilinx tools, the last thing I want to do is > learn somebody else's tools' quirks. What tool quirks. I think that is mostly a Xilinx domain. Altera tools just work and I've yet to find much in the way of problems with the Lattice tools. They never tried to roll their own, so I guess that is a plus. I'll be finding out how good Microsemi tools are soon. I've got a Smartfusion2 kickstart board and want to play with it. But the Avnet site is no working this week because of a massive upgrade. They actually made the board and I've not yet found much in the way of getting started info. I guess I should just rely on Microsemi to get me started on the tools and figure out the kickstart board specifics once I'm up with the tools. -- RickArticle: 158776
On Wednesday, April 6, 2016 at 11:51:16 AM UTC-4, rickman wrote: > You should be able to design one board with an FPGA, a 386 socket and a > 386 plug which will work for any of the three things you have talked > about doing, emulating the mobo with your FPGA, emulating the 386 with > your FPGA and monitoring the 386 in a real mobo with the FPGA. > > 386 Chip > ____________ > ++++++++++++ FPGA > ============== _____________ > |||||||||||| ,,,,,,,,,,,,, > =================================================== PCB > |||||||||||| > Plugs into 386 Mobo > > When emulating the 386 unplug it from the socket. When emulating the > mobo, unplug from the mobo. When monitoring the 386 in operation plug > in the 386 and plug the board into the mobo. > > If you aren't in a hurry, I can help you with the PCB design. I can use > this as a learning tool to come up to speed with KiCAD which I've been > meaning to do. I think I'd like to design this board, but without the plugs into the 386 motherboard. Would you still be willing to help me with design? I'll get the pinouts and work up a circuit and wiring diagram proposal in multi-layer image format for inspection. Do you know what part number I'd need for the level converters? Best regards, Rick C. HodginArticle: 158777
On 4/8/2016 8:14 AM, Rick C. Hodgin wrote: > On Wednesday, April 6, 2016 at 11:51:16 AM UTC-4, rickman wrote: >> You should be able to design one board with an FPGA, a 386 socket and a >> 386 plug which will work for any of the three things you have talked >> about doing, emulating the mobo with your FPGA, emulating the 386 with >> your FPGA and monitoring the 386 in a real mobo with the FPGA. >> >> 386 Chip >> ____________ >> ++++++++++++ FPGA >> ============== _____________ >> |||||||||||| ,,,,,,,,,,,,, >> =================================================== PCB >> |||||||||||| >> Plugs into 386 Mobo >> >> When emulating the 386 unplug it from the socket. When emulating the >> mobo, unplug from the mobo. When monitoring the 386 in operation plug >> in the 386 and plug the board into the mobo. >> >> If you aren't in a hurry, I can help you with the PCB design. I can use >> this as a learning tool to come up to speed with KiCAD which I've been >> meaning to do. > > I think I'd like to design this board, but without the plugs into the > 386 motherboard. > > Would you still be willing to help me with design? I'll get the pinouts > and work up a circuit and wiring diagram proposal in multi-layer image > format for inspection. > > Do you know what part number I'd need for the level converters? I use SN74CBTD3384 on a board I produce. I prefer the TSSOP (PW) package, but that will depend on how you wish to layout the board. There is a smaller package, the TVSOP (DGV) and some larger. No DIPs I'm afraid. If you want to get a board made, you need to use a layout package. I don't know of any PCB fab houses that will work with custom art. It has to be a layout package format or Gerber files. -- RickArticle: 158778
On Friday, April 8, 2016 at 1:29:49 PM UTC-4, rickman wrote: > On 4/8/2016 8:14 AM, Rick C. Hodgin wrote: > > On Wednesday, April 6, 2016 at 11:51:16 AM UTC-4, rickman wrote: > >> You should be able to design one board with an FPGA, a 386 socket and a > >> 386 plug which will work for any of the three things you have talked > >> about doing, emulating the mobo with your FPGA, emulating the 386 with > >> your FPGA and monitoring the 386 in a real mobo with the FPGA. > >> > >> 386 Chip > >> ____________ > >> ++++++++++++ FPGA > >> ============== _____________ > >> |||||||||||| ,,,,,,,,,,,,, > >> =================================================== PCB > >> |||||||||||| > >> Plugs into 386 Mobo > >> > >> When emulating the 386 unplug it from the socket. When emulating the > >> mobo, unplug from the mobo. When monitoring the 386 in operation plug > >> in the 386 and plug the board into the mobo. > >> > >> If you aren't in a hurry, I can help you with the PCB design. I can use > >> this as a learning tool to come up to speed with KiCAD which I've been > >> meaning to do. > > > > I think I'd like to design this board, but without the plugs into the > > 386 motherboard. > > > > Would you still be willing to help me with design? I'll get the pinouts > > and work up a circuit and wiring diagram proposal in multi-layer image > > format for inspection. > > > > Do you know what part number I'd need for the level converters? > > I use SN74CBTD3384 on a board I produce. I prefer the TSSOP (PW) > package, but that will depend on how you wish to layout the board. > There is a smaller package, the TVSOP (DGV) and some larger. No DIPs > I'm afraid. > > If you want to get a board made, you need to use a layout package. I > don't know of any PCB fab houses that will work with custom art. It has > to be a layout package format or Gerber files. Understood. The idea of the image format would be to present to you my initial work, so you could scrutinize it and give me notes. I would adjust it, and then once it's in final form, translate it to a layout tool. I have long-term goals to write a software program called Logician, which is a logic layout tool which will include routing abilities. So, this would be an early implementation of that algorithm so the bitlines are not trumped by their neighbors. :-) I envision a 4- or 6-layer board with vias. Best regards, Rick C. HodginArticle: 158779
On 4/8/2016 1:33 PM, Rick C. Hodgin wrote: > On Friday, April 8, 2016 at 1:29:49 PM UTC-4, rickman wrote: >> On 4/8/2016 8:14 AM, Rick C. Hodgin wrote: >>> On Wednesday, April 6, 2016 at 11:51:16 AM UTC-4, rickman wrote: >>>> You should be able to design one board with an FPGA, a 386 socket and a >>>> 386 plug which will work for any of the three things you have talked >>>> about doing, emulating the mobo with your FPGA, emulating the 386 with >>>> your FPGA and monitoring the 386 in a real mobo with the FPGA. >>>> >>>> 386 Chip >>>> ____________ >>>> ++++++++++++ FPGA >>>> ============== _____________ >>>> |||||||||||| ,,,,,,,,,,,,, >>>> =================================================== PCB >>>> |||||||||||| >>>> Plugs into 386 Mobo >>>> >>>> When emulating the 386 unplug it from the socket. When emulating the >>>> mobo, unplug from the mobo. When monitoring the 386 in operation plug >>>> in the 386 and plug the board into the mobo. >>>> >>>> If you aren't in a hurry, I can help you with the PCB design. I can use >>>> this as a learning tool to come up to speed with KiCAD which I've been >>>> meaning to do. >>> >>> I think I'd like to design this board, but without the plugs into the >>> 386 motherboard. >>> >>> Would you still be willing to help me with design? I'll get the pinouts >>> and work up a circuit and wiring diagram proposal in multi-layer image >>> format for inspection. >>> >>> Do you know what part number I'd need for the level converters? >> >> I use SN74CBTD3384 on a board I produce. I prefer the TSSOP (PW) >> package, but that will depend on how you wish to layout the board. >> There is a smaller package, the TVSOP (DGV) and some larger. No DIPs >> I'm afraid. >> >> If you want to get a board made, you need to use a layout package. I >> don't know of any PCB fab houses that will work with custom art. It has >> to be a layout package format or Gerber files. > > Understood. The idea of the image format would be to present to you my > initial work, so you could scrutinize it and give me notes. I would > adjust it, and then once it's in final form, translate it to a layout > tool. > > I have long-term goals to write a software program called Logician, which > is a logic layout tool which will include routing abilities. So, this > would be an early implementation of that algorithm so the bitlines are > not trumped by their neighbors. :-) > > I envision a 4- or 6-layer board with vias. To start, I suggest you take a look at FreePCB. It has an easy learning curve and support in a Yahoo group. Stick to a 4 layer board for cost. I can't see any reason why this would not be easy. Pick an FPGA in a non-BGA package if you can. I don't recall how many I/O you need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin QFPs around. Even if you go with an older FPGA like a Spartan 3A the wider pitch package is worth it. If you have to use a BGA, pick one with a wide ball spacing like 1.0 mm. -- RickArticle: 158780
On Friday, April 8, 2016 at 1:58:12 PM UTC-4, rickman wrote:
> On 4/8/2016 1:33 PM, Rick C. Hodgin wrote:
> > On Friday, April 8, 2016 at 1:29:49 PM UTC-4, rickman wrote:
> >> On 4/8/2016 8:14 AM, Rick C. Hodgin wrote:
> >>> On Wednesday, April 6, 2016 at 11:51:16 AM UTC-4, rickman wrote:
> >>>> You should be able to design one board with an FPGA, a 386 socket and a
> >>>> 386 plug which will work for any of the three things you have talked
> >>>> about doing, emulating the mobo with your FPGA, emulating the 386 with
> >>>> your FPGA and monitoring the 386 in a real mobo with the FPGA.
> >>>>
> >>>> 386 Chip
> >>>> ____________
> >>>> ++++++++++++ FPGA
> >>>> ============== _____________
> >>>> |||||||||||| ,,,,,,,,,,,,,
> >>>> =================================================== PCB
> >>>> ||||||||||||
> >>>> Plugs into 386 Mobo
> >>>>
> >>>> When emulating the 386 unplug it from the socket. When emulating the
> >>>> mobo, unplug from the mobo. When monitoring the 386 in operation plug
> >>>> in the 386 and plug the board into the mobo.
> >>>>
> >>>> If you aren't in a hurry, I can help you with the PCB design. I can use
> >>>> this as a learning tool to come up to speed with KiCAD which I've been
> >>>> meaning to do.
> >>>
> >>> I think I'd like to design this board, but without the plugs into the
> >>> 386 motherboard.
> >>>
> >>> Would you still be willing to help me with design? I'll get the pinouts
> >>> and work up a circuit and wiring diagram proposal in multi-layer image
> >>> format for inspection.
> >>>
> >>> Do you know what part number I'd need for the level converters?
> >>
> >> I use SN74CBTD3384 on a board I produce. I prefer the TSSOP (PW)
> >> package, but that will depend on how you wish to layout the board.
> >> There is a smaller package, the TVSOP (DGV) and some larger. No DIPs
> >> I'm afraid.
> >>
> >> If you want to get a board made, you need to use a layout package. I
> >> don't know of any PCB fab houses that will work with custom art. It has
> >> to be a layout package format or Gerber files.
> >
> > Understood. The idea of the image format would be to present to you my
> > initial work, so you could scrutinize it and give me notes. I would
> > adjust it, and then once it's in final form, translate it to a layout
> > tool.
> >
> > I have long-term goals to write a software program called Logician, which
> > is a logic layout tool which will include routing abilities. So, this
> > would be an early implementation of that algorithm so the bitlines are
> > not trumped by their neighbors. :-)
> >
> > I envision a 4- or 6-layer board with vias.
>
> To start, I suggest you take a look at FreePCB. It has an easy
> learning curve and support in a Yahoo group. Stick to a 4 layer board
> for cost.
FreePCB looks good. How much should a board like this cost?
> I can't see any reason why this would not be easy. Pick an
> FPGA in a non-BGA package if you can. I don't recall how many I/O you
> need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin
> QFPs around. Even if you go with an older FPGA like a Spartan 3A the
> wider pitch package is worth it. If you have to use a BGA, pick one
> with a wide ball spacing like 1.0 mm.
I had planned on using my Altera Cyclone V GX dev board with this FPGA:
http://wl.altera.com/products/devkits/altera/kit-terasic-cyclone-v-gx-starter.html
I have an adapter coming which leverages the HSMC port to GPIO ports:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=67&No=322&PartNo=2#section
I'm going to begin working on my Logician tool off-and-on this year.
It will allow me to program logic gates and handle translation to a
physical process, along with wire routing. It will include a full
simulator, and an export-to-Verilog module, which I will use for the
general purpose logic.
Best regards,
Rick C. Hodgin
Article: 158781rickman wrote: > On 4/8/2016 12:14 AM, Jon Elson wrote: >> >> So, Xilinx is working for me. And, yes, after going to the trouble of >> getting comfortable in the Xilinx tools, the last thing I want to do is >> learn somebody else's tools' quirks. > > What tool quirks. I didn't really mean quirks as in things that didn't work, or work right. I just meant that each tool chain has a lot of features to learn, where the optional settings are hidden, how to quickly configure the simulator, how to set up to generate configuration PROM images, etc. There is a lot to learn before you get fully productive. JonArticle: 158782
rickman wrote: > > I use SN74CBTD3384 on a board I produce. Also, the 74LVC8T245 is a good bidirectional translator, 8 bits in a 24-pin package. Or, the 74ALVC164245DL, two independent 8-bit translators in a 48- pin package. I've used a bunch of both of these in some gear I have produced, mostly to connect between FPGAs with 3.3 V I/O and 5V systems. I also used the former to connect 5 V systems to the old Beagle Board computer, which had 1.8 V I/O. JonArticle: 158783
Rick C. Hodgin wrote: I'll get the pinouts > and work up a circuit and wiring diagram proposal in multi-layer image > format for inspection. Complex designs like this require GOOD schematic and PCB layout tools. I use an old one, Protel 99SE, but that is no longer available, and was pretty expensive when it was. I have used Kicad a little, it shows REAL promise, but is not yet as good as Protel. It runs on Windows AND Linux! And, it is free, open-source software. The advantage of these packages is you can do copper pours, inner power plane layers, and it checks the correctness of the PCB layout against the schematic. No human could EVER be sure that a complex PCB layout was correct, no matter how long they looked at it. Software DRC takes just a couple seconds. JonArticle: 158784
rickman wrote: > I don't recall how many I/O you > need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin > QFPs around. Even if you go with an older FPGA like a Spartan 3A the > wider pitch package is worth it. If you have to use a BGA, pick one > with a wide ball spacing like 1.0 mm. > I have learned how to solder QFPs down to 0.4mm pitch, but it takes a TINY soldering tip, a stereo zoom microscope and a STEADY hand! 0.65 mm pitch is pretty easy, at least for me. JonArticle: 158785
On 4/8/2016 2:49 PM, Jon Elson wrote: > rickman wrote: > >> On 4/8/2016 12:14 AM, Jon Elson wrote: >>> >>> So, Xilinx is working for me. And, yes, after going to the trouble of >>> getting comfortable in the Xilinx tools, the last thing I want to do is >>> learn somebody else's tools' quirks. >> >> What tool quirks. > > I didn't really mean quirks as in things that didn't work, or work right. I > just meant that each tool chain has a lot of features to learn, where the > optional settings are hidden, how to quickly configure the simulator, how to > set up to generate configuration PROM images, etc. There is a lot to learn > before you get fully productive. Yeah, I guess so. Is Xilinx still using their own simulator? I seem to recall it compiled to machine code so the compile was slow, but the simulation itself was fast. Still true? -- RickArticle: 158786
On Friday, April 8, 2016 at 3:05:09 PM UTC-4, Jon Elson wrote: > rickman wrote: > > > I don't recall how many I/O you > > need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin > > QFPs around. Even if you go with an older FPGA like a Spartan 3A the > > wider pitch package is worth it. If you have to use a BGA, pick one > > with a wide ball spacing like 1.0 mm. > > > I have learned how to solder QFPs down to 0.4mm pitch, but it takes a TINY > soldering tip, a stereo zoom microscope and a STEADY hand! 0.65 mm pitch is > pretty easy, at least for me. I was under the impression I'd use some kind of solder paste over a solder mask the PCB maker sends, place the parts, and then simply bake in some kind of high-heat oven. Best regards, Rick C. HodginArticle: 158787
On 4/8/2016 3:09 PM, Rick C. Hodgin wrote: > On Friday, April 8, 2016 at 3:05:09 PM UTC-4, Jon Elson wrote: >> rickman wrote: >> >>> I don't recall how many I/O you >>> need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin >>> QFPs around. Even if you go with an older FPGA like a Spartan 3A the >>> wider pitch package is worth it. If you have to use a BGA, pick one >>> with a wide ball spacing like 1.0 mm. >>> >> I have learned how to solder QFPs down to 0.4mm pitch, but it takes a TINY >> soldering tip, a stereo zoom microscope and a STEADY hand! 0.65 mm pitch is >> pretty easy, at least for me. > > I was under the impression I'd use some kind of solder paste over a solder > mask the PCB maker sends, place the parts, and then simply bake in some kind > of high-heat oven. You can do that. But if you are using QFPs, a soldering iron works pretty well I am told. The solder stencil is not so easy to use but works ok. If you have BGAs or land grid array parts you have to use the solder stencil. -- RickArticle: 158788
rickman wrote: > On 4/8/2016 2:49 PM, Jon Elson wrote: >> rickman wrote: >> >>> On 4/8/2016 12:14 AM, Jon Elson wrote: >>>> >>>> So, Xilinx is working for me. And, yes, after going to the trouble of >>>> getting comfortable in the Xilinx tools, the last thing I want to do is >>>> learn somebody else's tools' quirks. >>> >>> What tool quirks. >> >> I didn't really mean quirks as in things that didn't work, or work right. >> I just meant that each tool chain has a lot of features to learn, where >> the optional settings are hidden, how to quickly configure the simulator, >> how to >> set up to generate configuration PROM images, etc. There is a lot to >> learn before you get fully productive. > > Yeah, I guess so. Is Xilinx still using their own simulator? I seem to > recall it compiled to machine code so the compile was slow, but the > simulation itself was fast. Still true? > Yes. For the designs I do, the compile only takes a few seconds, and the sim runs pretty fast, although not blazingly. Sometimes I need to run 10's of ms of simulated time to get out to the interesting part, and it takes a minute or so. I can't imagine how some of the people simulating gigantic systems manage. But, the GUI aspects of Xilinx' sim is SO much better than that ghastly Modelsim product which I never really got competent at running. JonArticle: 158789
Rick C. Hodgin wrote: > On Friday, April 8, 2016 at 3:05:09 PM UTC-4, Jon Elson wrote: >> rickman wrote: >> >> > I don't recall how many I/O you >> > need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin >> > QFPs around. Even if you go with an older FPGA like a Spartan 3A the >> > wider pitch package is worth it. If you have to use a BGA, pick one >> > with a wide ball spacing like 1.0 mm. >> > >> I have learned how to solder QFPs down to 0.4mm pitch, but it takes a >> TINY >> soldering tip, a stereo zoom microscope and a STEADY hand! 0.65 mm pitch >> is pretty easy, at least for me. > > I was under the impression I'd use some kind of solder paste over a solder > mask the PCB maker sends, place the parts, and then simply bake in some > kind of high-heat oven. I don't do this for one-offs or prototypes. There is a big trick to the stencils. You need to reduce the area of the stencil apertures, or the excessive solder paste clumps together and bridges between the leads. As the lead pitch gets finer, this gets more and more critical. Another trick is to place solder blobs on two diagonal pads, and tack the chip down. You can view the alignment on all 4 sides and "walk" the chip by melting the solder on one of the tacked-down pins at a time until alignment is good. Then, apply liquid flux down all the rows of pins, and drag a soldering iron down the rows. The solder plate on the board is usually enough to solder the pins. JonArticle: 158790
On 4/8/2016 6:11 PM, Jon Elson wrote: > rickman wrote: > >> On 4/8/2016 2:49 PM, Jon Elson wrote: >>> rickman wrote: >>> >>>> On 4/8/2016 12:14 AM, Jon Elson wrote: >>>>> >>>>> So, Xilinx is working for me. And, yes, after going to the trouble of >>>>> getting comfortable in the Xilinx tools, the last thing I want to do is >>>>> learn somebody else's tools' quirks. >>>> >>>> What tool quirks. >>> >>> I didn't really mean quirks as in things that didn't work, or work right. >>> I just meant that each tool chain has a lot of features to learn, where >>> the optional settings are hidden, how to quickly configure the simulator, >>> how to >>> set up to generate configuration PROM images, etc. There is a lot to >>> learn before you get fully productive. >> >> Yeah, I guess so. Is Xilinx still using their own simulator? I seem to >> recall it compiled to machine code so the compile was slow, but the >> simulation itself was fast. Still true? >> > Yes. For the designs I do, the compile only takes a few seconds, and the > sim runs pretty fast, although not blazingly. Sometimes I need to run 10's > of ms of simulated time to get out to the interesting part, and it takes a > minute or so. I can't imagine how some of the people simulating gigantic > systems manage. > > But, the GUI aspects of Xilinx' sim is SO much better than that ghastly > Modelsim product which I never really got competent at running. Can you be more specific? I got used to Modelsim and then paid for a package from Lattice when I got some work using their part. Between the time I ordered the package with Modelsim and the time it was shipped to me, they switched to using the Aldec product. I raised hell with them over the phone and email, but they insisted there was nothing they could do. So I got over it and found the Aldec simulator didn't crash periodically like the Modelsim product did. Otherwise it used a compatible scripting interpreter and overall worked very similarly. It has been a while since I've done much with it, but I don't recall anything that is too awkward. What is so bad that you find Modelsim to be "ghastly"? -- RickArticle: 158791
On 4/8/2016 6:17 PM, Jon Elson wrote: > Rick C. Hodgin wrote: > >> On Friday, April 8, 2016 at 3:05:09 PM UTC-4, Jon Elson wrote: >>> rickman wrote: >>> >>>> I don't recall how many I/O you >>>> need, but there are 144 pin QFPs (~110 I/Os) and I think some 208 pin >>>> QFPs around. Even if you go with an older FPGA like a Spartan 3A the >>>> wider pitch package is worth it. If you have to use a BGA, pick one >>>> with a wide ball spacing like 1.0 mm. >>>> >>> I have learned how to solder QFPs down to 0.4mm pitch, but it takes a >>> TINY >>> soldering tip, a stereo zoom microscope and a STEADY hand! 0.65 mm pitch >>> is pretty easy, at least for me. >> >> I was under the impression I'd use some kind of solder paste over a solder >> mask the PCB maker sends, place the parts, and then simply bake in some >> kind of high-heat oven. > I don't do this for one-offs or prototypes. There is a big trick to the > stencils. You need to reduce the area of the stencil apertures, or the > excessive solder paste clumps together and bridges between the leads. As > the lead pitch gets finer, this gets more and more critical. > > Another trick is to place solder blobs on two diagonal pads, and tack the > chip down. You can view the alignment on all 4 sides and "walk" the chip by > melting the solder on one of the tacked-down pins at a time until alignment > is good. Then, apply liquid flux down all the rows of pins, and drag a > soldering iron down the rows. The solder plate on the board is usually > enough to solder the pins. I have yet to deal with hand soldering of anything this fine, but I'm told you can put a blob of solder on the iron tip to do the swipe you are referring to. *Very* little solder is needed to make a good connection. Many follow up the solder swipe by a solder braid and iron to remove the excess which may not be easy to see between or behind the pins. Someone who was hand soldering one of my boards told me he had a fit trying to remove a short once because it was so fine he couldn't see it even *with* a magnifier. Eventually he just passed a sharp point between all the leads on the connector and the short was gone. I guess it was virtually like a tin whisker (but before RoHS). -- RickArticle: 158792
On 4/5/2016 3:23 PM, Rick C. Hodgin wrote: > On Tuesday, April 5, 2016 at 3:03:53 PM UTC-4, Rick C. Hodgin wrote: >> On Tuesday, April 5, 2016 at 2:53:15 PM UTC-4, Rob Gaddi wrote: >>> Rick C. Hodgin wrote: >>>> Hello all. I'm looking for some information about Altera's FPGA. I have >>>> this Cyclone V GX dev board: >>>> >>>> https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html >>>> >>>> It has a 160-pin HSMC connector, which connects using this flexible cable: >>>> >>>> https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf >>>> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=275 >>>> >>>> I'm wondering if this connector can be used for general purpose off-board >>>> communication for custom uses outside of connecting to other Mezzanine >>>> boards? Could I, for example, connect some wires to the pins and signal >>>> them independently for GPIO? >>>> >>>> Or... is this cable interface something proprietary that only allows >>>> interconnect between Mezzanine devices? >>> >>> It's a bit of a pain as connectors go. >>> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=67&No=322&PartNo=1 makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). >>> >>> -- >>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com >> >> Thank you, Rob. That's exactly what I was looking for. > > Ordered. Thank you again. I think you are better off not using the FPGA eval board and just making your own board with the 386 and the FPGA. The adapters and cables are going to add a lot of capacitance and noise to your signals. Why mess with the added complexity? -- RickArticle: 158793
On Thu, 07 Apr 2016 05:28:39 -0700, Rick C. Hodgin wrote: > After hearing all of the difficulties I may have on the motherboard > side, the re-grouping of just working with the Am386 CPU makes a lot > more sense. Plus, it actually accomplishes nearly all of my goals as my > goals were to replace the CPU's instruction set with my own, and to > validate it 1:1 that I am correct. By having a side-by-side comparison > I can do that. And as I've stated, it might even be interesting to try > to get other 80386-clone CPUs to test out side-by-side in the > configuration, and then write a paper outlining where they are > different. But, that's the lowest possible goal, just a "wouldn't it be > interesting" thought. :-) Yesterday I remembered an additional thing that can go wrong, and almost certainly will go wrong. The system you are hacking (the motherboard) almost certainly uses DRAM as its main memory. DRAM needs to be refreshed every so often. This is done by the memory controller toggling a particular command to the chip when it wants the chip to refresh the memory. The question is how does the memory controller know when to order a refresh. Almost 100% certainly, it has a counter that responds to the clock signal driven by or derived from the main system clock. The system clock you underclock. So if you slow the clock enough, you are certain to violate the refresh timing of the DRAM and ruin its contents. And you can't have a computer without a functional main memory. :)Article: 158794
On Wed, 06 Apr 2016 13:38:19 -0700, Rick C. Hodgin wrote: > My ultimate goal is to build a completely homemade CPU using my own > garage fab on 3 to 10 micron processes! I'm in. :) Although, for the time being, I'm fine with using FPGAs. I've been thinking about building a completely open-source computer, down to the atoms, but it's really a group project. There's literally no point in building a computer that will not be used outside of a single family or "close knit community". A bunch of villages and a city would be the smallest user base I would target. Yet, so far, I seem to be the only person I ever met off the Internet to have such interests. >> I have to ask: why spend time hacking x86 when there are so many other, >> BETTER architectures out there? :) > > I have a long history on 80386. I wrote my own kernel, debuggers, etc. > It's been a relationship dating back to the late 80s. Oh, ok. > However, one of the reasons I'm doing this is because I am extending the > ISA out to include 40-bit addresses, rather than just 32-bit, > which accesses memory in the Terabyte range, and to include a built-in > ARM ISA which allows the CPU to switch between ISAs based on branch > instructions. Ouch, ouch, ouch, too much - unless you're good at it. :) I designed and implemented a 16-bit soft CPU from scratch, and I can tell you it's seriously difficult to make it work. Right now, I'm hacking a 32- bit CPU (aeMB, to be very specific) and interfacing it to a SoC I plan to publish eventually and again, it's seriously difficult to make it work. If you add a bit to the word or address size, you are not just doubling the CPUs capabilities, you are also doubling the number, size and scope of problems you have to deal with. Now, if you already did work on this, or have a working Verilog/VHDL model, it's probably OK - taking into account your time horizon. But if you are at the stage of an idea, I would suggest making up your mind between x86 and ARM and just focusing on one untill you make it work. >> Also, why are you doing this? Is this a hobby? Work related? Starting a >> new bussiness? Want to design and implement a NSA-proof PC? > > To be honest, I am a Christian, and I want to use the talents I was > gifted with and give the fruit of my labor back to God, and to my fellow > man (and not a pursuit of money, or proprietary IP, or patents, or other > such things, but rather an expression of love basically in giving back). Oh. OK. :) Works for me. Did you publish any of your work? >> Does simulation count? :D > > Yes. Also in emulation, as by a real FPGA product, but one which does > not plug into a socket, but is its own entire creation. Here's an > Aleksander who created a 486 SX CPU (it has not integrated FPU): > > https://github.com/alfikpl/ao486 Verily, I shall review this. I'm starting to get the impression that all the stuff I'm making on my own has already been solved, but hasn't been advertised. I'm working on my dream computer, but these solved systems constantly keep popping up. Maybe all of it has already been solved? At any rate, this implementation is an absolute MONSTER, clocking in at 36k gates (and providing a passe 30 MHz of x86). Just how the fuck am I supposed to fit that in a sane chip? You know, the ones for which you can get synthesizers for free, instead of paying several thousand dollars for them. But the HDD or VGA *might* be salvageable, depending on the implementation.Article: 158795
On 4/9/2016 5:15 AM, Aleksandar Kuktin wrote: > On Thu, 07 Apr 2016 05:28:39 -0700, Rick C. Hodgin wrote: > >> After hearing all of the difficulties I may have on the motherboard >> side, the re-grouping of just working with the Am386 CPU makes a lot >> more sense. Plus, it actually accomplishes nearly all of my goals as my >> goals were to replace the CPU's instruction set with my own, and to >> validate it 1:1 that I am correct. By having a side-by-side comparison >> I can do that. And as I've stated, it might even be interesting to try >> to get other 80386-clone CPUs to test out side-by-side in the >> configuration, and then write a paper outlining where they are >> different. But, that's the lowest possible goal, just a "wouldn't it be >> interesting" thought. :-) > > Yesterday I remembered an additional thing that can go wrong, and almost > certainly will go wrong. > > The system you are hacking (the motherboard) almost certainly uses DRAM > as its main memory. DRAM needs to be refreshed every so often. This is > done by the memory controller toggling a particular command to the chip > when it wants the chip to refresh the memory. The question is how does > the memory controller know when to order a refresh. Almost 100% > certainly, it has a counter that responds to the clock signal driven by > or derived from the main system clock. The system clock you underclock. > > So if you slow the clock enough, you are certain to violate the refresh > timing of the DRAM and ruin its contents. > > And you can't have a computer without a functional main memory. :) There is a 14.31 MHz clock on the main board that is used to time various activity including the refresh. I believe this was divided by 3 to get the original CPU clock rate (8088) and further divided to get the clock to the 8253 timer chip which controlled the refresh as well as the speaker logic and generated the time of day clock. The clock rate to the CPU changed as PCs ran faster, but the clock to the timer chip remained. The 14.31 MHz clock was used on the backplane connectors to be used by the video cards when needed. Refresh needs to be done on DRAM, but if you aren't using DRAM, then you don't need refresh. -- RickArticle: 158796
On 4/9/2016 6:00 AM, Aleksandar Kuktin wrote: > On Wed, 06 Apr 2016 13:38:19 -0700, Rick C. Hodgin wrote: > >> My ultimate goal is to build a completely homemade CPU using my own >> garage fab on 3 to 10 micron processes! > > I'm in. :) > > Although, for the time being, I'm fine with using FPGAs. > > I've been thinking about building a completely open-source computer, down > to the atoms, but it's really a group project. There's literally no point > in building a computer that will not be used outside of a single family > or "close knit community". A bunch of villages and a city would be the > smallest user base I would target. > > Yet, so far, I seem to be the only person I ever met off the Internet to > have such interests. I expect trying to get anything remotely like a critical mass is virtually impossible. There is an open source chip similar in size and capability to the ARM processors called RISC-V that is getting wide attention and will produce a chip soon. >>> I have to ask: why spend time hacking x86 when there are so many other, >>> BETTER architectures out there? :) >> >> I have a long history on 80386. I wrote my own kernel, debuggers, etc. >> It's been a relationship dating back to the late 80s. > > Oh, ok. > >> However, one of the reasons I'm doing this is because I am extending the >> ISA out to include 40-bit addresses, rather than just 32-bit, >> which accesses memory in the Terabyte range, and to include a built-in >> ARM ISA which allows the CPU to switch between ISAs based on branch >> instructions. > > Ouch, ouch, ouch, too much - unless you're good at it. :) It will never be possible to include an ARM ISA unless a license fee is paid. I recall some years back a student produced an HDL version of an ARM 7TDMI. ARM spoke to him and the core was withdrawn. He also got a job with them. Win/win > I designed and implemented a 16-bit soft CPU from scratch, and I can tell > you it's seriously difficult to make it work. Right now, I'm hacking a 32- > bit CPU (aeMB, to be very specific) and interfacing it to a SoC I plan to > publish eventually and again, it's seriously difficult to make it work. I'm surprised that you say it is hard to make it work. Do you mean it is hard to build all the infrastructure? I have designed my own CPUs before and found that part easy. It is creating the software support that is hard, or at least a lot of work. I use Forth which helps make things easier. > If you add a bit to the word or address size, you are not just doubling > the CPUs capabilities, you are also doubling the number, size and scope > of problems you have to deal with. ??? My CPU design did not specify the data size, only the instruction size. I didn't have a problem adjusting the data size to suit my application. > Now, if you already did work on this, or have a working Verilog/VHDL > model, it's probably OK - taking into account your time horizon. But if > you are at the stage of an idea, I would suggest making up your mind > between x86 and ARM and just focusing on one untill you make it work. > >>> Also, why are you doing this? Is this a hobby? Work related? Starting a >>> new bussiness? Want to design and implement a NSA-proof PC? >> >> To be honest, I am a Christian, and I want to use the talents I was >> gifted with and give the fruit of my labor back to God, and to my fellow >> man (and not a pursuit of money, or proprietary IP, or patents, or other >> such things, but rather an expression of love basically in giving back). > > Oh. OK. :) Works for me. > > Did you publish any of your work? > >>> Does simulation count? :D >> >> Yes. Also in emulation, as by a real FPGA product, but one which does >> not plug into a socket, but is its own entire creation. Here's an >> Aleksander who created a 486 SX CPU (it has not integrated FPU): >> >> https://github.com/alfikpl/ao486 > > Verily, I shall review this. I'm starting to get the impression that all > the stuff I'm making on my own has already been solved, but hasn't been > advertised. I'm working on my dream computer, but these solved systems > constantly keep popping up. Maybe all of it has already been solved? Exactly what is your dream computer? > At any rate, this implementation is an absolute MONSTER, clocking in at > 36k gates (and providing a passe 30 MHz of x86). Just how the fuck am I > supposed to fit that in a sane chip? You know, the ones for which you can > get synthesizers for free, instead of paying several thousand dollars for > them. > > But the HDD or VGA *might* be salvageable, depending on the > implementation. > -- RickArticle: 158797
rickman <gnuarm@gmail.com> wrote:
>
> What part of the CPU chip on the rPi is not documented in the manual?
> It is large and I have not read it all of course, but I'm sure I would
> have heard in these discussions if there were any other part than the
> GPU that was driven by closed source code.
Have you lookead at the manual at all? I have BCM2835-ARM-Peripherals.pdf
which seem to be the only official documentation and it has 205
pages. This is tiny compared to other chips. For example main
i.MX6 manual from FreeScale has 5739 pages and there are additional
smaller manuals for i.MX6.
USB part in BCM manual tells you that they use Synopsys IP,
what configuration options they use with Synopsis core and
list registers that Broadcom added. In a sense Broadcom
released all _their_ information, but you need to get
Synopsys information from other source.
--
Waldek Hebisch
Article: 158798On 4/9/2016 6:48 PM, Waldek Hebisch wrote: > rickman <gnuarm@gmail.com> wrote: >> >> What part of the CPU chip on the rPi is not documented in the manual? >> It is large and I have not read it all of course, but I'm sure I would >> have heard in these discussions if there were any other part than the >> GPU that was driven by closed source code. > > Have you lookead at the manual at all? I have BCM2835-ARM-Peripherals.pdf > which seem to be the only official documentation and it has 205 > pages. This is tiny compared to other chips. For example main > i.MX6 manual from FreeScale has 5739 pages and there are additional > smaller manuals for i.MX6. > > USB part in BCM manual tells you that they use Synopsys IP, > what configuration options they use with Synopsis core and > list registers that Broadcom added. In a sense Broadcom > released all _their_ information, but you need to get > Synopsys information from other source. Yes, I looked at the manual. I think I already said I didn't read the entire manual, so why do you even ask? I was only looking for info on the part I was using. I don't read 205 page manuals for fun. Seems weird that there is open source driver code for the various parts of the chip that has no released documentation. I guess you can figure out some aspects of how the chip is being used by looking at the driver code, but anything not being used would still be unknown. -- RickArticle: 158799
Jon Elson <jmelson@wustl.edu> wrote: > Complex designs like this require GOOD schematic and PCB layout tools. I > use an old one, Protel 99SE, but that is no longer available, and was pretty > expensive when it was. I have used Kicad a little, it shows REAL promise, > but is not yet as good as Protel. Just to note that there's a free descendent of Protel which is called CircuitMaker: http://circuitmaker.com/ I haven't used it, but I use its commercial sister Altium which is pretty nice. The difference with CircuitMaker is your boards have to be public, there is no way to keep them private. So it's no good for commercial work, but that limitation is not a problem for an open source project. (It's also not open source, but my experience is the proprietary tools are generally several steps above the open source tools - depending on board complexity, going with proprietary tools can be a necessary evil to get work done. It also relies on an internet connection) Theo
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