Messages from 160250

Article: 160250
Subject: Re: Article about using Non-Project Mode
From: Ilya Kalistru <stebanoid@gmail.com>
Date: Wed, 23 Aug 2017 08:07:55 -0700 (PDT)
Links: << >> << T >> << A >>

On Saturday, July 1, 2017 at 12:15:38 AM UTC+3, Kevin Neilson wrote:
> > I'll publish the article as soon as it is reviewed by my employer.
> >=20
> > Kevin, if you have an Google account you can request access to the draf=
t and I'll grant it to you.
>=20
> Ilya,
> Thanks for the document.  You inspired me to use non-project mode and now=
 that I have a script for one of my projects I can just keep reusing it.  T=
he only thing I'd say about your document is that I think it had some Windo=
ws-specific stuff which wasn't obvious to me at first.
>=20
> There is also a brief intro to non-project mode in the Vivado Quick Refer=
ence:
>=20
> http://tinyurl.com/yb9d8y8d

It's finally published on edn.com ! http://tinyurl.com/y9ekp7lf
Thanks a lot to anyone who have helped me to improve the article.

Kevin, I'm so glad that I inspired you!
In fact, it was a goal of the article to encourage more people to use this =
mode, so that IDE developers pay more attention to this way of managing pro=
jects.

I hope that some inconvenience of using IPs in this mode will not discourag=
e you. :)
I am planning to write another article devoted to this problem. I hope I wi=
ll find time for doing some research on this matter and for writing article=
.

Article: 160251
Subject: Re: Test Driven Design?
From: Ilya Kalistru <stebanoid@gmail.com>
Date: Wed, 23 Aug 2017 08:10:47 -0700 (PDT)
Links: << >> << T >> << A >>

On Saturday, June 3, 2017 at 1:54:05 AM UTC+3, Ilya Kalistru wrote:
> It's a draft of an article. 
> https://docs.google.com/document/d/17LgQjxYdh8Dxy4NdFWWNYQ7up8MFNG4GQdPfv3s5LzI/edit?usp=sharing
> It would be great if you left you comments right in the document or here, so that I could improve it.
> 
> Thanks.

It's finally published on edn.com !   http://tinyurl.com/y9ekp7lf

Article: 160252
Subject: Re: Article about using Non-Project Mode
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 27 Aug 2017 11:57:38 +0100 (BST)
Links: << >> << T >> << A >>

Ilya Kalistru <stebanoid@gmail.com> wrote:
> It's finally published on edn.com ! http://tinyurl.com/y9ekp7lf
> Thanks a lot to anyone who have helped me to improve the article.

Nice :)

> I hope that some inconvenience of using IPs in this mode will not
> discourage you.  :)
> I am planning to write another article devoted to this problem. I hope I
> will find time for doing some research on this matter and for writing
> article.

I should probably have a play some time and try and do similar for Altera
tools.  It's fairly simple - the project settings output by Quartus are
'just tcl', so in theory it should be drivable from a tcl script.
At the moment we build from a Makefile but we still have a nominal project
with the tcl settings.

I was pleasantly surprised to discover that there's a variety of recipes for
putting Quartus inside Docker images, so it looks like there's quite a bit
of interest in scripted builds.

(My interest here is running the Altera JTAG stack inside Docker, so it's
easier to plug [lots of] FPGAs into the test environment without them
conflicting.  We already do this, but Docker will help cleaning up better)

Theo

Article: 160253
Subject: Re: Article about using Non-Project Mode
From: Ilya Kalistru <stebanoid@gmail.com>
Date: Sun, 27 Aug 2017 09:37:25 -0700 (PDT)
Links: << >> << T >> << A >>


> I should probably have a play some time and try and do similar for Altera
> tools.  ...
> ...
> Theo

Don't forget to mention my article in yours one :)

Article: 160254
Subject: Re: Microsemi FPGAs
From: JM <dontreplytothis173@gmail.com>
Date: Tue, 29 Aug 2017 22:39:25 +0100
Links: << >> << T >> << A >>

On 17/08/2017 05:20, John Larkin wrote:
> Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM
> Cortex M3 on chip?
>
> How good/awful is the tool set? Any big likes or dislikes?
>

They use Modelsim for the simulator and Synplify for synthesis.  That's 
as good as it gets.  Rest of the tools seem to be fine.  I did a design 
with one of these parts last year - didn't come across anything 
particularly troublesome.

I didn't use the high level (Matlab/Simulink) based design tools so 
don't know how they compare to the Altera/Xilinx equivalents - I 
wouldn't expect them to be as capable as the latter.

> They look like a pretty good deal for a medium FPGA with ARM.
>
>

They are.  Lattice also offer good value on small/medium FPGA's (not 
SOC's) - I tend to use Lattice in preference to Altera/Xilinx.

Article: 160255
Subject: registers delay
From: promach <feiphung27@gmail.com>
Date: Wed, 30 Aug 2017 09:20:37 -0700 (PDT)
Links: << >> << T >> << A >>

for the case of registers dependencies, d <= c <= b <= a , how do we assert d whenever a is asserted without cheating the delay ?

Article: 160256
Subject: Re: registers delay
From: sbattazzo@gmail.com
Date: Wed, 30 Aug 2017 12:36:35 -0700 (PDT)
Links: << >> << T >> << A >>

This is kind of vague and depends what you want to do with it and why, but you can always do something like:
d <= c | a;

If "a" is only asserted for one clock cycle, then you would get two pulses on "d." Are you trying to do that, or are you trying to extend "a" to a longer pulse?


On Wednesday, August 30, 2017 at 9:20:46 AM UTC-7, promach wrote:
> for the case of registers dependencies, d <= c <= b <= a , how do we assert d whenever a is asserted without cheating the delay ?

Article: 160257
Subject: logic scope coding
From: promach <feiphung27@gmail.com>
Date: Sat, 16 Sep 2017 02:13:08 -0700 (PDT)
Links: << >> << T >> << A >>

Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ? 

Is my coding approach too software-centric ?

Article: 160258
Subject: Re: logic scope coding
From: gtwrek@sonic.net (Mark Curry)
Date: Mon, 18 Sep 2017 17:28:13 -0000 (UTC)
Links: << >> << T >> << A >>

In article <c4efe3cd-b8c4-4fc7-846d-20871e1edd27@googlegroups.com>,
promach  <feiphung27@gmail.com> wrote:
>Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ? 
>
>Is my coding approach too software-centric ?

From just a quick look, my only recommendation would be to avoid the `defines
within the RTL code, and use parameters instead.  You've got some parameters
in the code, but `defines elsewhere.  I'd recommend standardizing on parameters.

`defines are global in scope, and not recommended for the way you're using them.
Imagine a design requiring two of your logic_analyzer - each with its own
configuration.  

Regards,

Mark

Article: 160259
Subject: duty cycle of clock divider
From: promach <feiphung27@gmail.com>
Date: Thu, 21 Sep 2017 05:32:42 -0700 (PDT)
Links: << >> << T >> << A >>

http://www.fpga4fun.com/MusicBox1.html

The frequency is 440Hz, as expected, but the output duty cycle is not 50% a=
nymore. The low level goes from counter=3D0 to counter=3D32767 (when bit 15=
 of counter is low) and then high level from 32768 to 56817. That gives us =
"speaker" being high only 42% of the time. The easiest way to get a 50% dut=
y cycle is to add a stage that divides the output by 2. So first we divide =
by 28409 (instead of 56818) and then by 2.  ????=20

I do not understand why we need to divide by 2.
Could anyone explain the above reasoning in more laymen way ?

Article: 160260
Subject: Re: duty cycle of clock divider
From: Andy Bennet <andyb@andy.com>
Date: Thu, 21 Sep 2017 13:50:27 +0100
Links: << >> << T >> << A >>

On 21/09/2017 13:32, promach wrote:
> http://www.fpga4fun.com/MusicBox1.html
>
> The frequency is 440Hz, as expected, but the output duty cycle is not 50% anymore. The low level goes from counter=0 to counter=32767 (when bit 15 of counter is low) and then high level from 32768 to 56817. That gives us "speaker" being high only 42% of the time. The easiest way to get a 50% duty cycle is to add a stage that divides the output by 2. So first we divide by 28409 (instead of 56818) and then by 2.  ????
>
> I do not understand why we need to divide by 2.
> Could anyone explain the above reasoning in more laymen way ?
>

He means divide the frequency by 2, implemented by a single stage 
counter flip flop. This will then always give a 50% duty cycle.

Article: 160261
Subject: Re: duty cycle of clock divider
From: promach <feiphung27@gmail.com>
Date: Thu, 21 Sep 2017 07:29:49 -0700 (PDT)
Links: << >> << T >> << A >>

I do not get how just dividing by 2 could get 50% duty cycle instead of 42% ?

Article: 160262
Subject: Re: duty cycle of clock divider
From: Andy Bennet <andyb@andy.com>
Date: Thu, 21 Sep 2017 15:55:16 +0100
Links: << >> << T >> << A >>

On 21/09/2017 15:29, promach wrote:
> I do not get how just dividing by 2 could get 50% duty cycle instead of 42% ?
>
Assuming the input frequency to the divider is constant, then:-
that frequency is defined by the reciprocal of the time period that 
elapses between successive rising or falling or some fixed point in the 
repetitive waveform ...
True or false ...

If true then if you clock a flip flop at the fixed point in the repetive 
waveform then the outout will toggle high for one complete period of the 
input waveform, and toggle low for one complete period of the input 
waveform.
If the frequency is constant, then the period of successive cycle of the 
input waveform will be the same.
Therefore the output of the flip flop divider will have a 50% duty cycle.

If false then it is not a constant input frequency and all the above 
does not apply.

Andy

Article: 160263
Subject: Re: duty cycle of clock divider
From: promach <feiphung27@gmail.com>
Date: Thu, 21 Sep 2017 09:49:33 -0700 (PDT)
Links: << >> << T >> << A >>

Strange, I have the clock divider coding at http://www.edaplayground.com/x/gXC

but it does not divide accordingly as mentioned in the article.

Any idea about what I missed out ?



// Adapted from http://www.fpga4fun.com/MusicBox1.html

module clk_div (i_clk, ck_stb);
  
  input i_clk;
  output reg ck_stb = 0;
  
  localparam THRESHOLD = 3;  // divides i_clk by (2*THRESHOLD = 6) to obtain ck_stb which is the divided clock signal
  
  reg [($clog2(THRESHOLD)-1):0] counter = 0;
  reg counter_reset = 0;
  
  always @(posedge i_clk)
    counter_reset <= (counter == THRESHOLD-1'b1);
  
  always @(posedge i_clk)
  begin
    if(counter_reset)
      counter <= 1;    
    else
      counter <= counter + 1;
    
    //$display("$clog2(THRESHOLD) = ", $clog2(THRESHOLD));
  end
  
  always @(posedge i_clk)
    ck_stb <= ~ck_stb;
  
endmodule

Article: 160264
Subject: Re: duty cycle of clock divider
From: promach <feiphung27@gmail.com>
Date: Thu, 21 Sep 2017 09:52:33 -0700 (PDT)
Links: << >> << T >> << A >>

I have tried clock divider at http://www.edaplayground.com/x/gXC , but it does not divide accordingly as mentioned in the article.

Any idea about what I missed out ?

// Adapted from http://www.fpga4fun.com/MusicBox1.html

module clk_div (i_clk, ck_stb);
  
  input i_clk;
  output reg ck_stb = 0;
  
  localparam THRESHOLD = 3;  // divides i_clk by (2*THRESHOLD = 6) to obtain ck_stb which is the divided clock signal
  
  reg [($clog2(THRESHOLD)-1):0] counter = 0;
  reg counter_reset = 0;
  
  always @(posedge i_clk)
    counter_reset <= (counter == THRESHOLD-1'b1);
  
  always @(posedge i_clk)
  begin
    if(counter_reset)
      counter <= 1;    
    else
      counter <= counter + 1;
    
    //$display("$clog2(THRESHOLD) = ", $clog2(THRESHOLD));
  end
  
  always @(posedge i_clk)
    ck_stb <= ~ck_stb;
  
endmodule

Article: 160265
Subject: Re: duty cycle of clock divider
From: promach <feiphung27@gmail.com>
Date: Thu, 21 Sep 2017 10:24:04 -0700 (PDT)
Links: << >> << T >> << A >>

I have found out the bug.

The last always block should look like the following:


  always @(posedge i_clk)
    if(counter_reset)
      ck_stb <= ~ck_stb;

Article: 160266
Subject: Re: duty cycle of clock divider
From: promach <feiphung27@gmail.com>
Date: Fri, 22 Sep 2017 04:04:35 -0700 (PDT)
Links: << >> << T >> << A >>

@Andy

For ambulance siren at http://www.fpga4fun.com/MusicBox2.html and http://www.edaplayground.com/x/5aSK , could you comment on the simulation waveform   https://i.imgur.com/gN0cqAJ.png   ?

Note: I will do the actual hardware (speaker) audio testing tomorrow.



// http://www.fpga4fun.com/MusicBox2.html  - Ambulance siren

module clk_div (i_clk, ck_stb);
  
  input i_clk;
  output reg ck_stb = 0;
  
  localparam THRESHOLD = 6;  // divides i_clk by 6 to obtain ck_stb which is the divided clock signal
  localparam TOGGLE_FREQUENCY_RATIO = 4;  // MSB bit of "tone" toggles with a frequency of about [i_clk / 2^4]
  
  reg [($clog2(THRESHOLD) - 1):0] counter = 0;
  reg counter_reset = 0;
  
  reg [(TOGGLE_FREQUENCY_RATIO - 1):0] tone = 0;
  
  always @(posedge i_clk) 
    tone <= tone+1;
  
  always @(posedge i_clk)
    if(tone[TOGGLE_FREQUENCY_RATIO-1])
      counter_reset <= (counter == THRESHOLD - 1'b1);
    else
      counter_reset <= (counter == (THRESHOLD >> 1) - 1'b1);
  
  always @(posedge i_clk)
  begin
    if(counter_reset)
      counter <= 1;    
    else
      counter <= counter + 1;
    
    //$display("$clog2(THRESHOLD) = ", $clog2(THRESHOLD));
  end
  
  always @(posedge i_clk)
    if(counter_reset)
      ck_stb <= ~ck_stb;
  
endmodule

Article: 160267
Subject: Re: duty cycle of clock divider
From: Andy Bennet <andyb@andy.com>
Date: Fri, 22 Sep 2017 13:04:51 +0100
Links: << >> << T >> << A >>

On 21/09/2017 17:52, promach wrote:
> I have tried clock divider at http://www.edaplayground.com/x/gXC , but it does not divide accordingly as mentioned in the article.
>
> Any idea about what I missed out ?
>
> // Adapted from http://www.fpga4fun.com/MusicBox1.html
>
> module clk_div (i_clk, ck_stb);
>
>   input i_clk;
>   output reg ck_stb = 0;
>
>   localparam THRESHOLD = 3;  // divides i_clk by (2*THRESHOLD = 6) to obtain ck_stb which is the divided clock signal
>
>   reg [($clog2(THRESHOLD)-1):0] counter = 0;
>   reg counter_reset = 0;
>
>   always @(posedge i_clk)
>     counter_reset <= (counter == THRESHOLD-1'b1);
>
>   always @(posedge i_clk)
>   begin
>     if(counter_reset)
>       counter <= 1;
>     else
>       counter <= counter + 1;
>
>     //$display("$clog2(THRESHOLD) = ", $clog2(THRESHOLD));
>   end
>
>   always @(posedge i_clk)
>     ck_stb <= ~ck_stb;
>
> endmodule
>

I'm guessing you have declared output register, which just defines the 
output state.
You should have just declared a register (reg?) which has both an input 
and output state.

Article: 160268
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: roman.eberle@arcor.de
Date: Sun, 1 Oct 2017 06:04:45 -0700 (PDT)
Links: << >> << T >> << A >>

Hi,

anyone having success with a FYDK-XILINX Platform Cable USB Model DLC9LP?
 
idVendor=0403, idProduct=6014

With your help I was able to get rid of "windrv6 module not loaded" error message, and it looks as if impact is using libusb-driver.so.

But I still get "cable not found" error.

thanks & regards

Article: 160269
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: Jon Elson <elson@pico-systems.com>
Date: Sun, 01 Oct 2017 13:50:43 -0500
Links: << >> << T >> << A >>

roman.eberle@arcor.de wrote:

> Hi,
> 
> anyone having success with a FYDK-XILINX Platform Cable USB Model DLC9LP?
>  
> idVendor=0403, idProduct=6014
> 
> With your help I was able to get rid of "windrv6 module not loaded" error
> message, and it looks as if impact is using libusb-driver.so.
> 
> But I still get "cable not found" error.
> 
> thanks & regards
I have a DLC9G, don't know how this is different from a DLC9LP.
It works, but I occasionally get into some kind of problem where it will not 
initialize.  I have to go through several menus to reset impact so it scans 
again for the device.  You do NOT need windrvr, that is for the old parallel 
port JTAG device.  

Jon

Article: 160270
Subject: Re: Help finding Xilinx software for HW-130 programmer
From: Rob M <f6ceedb9c75b52f7fcc0a55cf0cfbf5d_1084@example.com>
Date: Mon, 02 Oct 2017 21:37:02 -0500
Links: << >> << T >> << A >>

responding to
http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm
, Rob M wrote:
> TimRegeant  wrote:
>
> On 12/5/2016 10:37 PM, Joe Z wrote: 
> > responding to 
> >
>
http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm
> 
> > 
> > , Joe Z wrote: 
> >> gnuarm  wrote: 
> >> 
> >> On 5/3/2016 2:23 PM, Tim Regeant wrote: > I am searching for
> some 
> >> Xilinx programmer software for the HW-130 
> >> unit > from around 1996-2000. > > Looking the the DOS
> version.  The 
> >> filename was HW130.ZIP > > Also looking for the 16-bit
> windows version 
> >> HW130W.ZIP. > > Thank you for any help you can offer! 
> >> I have software from that era along with a license key.  I
> could get it 
> >> to you. 
> >> -- 
> >> Rick C 
> > 
> > Hi Rick, 
> > 
> > I'm in the same boat - I have an old XC17S that I need to read and 
> > re-create. I'm planning to grab an HW-130 on ebay, but the software
> for 
> > it is nowhere to 
> > be had... Can you email it to me too? 
> > 
> > -Joe Z 
> > 
> > 
> > 
> 
> 
> Send me an email with what you need.  I have the software. 
> 
Hi Rick and Joe

Have either of you got a working HW130 programmer and PC44 adaptor?  If so,
would you be able to program six XC7236s for me?

Best regards,

Rob

Article: 160271
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: rndhro <rndhro@invalid.com>
Date: Fri, 6 Oct 2017 09:27:48 +0200
Links: << >> << T >> << A >>

On 10/01/2017 03:04 PM, roman.eberle@arcor.de wrote:
> Hi,
> 
> anyone having success with a FYDK-XILINX Platform Cable USB Model DLC9LP?
>  
> idVendor=0403, idProduct=6014
> 
> With your help I was able to get rid of "windrv6 module not loaded" error message, and it looks as if impact is using libusb-driver.so.
> 
> But I still get "cable not found" error.
> 
> thanks & regards
> 

Hi,

are you sure the given product and vendor IDs are from your Xilinx
Programmer? All my programmers have VendorID 0x03fd and product IDs
between 0x0007 and 0x0015. Once fxload has loaded the cypress firmware
the programmer should have productID 0x0008 and the LED turns orange or
green.

Article: 160272
Subject: Re: Xilinx Platform cable USB and impact on linux without windrvr
From: Jan Coombs <jenfhaomndgfwutc@murmic.plus.com>
Date: Fri, 6 Oct 2017 21:41:34 +0100
Links: << >> << T >> << A >>

On Sun, 1 Oct 2017 06:04:45 -0700 (PDT)
roman.eberle@arcor.de wrote:

> Hi,
> 
> anyone having success with a FYDK-XILINX Platform Cable USB
> Model DLC9LP? 
> idVendor=0403, idProduct=6014

I bought four Chinese Platform Cables, and was surprised to
find I had two different types, two with Cypress 8051 + logic
chip, and two with FTDI (0403-6xxx) and level shifters. 

The guy using them got the FTDI ones working with Impact, but
not the Cypress ones which need a firmware file and an extra
package? to upload the 8051 firmware on connection under linux.  

I think that one of the apps is scripted Impact, so it may be
simple to recover the settings. Impact was installed from ISE
14.7. 

Jan Coombs

Article: 160273
Subject: Artix-7 boards
From: john <anon@example.com>
Date: Sat, 7 Oct 2017 13:16:06 +0100
Links: << >> << T >> << A >>

Has anyone had any experience of using these :

http://www.robotshop.com/uk/cmod-a7-35t-breadboardable-artix-7-fpga-module.ht
ml?gclid=EAIaIQobChMIkqXI9rje1gIVxZkbCh2l_AkhEAEYASAAEgLo_PD_BwE

They aren't in stock yet but maybe some have been shipped. 
I'm looking for comments on them for use with novice FPGA users.
Anything you have to say may be helpful as I'm looking to buy a few of them.

Also if anyone knows of a low cost spartan7 board that may hit the market
very soon I'd welcome the info.

thanks

-- 

john

=========================
http://johntech.co.uk
=========================

Article: 160274
Subject: Re: Artix-7 boards
From: Gabor <nospam@nospam.com>
Date: Sat, 7 Oct 2017 11:21:33 -0400
Links: << >> << T >> << A >>

On Saturday, 10/7/2017 8:16 AM, john wrote:
> Has anyone had any experience of using these :
> 
> http://www.robotshop.com/uk/cmod-a7-35t-breadboardable-artix-7-fpga-module.ht
> ml?gclid=EAIaIQobChMIkqXI9rje1gIVxZkbCh2l_AkhEAEYASAAEgLo_PD_BwE
> 
> They aren't in stock yet but maybe some have been shipped.
> I'm looking for comments on them for use with novice FPGA users.
> Anything you have to say may be helpful as I'm looking to buy a few of them.
> 
> Also if anyone knows of a low cost spartan7 board that may hit the market
> very soon I'd welcome the info.
> 
> thanks
> 

No experience with that board, however I have had experience
with the Artix-7 35T.  It's basically a 50T nobbled in software.
The way Xilinx does this leaves the entire 50T fabric available,
but limits the number of each fabric component you can use.  This
results in a device that can easily work with a 100% "full"
design, since it's the equivalent of a 70% full 50T.  Either
this device (smaller Artix-7 series) or Spartan-7 requires Vivado
software.  ISE does not support them.

 From the description it looks like the board has very little
external RAM, both considering total storage capacity and
bandwidth.  A single 8-bit wide DDR3 memory would have more
of both, at least for streaming data like video.  In general
I use the peripherals of a board to help me decide if I can
use it more than the FPGA itself.  If you're not interested
in video processing, it's probably OK.

-- 
Gabor

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