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Hi Tim, Tim Wescott <tim@seemywebsite.really> wrote: [] > In the OP's case, he's computing an output based on the wavelength of a > reference source, which leads me to believe that there's some sort of > interferometry going on, which would be sinusoidal because that's what > the peaks and valleys of the light are going to be. You nailed it! Unfortunately I cannot disclose the name of the project due to a certain amount of NDAs we have signed. It is possible that indeed nothing would happen otherwise, but I'd like to avoid looking for legal troubles... I prefer the technical ones ;-)Article: 156801
On 6/29/2014 9:19 PM, Tim Wescott wrote: > On Sun, 29 Jun 2014 07:58:50 -0700, BobH wrote: > >> On 6/28/2014 7:39 AM, alb wrote: >>> Hi there, >>> >>> we are measuring from a quadrature encoder the raw sine and cosine and >>> need to extract the angular position [1]. The position is then fedback >>> to a PID which drives a motor. >> >> Are you sure that the outputs are true sine and cosine? The analog >> output, optical devices I have worked with, output trapezoidal waveforms >> with a phase shift similar to sine/cosine. > > Interesting. I've worked on transmissive optical quadrature encoders > that specified a sine wave output. > > In the OP's case, he's computing an output based on the wavelength of a > reference source, which leads me to believe that there's some sort of > interferometry going on, which would be sinusoidal because that's what > the peaks and valleys of the light are going to be. > These encoders were HP (now Avago I think) transmissive, current output, optical quadrature sensors looking at a rotary wheel. We converted the current output to voltage, put some comparators on the voltages and fed the voltages to two channels of ADC. The comparators provided an integer value and we interpolated a fractional value from the ADC's based on the state of the comparator outputs. The outputs were triangular with some flat topping. It worked great and got me away from walking point on a really high visibility project. The manufacturing guys checked our results with high speed cameras and were amazed at the accuracy. That's about all I can say about that project for NDA issues. BobHArticle: 156802
Hello,
I have a custom PCB with FT2232H and FPGA on board. Writing from PC to FPGA=
via FT2232H in FT245 synchronuous FIFO mode works perfect. However, I've g=
ot some problems with reading from FPGA to PC in this mode. Below is a part=
of my VHDL code responsible for it:
USB_CLK: in std_logic;
RST : in std_logic;
TXE_n : in std_logic;
WR_n : out std_logic;
USB_DATA: inout std_logic_vector(7 downto 0);
RAM_DATA: in std_logic_vector(7 downto 0);
RD_ADDR: out std_logic_vector(12 downto 0);
signal RD_ADDRs: std_logic_vector(12 downto 0);
process (USB_CLK,RST,TXE_n)
begin
if RST=3D'1' then
RD_ADDRs<=3D(others=3D>'0');
USB_DATA<=3D(others=3D>'Z');
WR_n<=3D'1';
else
if USB_CLK'event and USB_CLK=3D'1' then
WR_n<=3DTXE_n;
if TXE=3D'0' then
USB_DATA<=3DRAM_DATA;
RD_ADDRs<=3DRD_ADDRs+1;
RD_ADDR<=3DRD_ADDRs;
else USB_DATA<=3D(others=3D>'Z');
end if;
end if;
end if;
end process; =20
=3D=3D=3D=3D=3D=3D=3D=3D=3D
And the software is as below (Delphi):
ResetAddressCounters;
ftresult:=3DFT_Read(FT_HANDLE,@FT_In_Buffer,8192,@Read_Result);
The RAM contents is 0,1,2,3...255,0,1,2....255,....,.... - total 8kB (32-te=
eth saw signal)
When I run the software for the first time, the data in FT_In_Buffer is rot=
ated right by a random number of bytes.For example 3 bytes:
253,254,255,0,1,2,3....255,0,1,2....255,0,1,2....252
Every next call to the above two software routines makes exactly 16 byte ro=
tation right.
What do I do wrong? Please help !!
Article: 156803On Friday, September 12, 2003 8:41:30 PM UTC+7, Arnaldo Oliveira wrote: > Hi! > > Could someone tell me how many transistors are integrated on the XC3S5000 > Spartan-3 device? > Thank You. > Arnaldo. > > -- XC3S5000 System Gate: 5M Equivalent Logic Cells: 74,880 I'm doing a research about method to estimate that number by using only datasheet.Article: 156804
kangsotheara@gmail.com wrote: > On Friday, September 12, 2003 8:41:30 PM UTC+7, Arnaldo Oliveira wrote: >> Could someone tell me how many transistors are integrated >> on the XC3S5000 Spartan-3 device? > XC3S5000 > System Gate: 5M > Equivalent Logic Cells: 74,880 > I'm doing a research about method to estimate that number by > using only datasheet. Hmm. Some dumb guesses, as they don't give so many details now. Maybe configuration bits are stored in 6 transistor SRAM cells. Dual-port BRAM probably takes somewhat more per bit. LUT4s should be made up of cascaded 2 input MUX to avoid glitches, if you have true and inverted select lines (8 transistors) the 7 MUX should be 8 transistors each, so 8*7+8 or 64. LUT bits need to be writable to use them as RAM, so a few more transitors for each bit to allow that. OK, try an easier way, instead. The XC3S5000 is supposed to be equal to 5M system gates. The usual gate is 4 transistors, so 20M. A rough guess is that the FPGA is a factor of two less efficient in gate usage than ASIC, so that would be 40M. Block RAM is 1872*1024 bits of, maybe 10 transistors each. LUT RAM is 520*1024 bits, of, maybe 20 transistors each. That is, 320 for an LUT4, which doesn't sound far off. We need 104 block 18x18 multipliers, which might take about as many transistors as the BRAM. That would be 184320 transistors each, which is about right for an 18x18 multiplier. This looks like it might be closer to 60M. -- glenArticle: 156805
Hi, I often see some FPGA positions requiring Python, Perl. What use of these scripting language? I know TCL used in FPGA tool chain. I am very curious about it? Thanks,Article: 156806
Hi, Around the tools (that indeed have usually TCL included) are often a wide variety of additional scripts to help you automate your designflow in several aspects (eg. code generators, make-mechanism, filter tool reports, manage regression tests,.... ). For these scripts is usually Phyton and Perl required, as TCL is not very compfortable. regards ThomasArticle: 156807
kangsotheara@gmail.com wrote:
> On Friday, September 12, 2003 8:41:30 PM UTC+7, Arnaldo Oliveira wrote:
>> Hi!
>>
>> Could someone tell me how many transistors are integrated on the XC3S5000
>> Spartan-3 device?
>> Thank You.
>> Arnaldo.
>>
>> --
> XC3S5000
> System Gate: 5M
> Equivalent Logic Cells: 74,880
>
> I'm doing a research about method to estimate that number by using only datasheet.
1) You do realize you just dug up an 11-year-old thread?
On Friday, September 12, 2003 ...
2) It would be a lot easier to estimate by the die area and process
node. Besides the config SRAM cells, don't forget that since
Virtex (original) and Spartan 2 all Xilinx FPGA's have buffered
routing. So everywhere you see connections between lines in the
FPGA editor there are active drivers.
3) Other than some academic exercise, why would you care how many
transistors are used? Are interested in the silicon efficiency
of FPGAs vs. ASICs?
--
Gabor
Article: 156808One example is the hdlmake project[1]: a very nice HDL project manager, bui= ld in Python. It allows you to flexibly manage multi-language and multi-pla= taform projects. Another example is MyHDL[2], a python-based HDL code generator[2]. [1] http://www.ohwr.org/projects/hdl-make [2] http://www.myhdl.org/ Le jeudi 3 juillet 2014 08:16:55 UTC-3, Thomas Stanka a =E9crit=A0: > Hi, >=20 > Around the tools (that indeed have usually TCL included) are often a wide= variety of additional scripts to help you automate your designflow in seve= ral aspects (eg. code generators, make-mechanism, filter tool reports, mana= ge regression tests,.... ). >=20 >=20 >=20 > For these scripts is usually Phyton and Perl required, as TCL is not very= compfortable. >=20 >=20 >=20 > regards ThomasArticle: 156809
On 03/07/2014 14:20, Aylons Hazzud wrote: > One example is the hdlmake project[1]: a very nice HDL project manager, build in Python. It allows you to flexibly manage multi-language and multi-plataform projects. > > Another example is MyHDL[2], a python-based HDL code generator[2]. > > [1] http://www.ohwr.org/projects/hdl-make > [2] http://www.myhdl.org/ > Here is another one: http://potentialventures.github.io/cocotb/ From their website: Why verify in Python? 1) It's easy to interface to other languages from Python 2) Python has a huge library of existing code to re-use like constraint solvers packet parsing/generation libraries. 3) Python is interpreted. Tests can be edited and re-run them without having to recompile the design or even exit the simulator GUI. 4) Writing Python is fast, it's easy to understand and everybody knows it. Aldec has a free webinar on the subject (10/07/14): http://www.aldec.com/en/events/426 Hans www.ht-lab.comArticle: 156810
Le jeudi 3 juillet 2014 10:44:48 UTC-3, HT-Lab a =E9crit=A0: > On 03/07/2014 14:20, Aylons Hazzud wrote: >=20 > > One example is the hdlmake project[1]: a very nice HDL project manager,= build in Python. It allows you to flexibly manage multi-language and multi= -plataform projects. >=20 > > >=20 > > Another example is MyHDL[2], a python-based HDL code generator[2]. >=20 > > >=20 > > [1] http://www.ohwr.org/projects/hdl-make >=20 > > [2] http://www.myhdl.org/ >=20 > > >=20 >=20 >=20 > Here is another one: >=20 >=20 >=20 > http://potentialventures.github.io/cocotb/ >=20 >=20 >=20 > From their website: >=20 >=20 >=20 > Why verify in Python? >=20 >=20 >=20 > 1) It's easy to interface to other languages from Python >=20 > 2) Python has a huge library of existing code to re-use like constraint= =20 >=20 > solvers packet parsing/generation libraries. >=20 > 3) Python is interpreted. Tests can be edited and re-run them without=20 >=20 > having to recompile the design or even exit the simulator GUI. >=20 > 4) Writing Python is fast, it's easy to understand and everybody knows it= . >=20 >=20 >=20 > Aldec has a free webinar on the subject (10/07/14): >=20 >=20 >=20 > http://www.aldec.com/en/events/426 >=20 >=20 >=20 > Hans >=20 > www.ht-lab.com WOW! This is the kind of project what I was looking for my DSP testbenchs! = For some time I had the feeling that Python would be ideal for testbenches,= and this just fits my dream. Thanks for sharing, I'll test it soon!Article: 156811
I have downloaded latest Diamond and installed it on my Gentoo OS.
It works normally except that I can't choose ECP5 part, because program lists none. I can see MachXO3L series, but no ECP5.
BTW, I do have 1year subscription license that is still current and program obviously can find and read it, since it lists it and enabled options ("Help->Debug License")
Has anyone tried this ?
Article: 156812Why not ask Lattice? Shouldn't be hard to submit a ticket.Article: 156813
Dne petek, 04. julij 2014 01:53:57 UTC je oseba KJ napisala: > Why not ask Lattice? Shouldn't be hard to submit a ticket. I did. Still waiting for an answer. Just thought to check here also, if anyone else had tried it.Article: 156814
On 7/4/2014 12:26 AM, Brane2 wrote: > Dne petek, 04. julij 2014 01:53:57 UTC je oseba KJ napisala: >> Why not ask Lattice? Shouldn't be hard to submit a ticket. > > I did. Still waiting for an answer. Just thought to check here also, if anyone else had tried it. I wouldn't use the online support, they normally aren't very good at actually answering your questions. Try your local FAE, they usually know what is going on and can give you a real answer to the questions you will ask next. -- RickArticle: 156815
BTW, I've got an anser that ECP is not covered by my current 1yr subscription license file and that the'll check if I am entitled to upgrade. Bummer. First they silently deleted whole XO3-H part of the series and now they want $$$ for a licence for ECP5 that is in absence of XO3-H my next choice. And there are no visible discounts this time- full price is EURO$1k. ;o/Article: 156816
On Thursday, July 3, 2014 9:20:12 AM UTC-4, Aylons Hazzud wrote: > One example is the hdlmake project[1]: a very nice HDL project manager, b= uild in Python. It allows you to flexibly manage multi-language and multi-p= lataform projects. >=20 >=20 >=20 > Another example is MyHDL[2], a python-based HDL code generator[2]. >=20 >=20 >=20 > [1] http://www.ohwr.org/projects/hdl-make >=20 > [2] http://www.myhdl.org/ >=20 >=20 >=20 > Le jeudi 3 juillet 2014 08:16:55 UTC-3, Thomas Stanka a =E9crit=A0: >=20 > > Hi, >=20 > >=20 >=20 > > Around the tools (that indeed have usually TCL included) are often a wi= de variety of additional scripts to help you automate your designflow in se= veral aspects (eg. code generators, make-mechanism, filter tool reports, ma= nage regression tests,.... ). >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > For these scripts is usually Phyton and Perl required, as TCL is not ve= ry compfortable. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > regards Thomas Thank you very much. It really looks like an excellent tool. I am still new to Linux.I download the first (hdlmake-v1.0) from the below = 4 files. And put it under ~(Home) directory in Ubuntu 12.04 LTS. I can rename the full hdlmake-v1.0 to hdlmake (as in its tutorial of the author)? hdlmake-v1.0 05/05/2013 15:20 37 kB 184 =09 hdlmake-v1.0-isyp 05/05/2013 15:21 40.8 kB 53 =09 hdlmake-v1.0-isyp.tar.gz 05/05/2013 15:20 220.3 kB 62 =09 hdlmake-v1.0.tar.gz 05/05/2013 15:20 100.5 kB 126Article: 156817
On 7/4/2014 7:06 AM, Brane2 wrote: > BTW, I've got an anser that ECP is not covered by my current 1yr subscription license file and that the'll check if I am entitled to upgrade. > > Bummer. First they silently deleted whole XO3-H part of the series and now they want $$$ for a licence for ECP5 that is in absence of XO3-H my next choice. > > And there are no visible discounts this time- full price is EURO$1k. ;o/ I'm confused. I thought that was the point of the paid license, you get the capability of supporting their full range of parts. If not, why bother paying for a license? Just what are you buying over the free edition of the tools? -- RickArticle: 156818
On Thursday, July 3, 2014 7:16:55 AM UTC-4, Thomas Stanka wrote: > Hi, >=20 > Around the tools (that indeed have usually TCL included) are often a wide= variety of additional scripts to help you automate your designflow in seve= ral aspects (eg. code generators, make-mechanism, filter tool reports, mana= ge regression tests,.... ). >=20 >=20 >=20 > For these scripts is usually Phyton and Perl required, as TCL is not very= compfortable. >=20 >=20 >=20 > regards Thomas Hi, I clone the repository, but I don't know what the following command does: $ python path/to/hdlmake/hdlmake "path/to/hdlmake/hdlmake" is the menifest file path, or the Python Tool pat= h? Thanks, ............ Cloning the repository If you prefer to get the source code, you need to have the popular Git vers= ion control system installed on your machine; if you don't, this page offer= s details on how you can configure Git to clone our repositories. Assuming = you have Git installed, running the following will clone (download all file= s in the) repository to a folder named hdlmake under your /home/user_name/ = folder: $ git clone git://ohwr.org/misc/hdl-make.git hdlmake Now you're almost ready to go. You can run hdlmake by changing directory to= a desired location and running $ python path/to/hdlmake/hdlmakeArticle: 156819
On Friday, July 4, 2014 8:20:34 AM UTC-4, fl wrote: > On Thursday, July 3, 2014 9:20:12 AM UTC-4, Aylons Hazzud wrote: >=20 > > One example is the hdlmake project[1]: a very nice HDL project manager,= build in Python. It allows you to flexibly manage multi-language and multi= -plataform projects. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Another example is MyHDL[2], a python-based HDL code generator[2]. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > [1] http://www.ohwr.org/projects/hdl-make >=20 > >=20 >=20 > > [2] http://www.myhdl.org/ >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Le jeudi 3 juillet 2014 08:16:55 UTC-3, Thomas Stanka a =E9crit=A0: >=20 > >=20 >=20 > > > Hi, >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > Around the tools (that indeed have usually TCL included) are often a = wide variety of additional scripts to help you automate your designflow in = several aspects (eg. code generators, make-mechanism, filter tool reports, = manage regression tests,.... ). >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > For these scripts is usually Phyton and Perl required, as TCL is not = very compfortable. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > regards Thomas >=20 >=20 >=20 > Thank you very much. It really looks like an excellent tool. >=20 >=20 >=20 > I am still new to Linux.I download the first (hdlmake-v1.0) from the belo= w 4 >=20 > files. And put it under ~(Home) directory in Ubuntu 12.04 LTS. I can rena= me >=20 > the full hdlmake-v1.0 to hdlmake (as in its tutorial of the author)? >=20 >=20 >=20 >=20 >=20 >=20 >=20 > hdlmake-v1.0 05/05/2013 15:20 37 kB 184 =09 >=20 > hdlmake-v1.0-isyp 05/05/2013 15:21 40.8 kB 53 =09 >=20 > hdlmake-v1.0-isyp.tar.gz 05/05/2013 15:20 220.3 kB 62 =09 >=20 > hdlmake-v1.0.tar.gz 05/05/2013 15:20 100.5 kB 126 On the author's website, he said: Downloading the compiled executable For downloading the compiled executable, click here and choose one of the f= iles without extension. Download to a location of choice, and you're almost= ready to use it! You can jump directly to the final steps. He said that "choose one of the files without extension". Is it this one: hdlmake-v1.0 05/05/2013 15:20 37 kB 184=20 In which directory do you put it? I am using Ubuntu 12.04. Thanks,Article: 156820
Le vendredi 4 juillet 2014 18:55:57 UTC-3, fl a =E9crit=A0: > On Thursday, July 3, 2014 7:16:55 AM UTC-4, Thomas Stanka wrote: >=20 > > Hi, >=20 > >=20 >=20 > > Around the tools (that indeed have usually TCL included) are often a wi= de variety of additional scripts to help you automate your designflow in se= veral aspects (eg. code generators, make-mechanism, filter tool reports, ma= nage regression tests,.... ). >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > For these scripts is usually Phyton and Perl required, as TCL is not ve= ry compfortable. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > regards Thomas >=20 >=20 >=20 > Hi, >=20 >=20 >=20 > I clone the repository, but I don't know what the following command does: >=20 >=20 >=20 > $ python path/to/hdlmake/hdlmake >=20 >=20 >=20 >=20 >=20 > "path/to/hdlmake/hdlmake" is the menifest file path, or the Python Tool p= ath? >=20 >=20 >=20 >=20 >=20 >=20 >=20 > Thanks, >=20 >=20 >=20 >=20 >=20 > ............ >=20 > Cloning the repository >=20 >=20 >=20 > If you prefer to get the source code, you need to have the popular Git ve= rsion control system installed on your machine; if you don't, this page off= ers details on how you can configure Git to clone our repositories. Assumin= g you have Git installed, running the following will clone (download all fi= les in the) repository to a folder named hdlmake under your /home/user_name= / folder: >=20 >=20 >=20 > $ git clone git://ohwr.org/misc/hdl-make.git hdlmake >=20 >=20 >=20 > Now you're almost ready to go. You can run hdlmake by changing directory = to a desired location and running >=20 >=20 >=20 > $ python path/to/hdlmake/hdlmake It is the path for the hdlmake executable.Article: 156821
Le vendredi 4 juillet 2014 19:15:14 UTC-3, fl a =E9crit=A0: > On Friday, July 4, 2014 8:20:34 AM UTC-4, fl wrote: >=20 > > On Thursday, July 3, 2014 9:20:12 AM UTC-4, Aylons Hazzud wrote: >=20 > >=20 >=20 > > > One example is the hdlmake project[1]: a very nice HDL project manage= r, build in Python. It allows you to flexibly manage multi-language and mul= ti-plataform projects. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > Another example is MyHDL[2], a python-based HDL code generator[2]. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > [1] http://www.ohwr.org/projects/hdl-make >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > [2] http://www.myhdl.org/ >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > Le jeudi 3 juillet 2014 08:16:55 UTC-3, Thomas Stanka a =E9crit=A0: >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Hi, >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Around the tools (that indeed have usually TCL included) are often = a wide variety of additional scripts to help you automate your designflow i= n several aspects (eg. code generators, make-mechanism, filter tool reports= , manage regression tests,.... ). >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > For these scripts is usually Phyton and Perl required, as TCL is no= t very compfortable. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > regards Thomas >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Thank you very much. It really looks like an excellent tool. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > I am still new to Linux.I download the first (hdlmake-v1.0) from the be= low 4 >=20 > >=20 >=20 > > files. And put it under ~(Home) directory in Ubuntu 12.04 LTS. I can re= name >=20 > >=20 >=20 > > the full hdlmake-v1.0 to hdlmake (as in its tutorial of the author)? >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > hdlmake-v1.0 05/05/2013 15:20 37 kB 184 =09 >=20 > >=20 >=20 > > hdlmake-v1.0-isyp 05/05/2013 15:21 40.8 kB 53 =09 >=20 > >=20 >=20 > > hdlmake-v1.0-isyp.tar.gz 05/05/2013 15:20 220.3 kB 62 =09 >=20 > >=20 >=20 > > hdlmake-v1.0.tar.gz 05/05/2013 15:20 100.5 kB 126 >=20 >=20 >=20 > On the author's website, he said: >=20 >=20 >=20 > Downloading the compiled executable >=20 >=20 >=20 > For downloading the compiled executable, click here and choose one of the= files without extension. Download to a location of choice, and you're almo= st ready to use it! You can jump directly to the final steps. >=20 >=20 >=20 > He said that "choose one of the files without extension". Is it this one: >=20 >=20 >=20 > hdlmake-v1.0 05/05/2013 15:20 37 kB 184=20 >=20 >=20 >=20 >=20 >=20 > In which directory do you put it? I am using Ubuntu 12.04. >=20 >=20 >=20 > Thanks, You may put it wherever it works best for you. When invoking the tool, you = just have to make sure to use the full path. Later, if you want to, you may put the directory in the $PATH environment v= ariable so you won't have to use the full path every time you use the tool.= Google how to do it, it is a very common task.Article: 156822
On 04/07/2014 17:23, rickman wrote: > On 7/4/2014 7:06 AM, Brane2 wrote: >> BTW, I've got an anser that ECP is not covered by my current 1yr >> subscription license file and that the'll check if I am entitled to >> upgrade. >> >> Bummer. First they silently deleted whole XO3-H part of the series and >> now they want $$$ for a licence for ECP5 that is in absence of XO3-H >> my next choice. >> >> And there are no visible discounts this time- full price is EURO$1k. ;o/ > > I'm confused. I thought that was the point of the paid license, you get > the capability of supporting their full range of parts. If not, why > bother paying for a license? Just what are you buying over the free > edition of the tools? > There's a "Request ECP5 support" form under ECP5 section on the website. http://ww3.latticesemi.com/ECP5DiamondLicenseRequest.html Looks to me as if they are just going to give you an add on but keeping tabs on who gets it (while the ECP5 is still virtual ? :-) Michael KellettArticle: 156823
Dne sobota, 05. julij 2014 08:24:29 UTC je oseba MK napisala: > > There's a "Request ECP5 support" form under ECP5 section on the website. > > > > http://ww3.latticesemi.com/ECP5DiamondLicenseRequest.html > Great ! Thanks, you were faster than their support :o) > Looks to me as if they are just going to give you an add on but keeping > > tabs on who gets it (while the ECP5 is still virtual ? :-) > Hehe- good one. ECP5- "Breaking The Rules" - meet first VFPGA - Virtual FPGA. First, you buy ECP3 as physical machine and then install ECP5 on top of it ;o) Honestly, this licensing stuff is annoying. I would understand it if I wanted some advenced sh** full of IP blocks etcetc. But they are charging serious $$$ for utility that basically configures merchandise they plan to sell. It's kind of utility equipment. Not to mention that for stuff I do, and at those densities, I'd be quite happy with lower level stuff. If someone gave me something like PCB editor for FPGA, where I could access and set basic structures and manipulate them as one would elements on PCB, I'd probably toss verilog in a second.Article: 156824
On 05/07/2014 12:28, Brane2 wrote: > I'd probably toss verilog in a second. That's your problem - switch to VHDL and everything will be rosy ! For what it's worth I use Aldec HDL (paid for $$$ but worth it) and only use the Lattice tools for some IP modules and synthesis. You get the Aldec tool (cut down but still quite good) in with the Lattice toolset. The stuff I do got way too big to want to think about gates a long while ago - latest project uses some 96 and some 128 bit arithmetic - I wouldn't fancy placing the flip-flops for that by hand ! Michael Kellett
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