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Rudolf Usselmann wrote: > ... > If Xilinx could find an alternative to this Wind/U, I think > they would have an excellent tool flow for Linux (plus fixing > the paralle port support to something native of course). > Apparently, Xilinx is doing just that, as mentioned a few days ago in another thread. Scroll down to message 5 in the thread. http://tinyurl.com/636ab -- My real email is akamail.com@dclark (or something like that).Article: 72701
Thanks for all the suggestions, they are valuable ideas that I will use
for similar problems.
However, I needed a divide by 2.5 in the end. A divide by 5 is simple
once you have a divide by 2.5. I wrote the following code:
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_unsigned.all;
--- Divide by 2.5 counter ---
entity div2p5 is
port (
clk : in std_logic;
q : out std_logic);
end div2p5;
architecture div2p5_arch of div2p5 is
signal cnt0 : std_logic_vector (2 downto 0) := "000";
signal cnt1 : std_logic_vector (2 downto 0) := "000";
signal q0 : std_logic;
signal q1 : std_logic;
begin
q <= q0 and q1;
process (clk)
begin
if(clk'event and clk = '0')then
if(cnt1 = "000") then
q0 <= '1';
end if;
if(cnt1 = "100") then
cnt0 <= "000";
q0 <= '0';
else
cnt0 <= cnt1 + 1;
end if;
end if;
end process;
process (clk)
begin
if(clk'event and clk = '1')then
cnt1 <= cnt0;
if(cnt0 = "010")then
q1 <= '0';
elsif(cnt0 = "011")then
q1 <= '1';
end if;
end if;
end process;
end div2p5_arch;
----------------------------
I needed a 20MHz clock on the Xilinx Spartan3 kit which has a 50MHz crystal.
Regards
Andrew
--
Spartan3 configuration JTAG download tool for GNU/Linux available from
http://www.rogerstech.co.uk/xc3sprog/
Article: 72702Robert Sefton wrote: > But he could use your 5-stage shift register + inverter if he initialized it > to "00011". Then delay the shift register output (any stage will work) 1/2 > cycle and OR it with the undelayed output to create a 50% duty cycle /5 > clock. The shift register gives you a /10 signal, right? I don't see how you generate the 50% duty cycle /5 clock from this by delaying 1/2 cycle and ORing it with undelayed output? Can you elaborate a bit? I think Jake's suggestion makes sense, you generate a /10 clock and delay it 2.5 cycles (in the faster domain) which corresponds to 2.5/10 = 1/4 cycle delay in the slower domain. By XORing two clocks with 1/4 cycle offset you get the double frequency with 50% duty cycle, in this case a /5 clock. -JS-Article: 72703
Jake Janovetz wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<4130AEF9.BF3AD39D@yahoo.com>... > > Since this is a very odd function to be implementing as part of a job, I > > assume it is a homework assignment. So I won't give any more > > details... > > I see this sort of answer a lot on this forum and, while I agree that > we don't need to be doing someone's homework, do we really need to > make this sort of statement? It's condescending and really > unnecessary. If you don't want to give details, just leave them out. > Let's give folks the benefit of the doubt and maybe we won't scare > people away. Condescending it may be, but if I don't explain why I am leaving out details, then he won't be able to correct me if I am wrong. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72704
Logically, this will work. But you don't need two counters, just one will do. Like another someone suggested, this algorithm generates two waveforms, each a divide by five, with a 2.5 clock phase shift. The results are ANDed to produce a waveform which is a divide by 2.5. Remove cnt0, make everything a function of cnt1 and you will get the same results. Notice that the result will not be square (50%/50% duty cycle). I believe this is what was originally requested. Andrew Rogers wrote: > > Thanks for all the suggestions, they are valuable ideas that I will use > for similar problems. > > However, I needed a divide by 2.5 in the end. A divide by 5 is simple > once you have a divide by 2.5. I wrote the following code: > > library IEEE; > use IEEE.std_logic_1164.all; -- defines std_logic types > use IEEE.std_logic_unsigned.all; > > --- Divide by 2.5 counter --- > entity div2p5 is > port ( > clk : in std_logic; > q : out std_logic); > end div2p5; > > architecture div2p5_arch of div2p5 is > signal cnt0 : std_logic_vector (2 downto 0) := "000"; > signal cnt1 : std_logic_vector (2 downto 0) := "000"; > signal q0 : std_logic; > signal q1 : std_logic; > > begin > > q <= q0 and q1; > > process (clk) > begin > if(clk'event and clk = '0')then > if(cnt1 = "000") then > q0 <= '1'; > end if; > if(cnt1 = "100") then > cnt0 <= "000"; > q0 <= '0'; > else > cnt0 <= cnt1 + 1; > end if; > end if; > end process; > > process (clk) > begin > if(clk'event and clk = '1')then > cnt1 <= cnt0; > if(cnt0 = "010")then > q1 <= '0'; > elsif(cnt0 = "011")then > q1 <= '1'; > end if; > end if; > end process; > > end div2p5_arch; > ---------------------------- > > I needed a 20MHz clock on the Xilinx Spartan3 kit which has a 50MHz crystal. > > Regards > Andrew > -- > Spartan3 configuration JTAG download tool for GNU/Linux available from > http://www.rogerstech.co.uk/xc3sprog/ -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72705
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:4131c785$0$27241$61ce578d@news.syd.swiftdsl.com.au... > Hi Rudi, > > Rudolf Usselmann wrote: > > > we are wrapping some of our IP Cores for EDK. That way they > > can be automatically instantiated in to a SoC and easily > > integrated. > > Good plan! I would love to see a wishbone -> opb bridge to get some of > that great opencores.org stuff into microblaze projects. opencores stuff is actually being used in OPB/Microblaze systems at many places :) > > However, we seem to have problems with include files. Our > > cores are written in Verilog, and we don't know how to > > specify the proper include path for include files. When > > EDK compiles the IP Core it can not find the include files > > unless we manually copy them to a local working directory. > > > > Does anybody know how to solve this problem ? > > Maybe the .pao (peripheral analyse order) file has something to do with > it? It lives in pcores/mycore/data/... I've only used it for VHDL > cores, but it probably has a role to play with verilog as well. the .PAO only specifies the order of compilation, but: xyz_defines.v that contains no modules but only defines would not produce any compiled code and as such will be ignored :( as much as I understand the all EDK core approuch is built on assumption that all parameters are propagated from top to bottom. So an include file with parameters clearly brakes the logic behind EDK cores. the only working solution is to prevent the EDK to synthesise the core and rerun synthesis for this single core from shell script (where the approp path to include dir can be given), optionally a build script could be made that copies the include file automatically to working dir what is not a good solution of course EDK support for verilog has been always a bit behind the VHDL support so maybe this problem gets and official fix too someday, or maybe some trick exist already :) AnttiArticle: 72706
Andrew, To easiest way generate a 20 Mhz clock signal on the Spartan-3 starter kit from the 50 Mhz osc would be to use the DCM. Is there any reason you have not considered that? Shalin- Andrew Rogers wrote: > Thanks for all the suggestions, they are valuable ideas that I will use > for similar problems. > > However, I needed a divide by 2.5 in the end. A divide by 5 is simple > once you have a divide by 2.5. I wrote the following code: > > library IEEE; > use IEEE.std_logic_1164.all; -- defines std_logic types > use IEEE.std_logic_unsigned.all; > > --- Divide by 2.5 counter --- > entity div2p5 is > port ( > clk : in std_logic; > q : out std_logic); > end div2p5; > > architecture div2p5_arch of div2p5 is > signal cnt0 : std_logic_vector (2 downto 0) := "000"; > signal cnt1 : std_logic_vector (2 downto 0) := "000"; > signal q0 : std_logic; > signal q1 : std_logic; > > begin > > q <= q0 and q1; > > process (clk) > begin > if(clk'event and clk = '0')then > if(cnt1 = "000") then > q0 <= '1'; > end if; > if(cnt1 = "100") then > cnt0 <= "000"; > q0 <= '0'; > else > cnt0 <= cnt1 + 1; > end if; > end if; > end process; > > process (clk) > begin > if(clk'event and clk = '1')then > cnt1 <= cnt0; > if(cnt0 = "010")then > q1 <= '0'; > elsif(cnt0 = "011")then > q1 <= '1'; > end if; > end if; > end process; > > end div2p5_arch; > ---------------------------- > > I needed a 20MHz clock on the Xilinx Spartan3 kit which has a 50MHz > crystal. > > Regards > AndrewArticle: 72707
"John Smith" <user@example.net> wrote in message news:41322E5D.5010802@example.net... > Robert Sefton wrote: > > > But he could use your 5-stage shift register + inverter if he initialized it > > to "00011". Then delay the shift register output (any stage will work) 1/2 > > cycle and OR it with the undelayed output to create a 50% duty cycle /5 > > clock. > > The shift register gives you a /10 signal, right? I don't see how you > generate the 50% duty cycle /5 clock from this by delaying 1/2 cycle and > ORing it with undelayed output? Can you elaborate a bit? > > I think Jake's suggestion makes sense, you generate a /10 clock and > delay it 2.5 cycles (in the faster domain) which corresponds to 2.5/10 = > 1/4 cycle delay in the slower domain. By XORing two clocks with 1/4 > cycle offset you get the double frequency with 50% duty cycle, in this > case a /5 clock. > > -JS- I meant to generate a /5 clock from the shift register with a 40% high duty cycle. I just realized the inverter in the feedback path needs to be removed. Anyway, take a 40% duty cycle /5 clock, delay it 1/2 cycle, and OR it with the undelayed version. You get a /5 clock with 50% duty cycle. You could also start with a 60% duty cycle /5 clock, delay it 1/2 cycle, and AND it with the undelayed version and also get a 50% duty cycle clock. Doesn't matter how you generate the clock (shift register or counter). The 1/2 cycle delay plus the gate just allows you to fix the duty cycle.Article: 72708
On Sat, 28 Aug 2004 15:33:47 +0100, Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk> wrote: >I'm trying to produce a square wave clock that is a fifth of the >frequency of a faster clock. This means that I must use both the falling >edge and rising of the clock. XST complains "Signal cnt cannot be >synthesized, bad synchronous description.", I have since learned that I >can only have one event per process. > >How do I produce a counter that counts on both clock edges? > >Regards >Andrew This comes up often enough, that it is in the FAQ. Although the problem is stated somewhat differently, getting a square wave from an odd division of a clock is really the same as dividing the clock by N.5 . In your case, you want to divide the rising edges of your source clock by 2.5 (or the combination of rising and falling edges by 5). Divide A Clock by N.5 http://www.fpga-faq.com/FAQ_Pages/0019_Divide_Clock_By_N_point_5.htm Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 72709
Hi All, Currently I am doing with a project which uses 5 Virtex 2 FPGAs(A,B,C,D,E). FPGA E gets data from a PC through the PCI-bus and distributes the data equally to the 5 FPGAs. In each FPGA there are 10 processing units for the incoming data. Since the 5 FPGAs are carrying out the same logic functions(FPFA E carries one more task --- communicating with PC using PCI-bus). They share the same VHDL source codes and the same UCF files. The only difference among them is the Pin Assignment. But, surprisingly, the different Pin Assignment create big problems for me. The clock period constraint was set to 144Mhz (4*36Mhz, the onboard oscillator) initially. After finishing the P&R, FPGA E met this 144Mhz requirement but all other 4 FPGAs failed. It is quite surprising because FPGA E contains more logic and uses more slices than the other 4 FPGAs. So I reduced the clock period to 108Mhz and redo the P&R for A,B,C,D. This time FPGA B&E passed. But A&C still failed. I had to reduce 2 Processing Units for A&C to make them running at 108MHz. I am quite new to FPGA and have no idea that why I get such strange results. Please help me and drop me some advice to solve this problem. Thanks a lot.Article: 72710
> I tried floorplanning some of the lower-level modules, and then saving > them into the [module].ucf file, but the higher-level modules (those > that instantiate the lower ones :-) didn't seem to pick up on the RPM > availability. Did you include the constraints in [module].ucf when you run ngdbuild on higher level modules? Jim (jimwu88NOOOSPAM@yahoo.com remove NOOOSPAM) http://www.geocities.com/jimwu88/chipsArticle: 72711
> But, surprisingly, the different Pin Assignment create big problems for me. > > The clock period constraint was set to 144Mhz (4*36Mhz, the onboard oscillator) initially. > So I reduced the clock period to 108Mhz ... > I had to reduce 2 Processing Units for A&C to make them running at 108MHz. 144MHz is not problematic on Virtex2 devices. 108MHz even less. There are many factors that could contribute to your problem. First would be how you might be implementing your logic. You can trash performance very rapidly by not taking the right approach. For example, multipliers can do 180Mhz, but only if you place your logic taking into consideration routing and use the registerd option. Second, yes, pin assignment or, more appropriately, floorplanning, has to be an integral part of the project. This isn't software, even though it might look like it. You have to put the time and effort into the initial planning stage in order to ensure success. Here, experience is invaluable. The tools are not going to save you from bad planning or the complete lack thereof. If your floorplanning is pretty much set in stone (due to your pin assignments) you can try two approaches to getting more performance. 1- Evaluate your logic to see if you can improve the way modules are implemented. You might add FF's in order to allow signals to move from stage to stage and meet timing. 2- Spend more money and move up to a faster speed grade. Without real details as to your implementation, it is very difficult to offer much more than the above. Oh, yes, "3" would be to hire a capable consultant to fix the problem for you. I am not one, so I can say this without ulterior motives. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" > So I reduced the clock period to 108Mhz and redo the P&R for A,B,C,D. This time FPGA B&E passed. But A&C still failed. I had to reduce 2 Processing Units for A&C to make them running at 108MHz. > > I am quite new to FPGA and have no idea that why I get such strange results. Please help me and drop me some advice to solve this problem. > > Thanks a lot.Article: 72712
"Dave" <apple2ebeige@yahoo.com> wrote in message news:d4aa8e8a.0408271702.3a36adaa@posting.google.com... > Using the Xilinx-supplied .mcs files I can program the configuration > PROM and run these reference designs: > > "Default Board Test MCS file" > "Digital Clock PCB monitor" > > But, this design: > > "MicroBlaze Master System" > > results in a non-responsive board. Anybody have any luck with this? > Thanks. The code for MicroBlaze RISC controller in the the MicroBlaze Master System is stored in the Platform Flash memory device, the same used to configure the FPGA. Check to see that jumper JP1 is set correctly. The JP1 jumper is in the upper right corner of the board. Check that the jumper connects the two left-most pins (positioned away from the right edge of the board). There is more on page 39 of the manual, also available online at the following link. http://www.xilinx.com/bvdocs/userguides/ug130.pdf When set in the position, the FPGA boots from the Platform Flash, then an application within the FPGA continues reading additional information from the serial Platform Flash. The MicroBlaze Master System converts the serial data to MicroBlaze instructions and saves them in the on-board SRAM and executes from there. CAVEAT: This is just a hunch, based on the information provided. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72713
Thanks Martin for the valuable advice. Actually I already made some improvements to the design by reducing Level_Of_Logic, adding FFs and giving some attributes. Since all the 5 FPGAs shares the same design and some of them can run at a higher frequency, I think floorplanning is a better choice to meet the timing requirement. For the current project, No manual floorplanning is done. After adding those VHDL files and UCF files, I just let ISE to run automatically. Frankly speaking, I know nothing about floorplanning. Could anyone recommend any book/tutorial on this topic?Article: 72714
Well, I answered the question myself on friday afternoon. Yes, I did have timing constraints, and yes the constraints were met.=20 However, a typo in the period of the clock made the constraints a little = bit too relaxed. I don't know what I was thinking when I calculated that = number in the first place, but it made the clock period almost 4 times=20 longer than the clock I'm utilizing... Completely my fault, and rather=20 embarrassing.. Anyway, I appreciate the input from all of you, and I'll get back to you = if I still get a huge difference in system performance when switching=20 from 6.1 to 6.2 with working timing constraints. Regards Johan Brian Philofsky wrote: >=20 >=20 > Johan Bernsp=E5ng wrote: >=20 > <snip> >=20 >> >> One question is still unanswered though, and I'd really appreciate=20 >> some input on this matter. How come that a system that synthesized=20 >> perfectly fine in ISE 6.1 also does that in ISE 6.2, but with a lower = >> performance (i.e. much more noise etc)? I have checkes all the coregen= =20 >> cores that I utilize and they are all the same version. I have also=20 >> checked my own logic, and it seem to synthesize the same way, but=20 >> still the result is so much better using 6.1. >=20 >=20 >=20 > There are many possible reasons for this but rather than going there=20 > first, I would like to ask the question of whether timing constraints=20 > were provided to the design and if so, were they met? The reason for=20 > the question is the way the software is designed to work is to look at = > the timing constraints provided and attempt to meet them. If they can = > be easily met, many times the software will give you that result withou= t=20 > trying to see exactly how fast the device can really go. This allows=20 > the tools to operate much faster and still deliver the results that wer= e=20 > requested. If no timing constraints are provided and a low effort leve= l=20 > is used (such as that is by default) the tools generally run very fast = > however do not produce the best possible result since it has nothing it= =20 > is trying to strive for. If no timing constraints are provided and a=20 > high effort level is used, the tools will provide a better result=20 > however without constraints being provided, the tools guess at the=20 > tradeoffs to make for timing so it still may not give as good of a=20 > result as if true timing constraints are provided. >=20 > Now if you are providing timing constraints that were met with a=20 > previous version of software and are not met now, that situation can be= =20 > more difficult to explain. In general that should not happen however w= e=20 > all know that it does from time to time. The best thing that you can d= o=20 > if you are in this situation is to contact either your FAE or the Xilin= x=20 > hotline to have this investigated. There may be a simple explanation o= r=20 > there may be a complicated one but generally it is very dependent on th= e=20 > design that is being run, the device being targeted, how the tools are = > being run and possibly a list of other factors. Without this=20 > investigation it would be difficult to fathom a guess at the reason for= =20 > that. >=20 >=20 > -- Brian >=20 >=20 >=20 >> >> Johan >> --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Embedded systems designer Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally.Article: 72715
Hi all, In TVPACK packing tool http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html three types of delays are being modelled 1 block delay (Delay Through a BLE) = 0.1 2 Intracluster net delay = 0.1 3 Intercluster net delay = 1.0 The above values are default values We can also specify different values. Can someone give me an insight bout how these values are being assigned and how 'll overall circuit delay change by changing them.The author just says they got these values as most suitable by experimentation. Here is the paper describing TVPACK -> http://www.eecg.toronto.edu/~vaughn/papers/fpga99b.pdfArticle: 72716
following is the sim script from xapp134, which runs mixed v & V simulation. Nothing is special. You need compile all files before sim them. vlib work vmap work work vcom -93 brst_cntr.vhd vcom -93 cslt_cntr.vhd vcom -93 ki_cntr.vhd vcom -93 mti_pkg.vhd vcom -93 rcd_cntr.vhd vcom -93 ref_cntr.vhd vlog mt48lc1m16a1.v vcom -93 sdrmc_state.vhd vcom -93 sys_int.vhd vcom -93 sdrm_t.vhd vcom -93 sdrm.vhd vlog tb_sdrm.v vsim work.t_sdrm view signals structure wave source source verwave.do run 3000 ns Hope it will help. Steven YuArticle: 72717
Jim Wu wrote:
>> I tried floorplanning some of the lower-level modules, and then saving
>> them into the [module].ucf file, but the higher-level modules (those
>> that instantiate the lower ones :-) didn't seem to pick up on the RPM
>> availability.
>
>
> Did you include the constraints in [module].ucf when you run ngdbuild on
> higher level modules?
Well, I have 'Use RLOC constraints' set in the 'Map properties'
dialogue, if that's what you mean ?
Just to be clear, I have a layout akin to:
top.v
|-top.ucf
+-middle.v
|-middle.ucf <-- contains floorplanner RPM
+-lower.v
+-lower.ucf <-- contains floorplanner RPM
in my Webpack 'Sources in project' box.
I have previously run Synthesize/Implement on 'middle.v' and 'lower.v'
and then edited the routed floorplan then saved as an RPM. When I then
run Synthesize/Implement on the 'top.v' module, the RPM's don't appear
to be being picked up (eg: the carry chains are in different relative
positions).
Is there something I have to do, so that Webpack will pick up the
submodule UCF's ? I thought having them in the tree (and hence in the
project) would be sufficient.
Cheers,
Simon.
Article: 72718
Hello to all,
I would like to integrate a buyied (target-)pci-core into an
xilinx-spartan3 fpga (xc3s200-pq208-4). The core is an *.edf.
The core has been originally designed for a virtex-system as you can
see in the ending part of the *.edf:
---<snip!>
(design (rename pci_core_32target "pci_32_target") (cellRef
pci_core_32target (libraryRef work))
(property PART (string "xc2v4000bf957-6") (owner "Xilinx"))
---<snap!>
Possibly this is the problem.
The fpga is coupled directly to the pci-bus.
So far, so good.
The situation:
--------------
When I turn power on, some pci devices including mine are no more
recognized by the master and the supply current increases very strong.
This is a hint for concurrent bus-driving. In addition the core does
not seem to answer the configuration requests of the master.
Has anyone an idea, what the cause of this behaviour may be?
NOTE: The mapping-tool reports, that all TBUF-elements are converted
to logic. Datebus-signals seem to be not bidirectional any more after
this.
("Transforming tristate2logic = off" in synthesis and mapping has no
effect!)
Thanks a lot,
T. Bartzick
Article: 72719
Thomas Bartzick wrote:
> Hello to all,
>
> I would like to integrate a buyied (target-)pci-core into an
> xilinx-spartan3 fpga (xc3s200-pq208-4). The core is an *.edf.
> The core has been originally designed for a virtex-system as you can
> see in the ending part of the *.edf:
>
> ---<snip!>
> (design (rename pci_core_32target "pci_32_target") (cellRef
> pci_core_32target (libraryRef work))
> (property PART (string "xc2v4000bf957-6") (owner "Xilinx"))
> ---<snap!>
>
> Possibly this is the problem.
>
> The fpga is coupled directly to the pci-bus.
> So far, so good.
>
> The situation:
> --------------
> When I turn power on, some pci devices including mine are no more
> recognized by the master and the supply current increases very strong.
> This is a hint for concurrent bus-driving. In addition the core does
> not seem to answer the configuration requests of the master.
>
> Has anyone an idea, what the cause of this behaviour may be?
>
> NOTE: The mapping-tool reports, that all TBUF-elements are converted
> to logic. Datebus-signals seem to be not bidirectional any more after
> this.
> ("Transforming tristate2logic = off" in synthesis and mapping has no
> effect!)
>
> Thanks a lot,
>
> T. Bartzick
Do you have try on an DESKTOP PCI SLOT, or on an custom PCI motherbaord.
If DESKTOP PCI SLOT, your sp3 is 3.3V tolerant only, and the major part
of the desktop are 5V IO Tolerant. So, you are driving SP3 IO with 5V
:-) . The way is to use sp2 or drivers between sp3 and pci finger.
Regards,
Laurent Gauch
www.amontec.com
Article: 72720Shalin Sheth wrote: > Andrew, > > To easiest way generate a 20 Mhz clock signal on the Spartan-3 starter > kit from the 50 Mhz osc would be to use the DCM. > > Is there any reason you have not considered that? > I didn't know that there is a DCM nor what a DCM is:) Clocking a counter on the positive edge and negative edge seemed easy enough at first. I have just started to learn VHDL and FPGA stuff, self taught so there's no course notes (or homework assignemts!). It has been a steep learning curve for me. Can anyone recommend any good and free articles to help learn VHDL for FPGA? Thanks Andrew -- Spartan3 configuration JTAG download tool for GNU/Linux available from http://www.rogerstech.co.uk/xc3sprog/Article: 72721
You can only export emulation only (using the ngc2edif utility or XST param). You don't need full export ability for the hardware compiles: you can use the emulation exportation to cut out the interface declaration and merge that into your EDIF. Then when you compile the NGC/NGO file from XST will get merged automatically. "HDLnewbie" <HDLnewbie.1bsrg6@info@totallychips.com> wrote in message news:HDLnewbie.1bsrg6@info@totallychips.com... > > Hi, > > Is it possible to do an edif export with ISE? I searched the > documentation and can't find an easy solution to this? > > > -- > HDLnewbie > ------------------------------------------------------------------------ > HDLnewbie's Profile: http://www.totallychips.com/forum/member.php?userid=8 > View this thread: http://www.totallychips.com/forum/showthread.php?t=1175 >Article: 72722
I think you should start with timing simulation rather than floorplanning. /Mikhail "Ying Hu" <huying@lastechnologies.com> wrote in message news:ee88431.1@webx.sUN8CHnE... > Thanks Martin for the valuable > advice. > > Actually I already made some improvements to the design by > reducing Level_Of_Logic, adding FFs and giving some attributes. > > Since all the 5 FPGAs shares the same design and some of them can > run at a higher frequency, I think floorplanning is a better choice to > meet the timing requirement. > > For the current project, No manual floorplanning is done. > After adding those VHDL files and UCF files, I just let ISE to run automatically. > > Frankly speaking, I know nothing about floorplanning. Could anyone recommend any book/tutorial on this topic?Article: 72723
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4130AEF9.BF3AD39D@yahoo.com... [snip] > The third is to use two registers, but one logic path with a MUX in the > front to switch registers as required by your function definition. [snip] If an FPGA with DDR support is the target, the DDR primitives can be instantiated directly. The ability to clock on the rising and falling edges is built-in without internal logic routing skew issues. If a CPLD is the target, maybe a different CPLD family would be a way to go; some Xilinx CPLDs have "clock doubling" built into the flops with the posedge/negedge triggering. Not all Xilinx CPLDs have the feature.Article: 72724
Andrew, DCM stands for Digital Clock Manager and has many features to generate new clocks of various frequencies and phase based on an input clock. Using the DCM would be the easiest and preferred solution to your design to generate the 20 Mhz clock. To read more about the DCM check out the DCM Application note at: http://direct.xilinx.com/bvdocs/appnotes/xapp462.pdf Cheers, Shalin- Andrew Rogers wrote: > Shalin Sheth wrote: > >> Andrew, >> >> To easiest way generate a 20 Mhz clock signal on the Spartan-3 starter >> kit from the 50 Mhz osc would be to use the DCM. >> >> Is there any reason you have not considered that? >> > > I didn't know that there is a DCM nor what a DCM is:) Clocking a counter > on the positive edge and negative edge seemed easy enough at first. > > I have just started to learn VHDL and FPGA stuff, self taught so there's > no course notes (or homework assignemts!). It has been a steep learning > curve for me. Can anyone recommend any good and free articles to help > learn VHDL for FPGA? > > Thanks > Andrew >
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