Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Greetings Please find list of books in Verilog fAQ at http://www.angelfire.com/in/verilogfaq/ In my personal opinion - Good book to start learning Verilog HDL : A Guide to Digital Design and Synthesis by Samir Palnitkar - Good verilog book with emphasis on synthesis Verilog HDL Synthesis, A Practical Primer by J. Bhasker - A allrounder book which has verilog, VHDL, digital design, synthesis. This book has long lasting value. HDL Chip Design : A Practical guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog by Douglas J. Smith Hope this helps Rajesh Bawankule In article <77m61e$qba$1@vixen.cso.uiuc.edu>, w-feng2@ews.uiuc.edu (feng weishi ) wrote: > "Joseph Kurian A. Manavalan" <jmanaval@viewlogic.com> writes: > > >Hello, > > >I would like to know what book a newbie to Verilog like myself would > >find quick, easy and at the same time comprehensive. > > >Joseph > > I'm asked to do a project using Verilog, and I have the same question too, > except that I want a book that have enough emphasis on synthesis, not just > a language introduction. > > Thanks aaaaaa lot! > > --- Weishi > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14151
On Tue, 12 Jan 1999 10:03:06 -0500, "Jeffrey L. Madden" <jlmadden@iupui.edu> wrote: <snipped> your code is fine, although a little verbose, as already pointed out. maybe fpga express is right, and the output *is* a constant. is CLEAR a constant '1'? are CLK or D constant? evanArticle: 14152
On Thu, 14 Jan 1999 16:17:24 +0100, "Stefan Klanke" <klanke@usa.net>
wrote:
>architecture combin_arch of combine is
> signal buf: UX01;
>begin
> buf <= IH(10) AND IH(9) AND IH(8);
> buf <= IL(10) AND IL(9) AND IL(8);
> process (IL,IH)
> begin
> O <= "0000000000000000";
> O (7 downto 0) <= IL (7 downto 0);
> O (15 downto 8) <= IH (7 downto 0);
> end process;
>
>end combin_arch;
this isn't relevant to your bus naming problem, but do you realise
that most of this architecture is redundant? it could be rewritten as:
architecture combin_arch of combine is
begin
O <= IH(7 downto 0) & IL(7 downto 0);
end combin_arch;
you also have two drivers on 'buf', which is generally not a good
thing (although, in this case, 'buf' is unused and is optimised out).
the synthesiser wont recognize them as tristate drivers and, if they
hadn't been optimised away, the implementation tools would have
reported an error.
evan
Article: 14153
On Thu, 14 Jan 1999 20:27:09 +0200, "Ido Kleinman"
<kleinn@REMOVETHIS.mail.biu.ac.il> wrote:
<snipped>
a few more thoughts about your point (1).
1) presumably you're only using package std_logic_1164. this package
doesn't define any relational operations on std_logic_vector (SLV, for
short), so you're actually using the language's built-in operators.
these have some significant disadvantages:
a) both operands must be SLVs, and
b) the language does not give any numerical significance to the
contents of the vector. the two vectors (which can be of different
lengths) are left-aligned, and comparison occurs on a bit-by-bit
basis, from left to right. this means that the comparison result is
often not as 'expected', ie. "1010_1011" is *less* than "110_0000".
2) literals of the form x#yy# are *integers*. 171, 16#AB#, and 16#A_B#
are all the decimal integer 171, and so can't be used in a built-in
SLV comparison, from point 1(a) above.
3) literals of the form x"yy", where x is B, O, or X, and y is 0 or 1,
are bit-string literals. in VHDL'87 these are interpreted exclusively
as bit_vectors (and so they *can't* be used in a built-in SLV
comparison). in VHDL'93 the literal is interpreted according to
context, and could be of any enumerated type that includes '0' and '1'
(ie. the literal *can* be used in a built-in SLV comparison).
the standard form to ensure that a bit-string literal will be
interpreted by both a '93 compiler and an '87 compiler as an SLV is,
as someone else pointed out, to_stdlogicvector(bit_vector'("yyyy")).
4) synopsys is, of course, '87, while metamor is '93. however, it's
worse than this, since - as you've noticed - synopsys doesn't support
bit string literals correctly. X"AB" is not recognised, and you can't
use underscores inside the literal. this is strange, since their VHDL
manual correctly defines bit-string literals, and the language support
section at the back says nothing about limited support for them.
5) the important question - why, given the limitations in (1) above,
are you using the built-in relational operators? it makes much more
sense to use an arithmetic package ('std_logic_arith' for synopsys
synthesis, 'numeric_std' for the rest of the world). the only
disadvantage is that you should be using the new types 'signed' (for
2's complement) and 'unsigned' (for unsigned binary). you can then
carry out your relationals ops against signed, unsigned, or integer
quantities.
6) if you must use SLVs, then you can use the synopsys packages
std_logic_unsigned, if your SLVs contain unsigned quantities, or
std_logic_signed, if they contain 2's complement numbers. however,
this is not a good idea - it makes your code a real dog to port.
7) both (5) and (6) above also solve the problem of comparing vectors
of different lengths and, of course, you can do simple comparisons
against integers, ie.
if MY_SIG > 171 then ...
or if MY_SIG > 16#AB# then ...
evan
Article: 14154I'm beginning to believe that the problem does not exist in the synthesis but rather the implementation. I've been implementing the designs at the dos prompt (not using XILINX Design manager) because the XILINX software gives me an error. Does anyone know where some information is on how each of the implementation tools that are provided with Foundation Design manager (i.e. ngdbuild, map, par)? If so it would be appreciated. Nick ems@riverside-machines.com.NOSPAM wrote: > On Tue, 12 Jan 1999 10:03:06 -0500, "Jeffrey L. Madden" > <jlmadden@iupui.edu> wrote: > > <snipped> > > your code is fine, although a little verbose, as already pointed out. > > maybe fpga express is right, and the output *is* a constant. is CLEAR > a constant '1'? are CLK or D constant? > > evanArticle: 14155
When I bring in a file from Mentor into Foundation Design Manager and try to implement it it gives me an error the the netlist is not complete. Does anyone know if this is because Mentor Graphics uses a generic parts library when creating the "edif" netlist? Thanks, NickArticle: 14156
In article <77ne38$or3@tandem.CAM.ORG>, denis lachapelle <sysacom@cam.org> writes >Is there many poeple using the AT40K family ? >Which tools do you use? > >Thank you, > > >Denis Lachapelle, sysacom@cam.org >Sysacom R&D plus inc. >www.cam.org/~sysacom >tel 450 585-6396, fax 450 582-3231 > > I went to an Atmel 40k seminar last year, and received their development system. Couldn't get my head around it though. Its very unfriendly to use. If I had not won the flight simulator ride, it would have been a complete waste of time. :-) I now use vantis for cpld's and xilinx for fpga's. -- Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 14157
In article <uo9d84lfc11.fsf@netcom3.netcom.com>, Tom Lane <tgl@netcom.com> wrote: > handleym@ricochet.net (Maynard Handley) writes: > > Tom Lane <tgl@netcom.com> wrote: > >> 2. What you actually want is not a DCT but a quantized DCT. Any > >> multiply that you can push to the DCT-coefficient end of the operation > >> can be eliminated by folding its constant into the coefficient > >> quantization factors that you're going to have to multiply or divide by > >> anyway. If you follow this road you find that you only need 5 or so > >> multiplies per 1-D DCT inside the "DCT box" itself. > > > Call me an idiot, Tom, but it's not clear to me quite what you're getting > > at here. > > The data flow simply following the spec looks something like > > loop > > parse an AC coeff > > multiply it by quantization_scale*matrix[which AC Coeff] > > end loop > > IDCT this block which equals > > loop over rows and columns > > do a bunch of coeff[i]*some_fixed_point_value + more of the same > > > You seem to be proposing that this be replaced with > > loop > > parse an AC coeff > > end loop > > IDCT this block which equals > > loop over rows and columns > > do a bunch of coeff[i] > > *quantization_scale*matrix[which AC Coeff]*some_fixed_point_value > > + more of the same > > > So how does this in and of itself reduce the number of multiplies? > > No, that's not what I'm getting at. What you do is adjust the > quantization multipliers (matrix[n] in your pseudocode above) > by multiplying them by DCT-determined constants before you start > the decoding pass. The pseudocode still looks much as in your > first example --- but the number of multiplies needed per 1-D DCT > drops from 11 or so to 5 or so (something that can't be seen in > your pseudocode, since it glosses over the contents of the DCT step). > Alright, I get it. The ingredient I missed is that it's not a case of possibly having to multiply ANY of the elements of the 8x8 dequant matrix with any of the 11 coeffs involved in the IDCT. Rather specific IDCT coeffs go with specific matrix elements. Thanks for your patience in explaining. Maynard > JPEG doesn't have quantization_scale, btw, unless you are implementing > some of the Part 3 extensions. > > > Is your assumption that quantization_scale changes infrequently (heck with > > JPEG I don't know---maybe it's a one-off for the entire image) so that at > > the start before parsing we calculate a matrix of size [64][11] which > > equals > > quantization_scale*matrix[0..63]*theSpecificIDCTCoeff[0..10]? > > I'm not following what the second subscript is supposed to represent there, > but it's not needed in what I'm thinking of. > > regards, tom lane > organizer, Independent JPEG GroupArticle: 14158
I'm currently designing a fpga-based system for a wide consumer market. Since this is my first design to go on production, I'm concerned about the intellectual property of the hardware implemented in the FPGA. Nobody likes to spend months of effort in the lab, while some hacker in the other side of the world reads out the eeprom with the programming bitstream and somehow gets my code (not funny at all). Is it possible to obtain the hdl code or any revealing information by doing reverse engineering? I use both Altera's and Xilinx's FPGAs How do you guys deal with intellectual property? Cya. Antonio Moreno schaltung@hotmail.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14159
Actually, there is a little-known bit of C code on the Xilinx website that was written back in 1989. It is provided "as is" and is not a Xilinx product (which means it's not supported, patched, etc.), but it may be of some help to you. Check out: http://www.xilinx.com/techdocs/htm_index/utils_prom.htm The file is called dn_ld.zip. Regards, Hobson Frater Xilinx ApplicationsArticle: 14160
On 15 Jan 1999 14:39:29 GMT, "Austin Franklin" <aus3tin@darkroom.com> wrote: >> The cost of developing an FPGA/core PCI interface system just got a lot >> cheaper. >> PLD Consulting Editor Murray Disman gives the scoop on a two team >> approach in >> which two companies provide a populated board and netlist for a PCI >> target for >> just $695. Compare that to $8,000 for a PCI core. Wow. But there's a >> catch. >> >http://www.edtn.com/shared/redirect?url=http://www.edtn.com/pld/pldp.htm&sou >rce_code=26 > >You forgot to mention this little 'tidbit', which is probably what you mean >by 'there's a catch': > >"The user is free to use the core to develop their system, but must >negotiate the purchase of the core if the system goes into production. " > >What's that going to cost? Logically, not more than buying the whole thing from Xilinx. ($8995 last time I looked.) One would hope you can at least credit the original purchase against this. But deferring the major cost to the production schedule instead of the development schedule can make all the difference to some projects... - BrianArticle: 14161
CALL FOR PAPERS 4th International Workshop on Applications of the Reed-Müller Expansion in Circuit Design August 20-21, 1999, University of Victoria, Victoria B.C., Canada Non-Restrictive topic list includes: AND-XOR representations, decision diagrams, spectral techniques, testability issues Submission Deadline: April 1, 1999 Submit 5 copies of drafts up to 20 pages in length to: Michael Miller, Workshop Chair Department of Computer Science University of Victoria Victoria, B.C., Canada V8W 3P6 or email PS, PDF, Latex or MS Word files to: rm99@csr.uvic.ca For more information: http://www.csr.uvic.ca/~mmiller/RM99Article: 14162
> > Questions: > > - Any of the big, fast & popular chips have public specs? > - Anyone published reversed engineered specs? > - Any FPGA vendors interested in supporting development of a free, > retargettable synthesis tool? (Development style similar to GCC/EGCS). > - Anyone willing to run a bunch of compiles & simulations from time to > time, and return the results of analysing the output to me? > - Anyone interested in collaborating on a free FPGA synthesis tool? > -- Willing to run compiles & simulations from time to time using > your FPGA vendor's tools, and send me the results. I have several versions of the Xilinx Foundation developement system, and would be wiling to run compiles for you. I can set up multiple versions of teh developement system on multiple machines if need be. I also have an old version of Orcad Express, but have never figured out how to use it. Good luck. I wish you lots of success. Lots of people would like such a tool (IMHO). Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://www.devili.iki.fi/cpm PRIMARY US MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpm SECONDARY US MIRROR AT : http://CPM.INTERFUN.NETArticle: 14163
OK, what the world needs is not more tools for the FPGA preisthood. These corporate types who do the one trick pony. The world needs easy to use tools for the rest of us, who do an occassional FPGA or CPLD. The last great tool for us was the PLDShell program writen by INTEL to support their now defunct PLDs and FPGAs. I learned that system and produced useful applications in less time then it took me to just install Foundation or Max! Rocky LavineArticle: 14164
> Anyone out there have some C code > they would like to contribute to the cause? Although the algorithm is > not complex, it is not easy to glean from the data book description. > > -- > > Rick Collins Rick, I have Motorola 68000 assembly-language code that loads two 4010's from config tables built into the microprocessor eprom image. We also wrote a DOS (PowerBasic) program that builds the eprom image from the Motorola hex-format uP code and two Xilinx .RBT files. The source code has lots of painfully-discovered timing and sequencing notes. Yes, it's silly for everybody to keep re-inventing this stuff, especially based on the sparsely-scattered collection of vague hints that comprises most FPGA documentation. One or two solid appnotes could save customers literally hundreds of thousands of hours of reinvention. John -- ********************************************************************h John Larkin, President phone 415 753-5814 fax 753-3301 Highland Technology, Inc 320 Judah Street jjlarkin@worldnet.att.net San Francisco, CA 94122 http://www.highlandtechnology.comArticle: 14165
> I feel your pain. I just went through the same process. It took me about > 2 weeks to convert one design with about 7 VHDL files. Unfortunately, > Xilinx doesn't really explain the various VHDL differnces you are likely > to encounter between the two compiliers. Well, so much for VHDL 'portability'! > And the syntax stuff is just > the tip of the iceburg! I found that the resulting gates produced are > very inefficient unless you make even more drastic changes to your VHDL. I guess if you did schematics in the first place, this wouldn't have been a problem. Sorry, I just couldn't resist the 'poke in the ribs' ;-) AustinArticle: 14166
Could one of you please point me in the right direction of how to interface a 300 MHz core to a 50 MHz bus? (Frequencies only examples) Basically I want to run a core processor at a much higher speed than the bus that I must connect it to. How is this usually done? TIA EricArticle: 14167
http://www.angelfire.com/ca/verilog/ Although there are several websites for Verilog related resources, there are only a few for Verilog PLI. This website is dedicated to Verilog PLI (although there are links/pages to guide you if you do not know, for example, what Verilog is). It has been designed as a meeting point for newcomers looking for a clue as well as gurus who want to help them. It also has a free tutorial on Verilog PLI and several examples as references. Comments and suggestions are welcome. - Swapnajit Mittra. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14168
Hi Could you please send me your comments on what I have written "as a summary" about the latest achievements on the RTR "Run-Time-Reconfigurable" logic field also could you give hints and advice on which field should I consider in my next writing. The address is : http://www.geocities.com/SiliconValley/Pines/6639/fpga you can download the ps file from http://www.geocities.com/SiliconValley/Pines/6639/fpga/main.ps.gz Note: the writing is in its draft state now Thanks in advance for your timeArticle: 14169
Currently a student in fourth year at ESIEE (Ecole Superieure
d'Ingenieurs en Electronique et Electrotechnique), a French five-year
Electrical and Electronic Engineering college leading to a degree
equivalent to a Master of Science in Electrical Engineering and Computer
Science, I am looking for an internship from May to July 1999 as part of
my course.
I would like to work as an ASIC designer and I think it is very
important for a French engineer to acquire international work
experience.
Please do not hesitate to contact me if you want to have my CV.
Benoit Michel
michelb@esiee.fr
Article: 14170I can recommend The Programmable Logic Jump Station at http://www.optimagic.com as a good place to start. It has . . . Introductory material: http://www.optimagic.com/faq.html Free or low-cost design software: http://www.optimagic.com/software.html Books on programmable logic, etc.: http://www.optimagic.com/books.html Tutorials on VHDL, Verilog: http://www.optimagic.com/tutorials.html FPGA boards: http://www.optimagic.com/boards.html ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Jim King wrote in message <77n9re$eud$1@trog.dra.hmg.gb>... >Hi, >One of our staff here is looking for a general introduction to FPGAs. >Preferably something that is not too vendor specific, but gives an idea of >how they work, how they are used, etc. >Can anybody suggest books, or URLs of useful material. > >Cheers > >Jim King >Defence Evaluation and Research Agency >Defford >Worcestershire >WR8 9DU >UK > >Article: 14171
BTW, the Atmel tools are available for free via the Atmel web site at http://www.atmel.com/fpga_software.html . You can also find a fairly comprehensive list of free or low-cost FPGA/CPLD design software on The Programmable Logic Jump Station at http://www.optimagic.com/lowcost.html . ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- denis lachapelle wrote in message <77ne38$or3@tandem.CAM.ORG>... >Is there many poeple using the AT40K family ? >Which tools do you use? > >Thank you, > > >Denis Lachapelle, sysacom@cam.org >Sysacom R&D plus inc. >www.cam.org/~sysacom >tel 450 585-6396, fax 450 582-3231 > >Article: 14172
This is a multi-part message in MIME format. --------------3BFEEEF870862C57DFAA3F50 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit It is possible for a hacker to copy your design if you use a RAM programmed FPGA assuming he can readout the serial EPROM or monitor the bitstream going into the FPGA. If you want to avoid this problem you need to use a device which gets programmed in the factory like an Actel part or a FLASH or EPROM based PLD. Antifuse FPGA's such as Actel's appear to be more resistant to bitstream copying than the other technologies. There are various tricks you can play to make SRAM FPGA's resistant to bitstream copying but they all increase cost or reduce reliability in some way. Copying the bitstream does not tell the hacker how the design works or give him it in a format which is easy to change or improve. A lot of information is lost between the HDL and the bitstream: the situation is worse for a hacker than trying to reverse compile a C program from machine code. Chances are, unless you have done something very smart in your design, reverse engineering it from the bitstream is harder work than redesigning it from scratch. So having your design copied is a real threat but having it reverse engineered is probably only a theoretical risk. Most people forget about it and concentrate on getting the product to market fast with the FPGA's with the best price/performance. Tom Kean. schaltung@hotmail.com wrote: > I'm currently designing a fpga-based system for a wide consumer market. Since > this is my first design to go on production, I'm concerned about the > intellectual property of the hardware implemented in the FPGA. > > Nobody likes to spend months of effort in the lab, while some hacker in the > other side of the world reads out the eeprom with the programming bitstream > and somehow gets my code (not funny at all). > > Is it possible to obtain the hdl code or any revealing information by doing > reverse engineering? I use both Altera's and Xilinx's FPGAs > > How do you guys deal with intellectual property? > > Cya. > Antonio Moreno > schaltung@hotmail.com > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own --------------3BFEEEF870862C57DFAA3F50 Content-Type: text/x-vcard; charset=us-ascii; name="tom.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Tom Kean Content-Disposition: attachment; filename="tom.vcf" begin:vcard n:Kean;Tom tel;fax:UK +44 131 556 9247 tel;work:UK +44 131 556 9242 x-mozilla-html:TRUE org:Algotronix Ltd. adr:;;P.O. Box 23116;Edinburgh;;EH8 8YB;Scotland version:2.1 email;internet:tom@algotronix.com title:Director note:Web Site: www.algotronix.com x-mozilla-cpt:;4768 fn:Tom Kean end:vcard --------------3BFEEEF870862C57DFAA3F50--Article: 14173
Eric W Braeden wrote in message <77qnfj$25u$1@news.erinet.com>... >Could one of you please point me in the right >direction of how to interface a 300 MHz core >to a 50 MHz bus? (Frequencies only examples) > >Basically I want to run a core processor at >a much higher speed than the bus that I must >connect it to. How is this usually done? A common technique is to put a FIFO (first-in, first-out) memory between the two. That lets the processor run at full speed when reading or writing to the I/O bus. Wade Peterson Silicore Corporation http://www.silicore.net/Article: 14174
thank you , but as you said the question is , how good are compilers today, like altera's maxplusII , for my self I made designs using AHDL and some times I had to go to lower level (gates) so the AHDL compiler could under stand what I mean, are VHDL compilers better then me? and to what extant , regarding clock speed and silicon area? and yes I'm VERY interested in knowing more about this. Jamie Lokier wrote: > This is interesting, as I know someone who switch from _V_HDL to _A_HDL > because he found VHDL too difficult to work with, and AHDL much more > straightforward. > > His AHDL code contains a fair amount of asynchronous stuff, crossing clock > domains, tight timing etc. (I know, I work with his code). So it can > be done. > > I don't know much about either language (except I have had to read and > understand some AHDL), but it does appear that with VHDL, you are > relying to some extent on the compiler knowing what you mean by various > constructs. See other threads in this very newsgroup for "how do I > generate XXX flip-flop" questions. > > -- Jamie > > Brett George writes: > > do you want me to answer all three queries? > > Anyway, thought you might be interested to know that I have performed > > one design using AHDL/graphical logic. And found AHDL very difficult > > to use when trying to do things more complicated than can be visualised > > in terms of gates. Things like asyncronous state-machines had to be > > re-designed > > in terms of edge triggered FFs etc. > > We will be making the move to VHDL shortly, for the next design and > > expect > > much better results. It seems to be a lot more flexible, as it is an > > actual language, > > rather than a text based logic system. > > > Will let you know how it went in a few weeks if you are still interested. > > > Brett. > > > aweas wrote: > > >> Hi > >> I think a lot of poeple made the transfer from altera's ahdl to vhdl. > >> those how did it , can you please give me some feed back about the > >> results. > >> and info about the transfer to VHDL . > >> I'll be happy to get as much answer's as possible > >> > >> thank you > >> Aweas
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z