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On Aug 16, 9:53=A0am, ghelbig <ghel...@lycos.com> wrote: > On Aug 15, 1:37=A0pm, MarkAren <markare...@yahoo.com> wrote: > > > > > > > Hi All, > > > I have just compiled a NIOS II core into Cyclone I part (I was given > > an old MJL demo board) and compiled some trivial C. Everything seems > > to work as advertised. > > > I still haven't figured out the time limited nature of the NIOS II > > SOPC builder, could someone enlighten me please. There seems to be a > > 60 minute limit between creating the FPGA code (Verilog) and compiling > > a new FPGA image, or does that limit apply to time between compiling > > an image and programming a part ? > > > Also, what is the difference between the web edition and the fully > > paid up version of Quartus II. > > > All tools above are V7.2. > > > I am only experimenting at the moment and I need to understand the > > limitations of the tool chain before I invest too much more time and > > effort in this educational project,. > > > Many thanks, > > > Mark > > As I recall, the time limit starts after downloading the FPGA. > > I was told that the difference between 'web' and 'full' was the number > (size) of devices supported. > > I'm pretty sure that all of this is documented on the Altera web site. > > G.- Hide quoted text - > > - Show quoted text - Hi Guys, Thanks for the comments so far. I agree that US$600 is a load of money for the hobbyist, but this is one hell of a useful tool from where I sit. So as far as the JTAG download session being valid for 60 minutes, that makes sense. What if one was to burn the image into FLASH then use another device to download the configuration using AS or PS formats ? I assume that the timeout mechanism is within the FPGA, so this won't work (unless the design reboots itself every 58 minutes ?) Comments please. Thanks, MarkArticle: 134526
I just inserted an inferred ram module into my code, and all of a sudden it takes forever to synthesize...I only inferred one ramblock...is there anything I can do to get it down to a reasonable time? I have a lot of warnings, but still...I went from a few seconds to synth now taking minutes.....?? thanks for your helpArticle: 134527
Very informative, johnathan...thanks for that. laserbeak...is there some compiler directives you could use analagous to C's #ifdef's for excluding code in a particular build? I would look this up, but I don't even have a verilog book :P....just learning from the net...Article: 134528
On 16 Aug., 13:25, andersod2 <thechrisander...@gmail.com> wrote: > I just inserted an inferred ram module into my code, and all of a > sudden it takes forever to synthesize...I only inferred one > ramblock...is there anything I can do to get it down to a reasonable > time? =A0I have a lot of warnings, but still...I went from a few seconds > to synth now taking minutes.....?? We need more data: - synthesis tool? - language? - taget technology? - size of the ram? KoljaArticle: 134529
On Sat, 16 Aug 2008 04:36:35 -0700 (PDT), andersod2 wrote:
>is there some compiler directives you could use analagous
>to C's #ifdef's for excluding code in a particular build?
Absolutely:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
module design(...);
...
endmodule
`ifdef A_COMPLETELY_RIDICULOUS_MACRO_NAME
module testbench;
...
design design_instance(....);
...
endmodule
`else
module toplevel;
...
endmodule
`endif
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Now here's the trick: Almost every Verilog tool
will automatically `define a tool-specific macro
before every compile run. So, for example:
`ifdef VCS
// this code will be compiled only when using Synopsys VCS
`endif
`ifdef INCA
// this only when using Cadence simulators
`endif
`ifdef MODEL_TECH
// this only when using Mentor simulators
`endif
`ifdef synthesis
// Synplify, and perhaps other synth tools, define this
`endif
I'm sure there's one of those for each synthesis tool,
but I don't have those at my fingertips. Anyway, you can
deal with that for yourself rather easily because you can
either hack in a single `define directive in a tiny file
that gets compiled first, or (better) define on the compile
command line - this works for every Verilog tool I've ever
used:
vlog|vcs|ncvlog|your_choice_of_tool +define+MY_MACRO files.v
Finally, if it's synthesis that's an issue, all synthesis tools
respect some kind of synthesis-on/off pragma in your code.
Personally I passionately loathe the use of pseudo-comments
in this way, but you should find this will allow you to
include simulation-only code in a file that may also be
synthesised:
module d_ff (input clock, input d, output reg q);
always @(posedge clock) begin
// synthesis translate_off
$display("The clock ticked at time %t", $time);
// synthesis translate_on
q <= d;
end
endmodule
The exact form of the synthesis on/off pragma will
vary from one synthesis tool to another, as you might
guess. RTFM.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 134530
A system with a 16-wide input bus, clocked (negative edge) into a
16-wide register.
(Actually a sub-set of a real system.)
The system clock input is balanced; it is converted to single ended
and fed to a clock buffer to clock the register.
The system outputs are
1/ the register output
2/ the single ended clock drive
I want to constrain the register output so that it changes less than
2.6ns after the fall of the clock output- a constraint between two
outputs.
Here's the constraint section of my UCF file:
#################################################
NET "CLK_120MHZ_P" TNM_NET = FFS "CLK_120MHZ_P";
TIMESPEC "TS_CLK_120MHZ_P" = PERIOD "CLK_120MHZ_P" 8 ns HIGH 50 %;
NET DATA_OUT_CLK TNM=PADS ck_out;
NET DATA_OUT* TNM=PADS d_out;
# the constraint mentioned above
TIMESPEC "TS_output_ck_to_data" =FROM ck_out TO d_out 2.6ns;
# two more constraints- somewhat arbitrary
TIMESPEC "TS_ext_ck_to_data" =FROM CLK_120MHZ_P TO d_out 5.5ns;
TIMESPEC "TS_ext_ck_to_ckout" =FROM CLK_120MHZ_P TO ck_out 5.5ns;
#################################################
*Problem*- some constraints are ignored- from the place and route
report:
WARNING:Timing:3223 - Timing constraint TS_output_ck_to_data =
MAXDELAY FROM TIMEGRP "ck_out" TO TIMEGRP "d_out" 2.6
ns; ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_ext_ck_to_ckout = MAXDELAY
FROM TIMEGRP "CLK_120MHZ_P" TO TIMEGRP "ck_out"
5.5 ns; ignored during timing analysis.
Q1/ Why are those constraints ignored?
Q2/ Even more puzzling to me, why is the external clock to data
constraint heeded while the external clock to clock out is ignored?
Q3/ Am I approaching the problem in a sensible way?
I've put a .zip of the two Verilog files (one's just the IO buffers)
and the .ucf file here:
http://www.humyo.com/F/6619-179262397
All comments welcome.
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.
Article: 134531"andersod2" <thechrisanderson@gmail.com> wrote in message news:91c3827f-cc64-485d-894d-7438de4673a4@b38g2000prf.googlegroups.com... > > I just inserted an inferred ram module into my code, and all of a > sudden it takes forever to synthesize...I only inferred one > ramblock...is there anything I can do to get it down to a reasonable > time? I have a lot of warnings, but still...I went from a few seconds > to synth now taking minutes.....?? > Most likely you're not quite following the template (although you think you are) and what is getting synthesized has to get implemented in logic cells rather than internal memory. Another cause than cause logic instead of internal memory to be used that I've seen is that even though my code exactly followed the template I had to manually add an attribute to the read address signal to prevent the signal from getting changed. Whatever it was doing optimized it into some form that the synthesis tool thought it needed logic cells and couldn't use internal memory. Since adding (or not adding) an attribute to a signal does absolutely nothing to the function of the code, it was just something that needed to be done. I opened a case with the tool supplier, not fixed yet, possibly soon. KJArticle: 134532
On Aug 15, 4:32=A0pm, Peter Alfke <pe...@xilinx.com> wrote: > On Aug 15, 1:13=A0pm, stewa...@gmail.com wrote: > > > > > I want to implement 1280x1024but cannot synthesize an 108MHz pixel > > block for the timing. =A0I would prefer to use a 100 MHz (generated fro= m > > 200) but can also make a 104 or 112 Mhz. > > > Normal 1280x1024 timing: > > Horizontal > > Resolution pixels: 1280 > > Front porch pixels: 48 > > Sync pulse pixels: 112 > > Back porch pixel: 248 > > Veritcle > > Resolution lines: 1024 > > Front porch lines: 1 > > Sync pulse lines: 3 > > Back porch lines: 38 > > > Has anyone had any experience altering the porch/sync lengths and > > pixel clock to keep 60Hz that will sync to an LCD monitor? > > > Thanks! > > What's your real question? What's the FPGA device? > With a Virtex DCM you can generate all sorts of frequencies around 104 > MHz with ~0.2 MHz granularity. > Peter Alfke Using a Virtex 4, but my oscillator is a 200 MHz differential source. Coregen will not let me generate a DCM chain to create the 108MHz from 200MHz (the M and D for CLKFX are to high). My real problem is that I want to output 1280x1024 @60Hz DVI timing with a TFP410 using a non-standard clock (not using 108MHz). I am wondering what I would set my front porch, back porch and sync pulse at with a 100MHz, 104MHz or 112 MHz pixel clock, with 100MHz being perfered for 1280x1024@60Hz. ThanksArticle: 134533
"tersono" <ethel.thefrog@ntlworld.com> wrote in message news:equda41r55sn5pta3e58uikts03gku5lae@4ax.com... >A system with a 16-wide input bus, clocked (negative edge) into a > 16-wide register. > > (Actually a sub-set of a real system.) > > The system clock input is balanced; it is converted to single ended > and fed to a clock buffer to clock the register. > > The system outputs are > > 1/ the register output > 2/ the single ended clock drive > > I want to constrain the register output so that it changes less than > 2.6ns after the fall of the clock output- a constraint between two > outputs. > Dear Ethel Frogface, Use the IOB's DDR flipflops to output the clock. Use a '0' and a '1' on the data inputs to the two DDR registers. Also, use the IOBs' flipflops for the register you've made. Then the clock and the register outputs all change at the same time. HTH, Syms. p.s. Philip F. claims to have invented this way of getting clocks out of FPGAs. He always bleats on at me if I don't mention that! ;-)Article: 134534
On Aug 16, 11:22=A0am, stewa...@gmail.com wrote: > On Aug 15, 4:32=A0pm, Peter Alfke <pe...@xilinx.com> wrote: > > > > > On Aug 15, 1:13=A0pm, stewa...@gmail.com wrote: > > > > I want to implement 1280x1024but cannot synthesize an 108MHz pixel > > > block for the timing. =A0I would prefer to use a 100 MHz (generated f= rom > > > 200) but can also make a 104 or 112 Mhz. > > > > Normal 1280x1024 timing: > > > Horizontal > > > Resolution pixels: 1280 > > > Front porch pixels: 48 > > > Sync pulse pixels: 112 > > > Back porch pixel: 248 > > > Veritcle > > > Resolution lines: 1024 > > > Front porch lines: 1 > > > Sync pulse lines: 3 > > > Back porch lines: 38 > > > > Has anyone had any experience altering the porch/sync lengths and > > > pixel clock to keep 60Hz that will sync to an LCD monitor? > > > > Thanks! > > > What's your real question? What's the FPGA device? > > With a Virtex DCM you can generate all sorts of frequencies around 104 > > MHz with ~0.2 MHz granularity. > > Peter Alfke > > Using a Virtex 4, but my oscillator is a 200 MHz differential source. > Coregen will not let me generate a DCM chain to create the 108MHz from > 200MHz (the M and D for CLKFX are to high). > > My real problem is that I want to output 1280x1024 @60Hz DVI timing > with a TFP410 using a non-standard clock (not using 108MHz). =A0I am > wondering what I would set my front porch, back porch and sync pulse > at with a 100MHz, 104MHz or 112 MHz pixel clock, with 100MHz being > perfered for 1280x1024@60Hz. > Thanks If you want to, you can generate 108 MHz out of 200 MHz incoming, since the FCM has a built-in divide-by 2 prescaler that changes the DCM input to 100 MHz, and then you multiply by 27 and divide by 25, and you have your 108 MHz. Peter AlfkeArticle: 134535
On Aug 16, 3:13 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "tersono" <ethel.thef...@ntlworld.com> wrote in message > > news:equda41r55sn5pta3e58uikts03gku5lae@4ax.com... > > >A system with a 16-wide input bus, clocked (negative edge) into a > > 16-wide register. > > > (Actually a sub-set of a real system.) > > > The system clock input is balanced; it is converted to single ended > > and fed to a clock buffer to clock the register. > > > The system outputs are > > > 1/ the register output > > 2/ the single ended clock drive > > > I want to constrain the register output so that it changes less than > > 2.6ns after the fall of the clock output- a constraint between two > > outputs. > > Dear Ethel Frogface, > Use the IOB's DDR flipflops to output the clock. Use a '0' and a '1' on the > data inputs to the two DDR registers. Also, use the IOBs' flipflops for the > register you've made. Then the clock and the register outputs all change at > the same time. > HTH, Syms. > > p.s. Philip F. claims to have invented this way of getting clocks out of > FPGAs. He always bleats on at me if I don't mention that! ;-) Philip F's claims aside, is this really a useful way of propagating the clock? With both the output clock and the registered data coming from IOB FFs, won't there be a race condition? I guess the receiving chip can clock the data on the other edge of the clock, but typically when clocking on board, the data has a minimum hold time sufficient to reliably clock the data into the receiving device. I don't think this method will provide the required hold time. I have not used the DLLs before, but my impression was that they could be used to clock the data out on a clock which is delay locked to the actual board clock. The board clock output is feed back to an input pin and run through the DLL. The DLL aligns it to provide the data output at the time you require it. This should provide a sufficient delay of the data so that a positive hold time can be provided. RickArticle: 134536
static as in global file scope was what a i was talking about. but that doesn't exist in veriolg, so it looks like i'll have to keep my simulation modules, outside of the source for the module to be simulated. Cant recall ever being introduced to the first definition you've mentioned. Thanks :) On Aug 16, 5:44=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sat, 16 Aug 2008 01:46:04 -0700 (PDT), laserbeak43 wrote: > >oh, and for that matter, what's the verilog equivalent of the Ansi C > >"static" keyword? > > Which meaning of "static"? > > static =3D lexically local variable of a function, > which therefore is in fact a global variable whose > name is visible only within the function scope: > all local variables of Verilog-95 tasks and functions > have this behaviour. =A0Only by declaring your Verilog > tasks or functions to be "automatic" do you get > argument and local variables created dynamically > per call. > > static =3D global (file-scope) declaration that is > not published outside the file: no such thing in > Verilog. =A0Everything is public and the names get > resolved at elaboration time. =A0In particular, > module names all get thrown into one common namespace > (although the library/configuration machinery of > Verilog-2001 somewhat messes with that idea); and > there are no other top-level declarations apart from > modules. > > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 134537
On Aug 16, 5:56=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sat, 16 Aug 2008 01:43:19 -0700 (PDT), laserbeak43 > > <laserbea...@gmail.com> wrote: > >Hi, > >i have some verilog code that i want to keep for future use as a part > >of a library. > >I have created the module and am working on the stimulus. if i were to > >put the > >module and stimulus in the same file, would this cause problems in the > >future if > >i try to load the module from the file? > > I don't know what you mean by "load the module from the file". > If you put a design module and a testbench module in the same > file, then whenever the compiler processes that file it will > compile both modules. ok, That makes sense. =2E... > Give these two files to the compiler and it will find > three modules: the_real_top_level, design, and > design_tb. =A0Two of those modules - the_real_top_level > and design_tb - are not instantiated by other modules. > Consequently the following hierarchy will be constructed: > > [top of simulation] > =A0 | > =A0 +--- unnamed instance of the_real_top_level > =A0 | =A0 =A0 =A0 | > =A0 | =A0 =A0 =A0 +--- instance "design_2" of design > =A0 | > =A0 +--- unnamed instance of design_tb > =A0 =A0 =A0 =A0 =A0 | > =A0 =A0 =A0 =A0 =A0 +--- instance "design_instance" of design > > Is that a problem for you? No, I think I've got that part down, ISE seems to make that part understandable along with the book i'm reading. > Some tools allow you to compile files individually, > putting the compiled modules into a "library" in some > tool-dependent way; you can then choose which top-level > module(s) in that library you wish to simulate, and the > tool will construct the hierarchy from that. =A0So, for > example, in ModelSim I might do this: > > =A0 vlog F1.v ; # compile file F1 > =A0 vlog F2.v ; # compile file F2 > =A0 vsim the_real_top_level > > and that will build this hierarchy: > > [top of simulation] > =A0 | > =A0 +--- unnamed instance of the_real_top_level > =A0 =A0 =A0 =A0 =A0 | > =A0 =A0 =A0 =A0 =A0 +--- instance "design_2" of design And this would be how you'd create a new library? Is there any good documentation on this process? > Finally, you may be giving yourself problems with synthesis > because (I assume) at some stage you want to synthesise the > design, but not the testbench module. > > The conclusion from all of this should surely be obvious: > ONE MODULE PER FILE is almost always the sensible way > to organise your Verilog source code. Ok, Gotcha! Thanks for that detailed explanation! There couldn't be a single doubt in my mind about it now!! Thanks MalikArticle: 134538
On Aug 16, 7:36=A0am, andersod2 <thechrisander...@gmail.com> wrote: > Very informative, johnathan...thanks for that. > > laserbeak...is there some compiler directives you could use analagous > to C's #ifdef's for excluding code in a particular build? =A0I would > look this up, but I don't even have a verilog book :P....just learning > from the net... ahh, very good suggestion andersod2 :) and thanks for giving me clues to use to find answers jonathan. what a helpful thread!! Thanks, MalikArticle: 134539
On Aug 16, 3:19=A0pm, rickman <gnu...@gmail.com> wrote: > On Aug 16, 3:13 pm, "Symon" <symon_bre...@hotmail.com> wrote: > > Dear Ethel Frogface, > > Use the IOB's DDR flipflops to output the clock. Use a '0' and a '1' on= the > > data inputs to the two DDR registers. Also, use the IOBs' flipflops for= the > > register you've made. Then the clock and the register outputs all chang= e at > > the same time. > > HTH, Syms. > > > p.s. Philip F. claims to have invented this way of getting clocks out o= f > > FPGAs. He always bleats on at me if I don't mention that! ;-) > > Philip F's claims aside, is this really a useful way of propagating > the clock? =A0With both the output clock and the registered data coming > from IOB FFs, won't there be a race condition? =A0I guess the receiving > chip can clock the data on the other edge of the clock, but typically > when clocking on board, the data has a minimum hold time sufficient to > reliably clock the data into the receiving device. =A0I don't think this > method will provide the required hold time. > > I have not used the DLLs before, but my impression was that they could > be used to clock the data out on a clock which is delay locked to the > actual board clock. =A0The board clock output is feed back to an input > pin and run through the DLL. =A0The DLL aligns it to provide the data > output at the time you require it. =A0This should provide a sufficient > delay of the data so that a positive hold time can be provided. Howdy Rick, While you could certainly do that, most designs seem to have converged on using the most simple transmit structure possible (typically using I/O flops, often DDR) and do whatever is necessary on the RX side to get the correct setup and hold times. In this case, one would either use the DLL/DCM on the receiving FPGA in source sync mode, or possibly use the BUFR if using a V4 or V5. Have fun, MarcArticle: 134540
On Aug 16, 7:11 pm, Marc Randolph <mr...@my-deja.com> wrote: > On Aug 16, 3:19 pm, rickman <gnu...@gmail.com> wrote: > > > > > On Aug 16, 3:13 pm, "Symon" <symon_bre...@hotmail.com> wrote: > > > Dear Ethel Frogface, > > > Use the IOB's DDR flipflops to output the clock. Use a '0' and a '1' on the > > > data inputs to the two DDR registers. Also, use the IOBs' flipflops for the > > > register you've made. Then the clock and the register outputs all change at > > > the same time. > > > HTH, Syms. > > > > p.s. Philip F. claims to have invented this way of getting clocks out of > > > FPGAs. He always bleats on at me if I don't mention that! ;-) > > > Philip F's claims aside, is this really a useful way of propagating > > the clock? With both the output clock and the registered data coming > > from IOB FFs, won't there be a race condition? I guess the receiving > > chip can clock the data on the other edge of the clock, but typically > > when clocking on board, the data has a minimum hold time sufficient to > > reliably clock the data into the receiving device. I don't think this > > method will provide the required hold time. > > > I have not used the DLLs before, but my impression was that they could > > be used to clock the data out on a clock which is delay locked to the > > actual board clock. The board clock output is feed back to an input > > pin and run through the DLL. The DLL aligns it to provide the data > > output at the time you require it. This should provide a sufficient > > delay of the data so that a positive hold time can be provided. > > Howdy Rick, > > While you could certainly do that, most designs seem to have converged > on using the most simple transmit structure possible (typically using > I/O flops, often DDR) and do whatever is necessary on the RX side to > get the correct setup and hold times. In this case, one would either > use the DLL/DCM on the receiving FPGA in source sync mode, or possibly > use the BUFR if using a V4 or V5. And what if the receiving side is not an FPGA??? The OP asked for a maximum clock out to register out of 2.6 ns. He did not provide a minimum (as would be needed to spec a hold time). So I can't say that your approach won't work. Since he seems to be working with a receiver with specific timing constraints, using the DLL to provide an appropriate timing relation between the clock out and the register out would be a good solution. But to answer the OP's original question, the software is not designed to provide timing controls between arbitrary points in the system. It is designed to constrain timing delays from clocks to corresponding outputs, inputs to corresponding outputs and inputs to corresponding register clocks. I say "corresponding" because it can only work with path delays that it understands. The tools are not designed to control the delays in parallel paths to match them within a spec as you are asking it to do. Mainly this is not practical because the timing delays are spec'd as maximums, but typically not minimums. So the timing of the clock route can't be made to not be faster than a given amount which is what you would have to do to get your maximum delay to the register output. That is why a feedback path is needed. Once you feed the clock output back into the FPGA, it can be used as a reference to clock the output register and meet your timing. RickArticle: 134541
Kolja, Sorry it was late and I wasn't thinking right.... -Webpack ISE (9.x?) -Verilog -Spartan3a -1 ram block = 18k bits partitioned at 72x256 (legal partition according to docs...well some of them at least) KJ, Thanks a lot...I think you may be right because I'm getting a lot of latch warnings, but didn't understand why. I am using inferred ram, which the docs say will work the same as an explicit template instantiation if I just use the typical "reg [w:x] mem[y:z];" notation...do you think using a template is always the better way to go? If this isn't evidence for that, then I don't know what is because I'm not doing anything special. In fact I lifted the code for my mem module from a verilog site...if there's a a way I can guarantee that the inferred ram will be put in a block I would very much like to know as I find it much easier to work with than the template. Is that a constraints thing? thanks again for your helpArticle: 134542
On Aug 17, 3:45 am, andersod2 <thechrisander...@gmail.com> wrote: > Kolja, > Sorry it was late and I wasn't thinking right.... > -Webpack ISE (9.x?) > -Verilog > -Spartan3a > -1 ram block = 18k bits partitioned at 72x256 (legal partition > according to docs...well some of them at least) > > KJ, > Thanks a lot...I think you may be right because I'm getting a lot of > latch warnings, but didn't understand why. I am using inferred ram, > which the docs say will work the same as an explicit template > instantiation if I just use the typical "reg [w:x] mem[y:z];" > notation...do you think using a template is always the better way to > go? If this isn't evidence for that, then I don't know what is > because I'm not doing anything special. In fact I lifted the code for > my mem module from a verilog site...if there's a a way I can guarantee > that the inferred ram will be put in a block I would very much like to > know as I find it much easier to work with than the template. Is that > a constraints thing? > thanks again for your help There is RAM and there is RAM. If you are inferring async RAM in an FPGA, it is likely that this does not map to any existing feature in the device. Most FPGAs use synchronous block RAM which requires a registered model. Rather than getting generic RAM code from a VHDL site, check the site for your FPGA supplier for code to infer a RAM that works for their parts. Or at very least, check for a model from the site for the synthesis tool you are using. RickArticle: 134543
Hi all, I am new to multicore platforms on FPGA's. I was wondering if there is some good information somewhere on the net where I can read on building multicore systems and installing an OS on an FPGA target board for this multicore system (Digilent Virtex II-Pro,...). (I am looking for theoretical and practical tutorials like in EDK,...) The multicore system I would like to build is around microblaze or PowerPC cores but other references are good. Kind regards and thanks for your help. Vince SertiArticle: 134544
"rickman" <gnuarm@gmail.com> wrote in message news:d5d7b8d8-0dec-48c3-a26d-4cf644d35327@p25g2000hsf.googlegroups.com... > On Aug 16, 3:13 pm, "Symon" <symon_bre...@hotmail.com> wrote: >> "tersono" <ethel.thef...@ntlworld.com> wrote in message >> >> news:equda41r55sn5pta3e58uikts03gku5lae@4ax.com... >> >> >> Dear Ethel Frogface, >> Use the IOB's DDR flipflops to output the clock. Use a '0' and a '1' on >> the >> data inputs to the two DDR registers. Also, use the IOBs' flipflops for >> the >> register you've made. Then the clock and the register outputs all change >> at >> the same time. >> HTH, Syms. >> >> p.s. Philip F. claims to have invented this way of getting clocks out of >> FPGAs. He always bleats on at me if I don't mention that! ;-) > > Philip F's claims aside, is this really a useful way of propagating > the clock? Yes. > With both the output clock and the registered data coming > from IOB FFs, won't there be a race condition? No. Because... > I guess the receiving > chip can clock the data on the other edge of the clock, Good idea! ;-) > but typically > when clocking on board, the data has a minimum hold time sufficient to > reliably clock the data into the receiving device. I don't think this > method will provide the required hold time. > OK, if you're set on using the 'same' edge instead of the 'other' one, then if you're driving another FPGA, the inputs have special programmable delays built in to give the appearance of zero hold time for the IOB input FFs. For devices without zero hold time, read on below. > > I have not used the DLLs before, but my impression was that they could > be used to clock the data out on a clock which is delay locked to the > actual board clock. The board clock output is feed back to an input > pin and run through the DLL. The DLL aligns it to provide the data > output at the time you require it. This should provide a sufficient > delay of the data so that a positive hold time can be provided. > > Rick Yep, that'll work provided the frequency of operation is within the DCM's range. If the OP is worried about a 2.6ns delay, I guess the DCM will work and I think the solution you suggest will work nicely. Even without feedback, it's easy to use a DCM to generate a clock to drive the DDR-clock-output-thingy suggested above to provide adjustable phase difference between clock and data outputs. HTH., Syms.Article: 134545
When I was inferring dual port BRAM with same data bus sizes, I was able to see the contents of BRAM memory locations in ISE simulator. Now I'm instatieting (is this word correctly written?) dual port BRAM with port A 8bits and port B 1bit wide data bus, and I cant get ISE sim to show the memory contents. Is it not possible or am I doing something wrong?Article: 134546
On Aug 17, 1:19=A0am, rickman <gnu...@gmail.com> wrote: > On Aug 17, 3:45 am, andersod2 <thechrisander...@gmail.com> wrote: > > > > > Kolja, > > Sorry it was late and I wasn't thinking right.... > > -Webpack ISE (9.x?) > > -Verilog > > -Spartan3a > > -1 ram block =3D 18k bits partitioned at 72x256 (legal partition > > according to docs...well some of them at least) > > > KJ, > > Thanks a lot...I think you may be right because I'm getting a lot of > > latch warnings, but didn't understand why. =A0I am using inferred ram, > > which the docs say will work the same as an explicit template > > instantiation if I just use the typical "reg [w:x] mem[y:z];" > > notation...do you think using a template is always the better way to > > go? =A0If this isn't evidence for that, then I don't know what is > > because I'm not doing anything special. =A0In fact I lifted the code fo= r > > my mem module from a verilog site...if there's a a way I can guarantee > > that the inferred ram will be put in a block I would very much like to > > know as I find it much easier to work with than the template. =A0Is tha= t > > a constraints thing? > > thanks again for your help > > There is RAM and there is RAM. =A0If you are inferring async RAM in an > FPGA, it is likely that this does not map to any existing feature in > the device. =A0Most FPGAs use synchronous block RAM which requires a > registered model. =A0Rather than getting generic RAM code from a VHDL > site, check the site for your FPGA supplier for code to infer a RAM > that works for their parts. =A0Or at very least, check for a model from > the site for the synthesis tool you are using. > > Rick All Xilinx BlockRAMs are synchronous, they need a clock not only for writing, but also for reading (the register the incoming address and control information with a clock edge). In our documentation we often say: "nothing happens without a clock". Traditional RAMs may not have that requirement, and the distributed (LUT-) RAM can read data without the use of a clock. Peter Alfke, XilinxArticle: 134547
Check out http://portal.itauth.com/2007/11/07/learning-vhdl-spartan3-xc3s20= 0-fpga#comment-144. In this blog entry, Vlas solve the problem by setting an iMPACT option. He states ' "Use HIGHZ instead of BYPASS" by going to Edit -> Preferences... -> iMPACT -> Configuration Preferences.' On Jul 31, 11:09=A0pm, skyworld <chenyong20...@gmail.com> wrote: > Hi, > > in many times when I program Xilixn FPGA with parallel cable, I always > get message "program failed". In some case I populated several > capacitors to the pins of download cable and it works. But many times > I still failed. Did anybody here met this problem? Is there any > comments on this?Article: 134548
On Aug 17, 9:17 am, aleksa <aleks...@gmail.com> wrote: > When I was inferring dual port BRAM with same data bus sizes, > I was able to see the contents of BRAM memory locations in ISE > simulator. > > Now I'm instatieting (is this word correctly written?) > dual port BRAM with port A 8bits and port B 1bit wide data bus, > and I cant get ISE sim to show the memory contents. > > Is it not possible or am I doing something wrong? When you instantiate a vendor supplied component, you are using their library element. Often this is just a black box that you can't see into. If you want to be able to view the contents of the BRAM, you need to infer it instead of instantiating it. Then the HDL code will be fully visible. BTW, the most efficient simulation uses integers for the actual memory block rather than std_logic_vector. RickArticle: 134549
Hi, This has already been resolved for me, I'm simply sharing the experience in case it is of help to anybody. After a rather agonizing week of blind speculative troubleshooting, I managed to understand exactly what took place during my tests. Bottom line: Xilinx 9.2i tools are =91buggy=92, avoid using at all cost! 9.1, on the other hand, are much more stable. My dillemma, however, is to be able to use ISE in conjunction with BOTH EDK and SysGen. 9.1 doesn=92t support SysGen---please correct me if I'm wrong. For the time being, I have both installed and I=92ll be alternating back-and-forth between them with the ever daunting task of changing Windows Xilinx=92 Environment Variables each hop. Anybody knows of a way to script this on Windows presuming it can be done. Now, on the =91buggy=92 9.2 tools issue, I observed the following: -ISE9.2 doesn=92t spot certain errors when compared to 9.1 e.g. in ucf the original source code had the async interrupt constraint applied on the VHDL signal instead of the corresponding I/O pin. Not sure if this didn=92t use to be allowed and now is. UCF snippet: # Ignore this gpio bit as it is an async interrupt in this example NET "gpio_out_s<4>" TIG; I changed this to: NET "gpio_out<4>" TIG; -there is definitely something wrong with the IMPACT executable in the 9.2 version. I tried programming the PROM with a pregenerated .mcs file in the reference design but it didn=92t work. This was observed under ISE9.2.04 & EDK9.2.02 (both latest, 0x denoting sp x); however, it did work with the ISE9.2.03 & EDK9.2 combination, I mean just for the precompiled .mcs. Regards, -Manny
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