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I'll try and help by pointing you at the programs that are needed, but I wasted an 2 hours today, unsuccessfully putting an example together for you. The answer is probably somewhere in the documentation, but I couldn't find it. UPDATE: I couldn't believe that I was posting a reply without the actual answer. I went back and beat on it a lot more, and have something like an answer. I hope it helps. On 06 Sep 2000 13:34:49 -0600, Erik Brunvand <elb@telemark.cs.utah.edu> wrote: > >Hi - > >I've been trying to use FPGA_Express v3.1 with Powerview v6.1 on a >Solaris machine and am running into an annoying problem. So my test environment was ePD 1.1 , and M3.1i , and FPGA express 3.4 , on a pentium, running Windows 2000, but other than that, identical to your situation. >Here's the setup: I have a schematic in Viewdraw that contains some >components out of the xc4000x library and a number of symbols, each of >which represents some VHDL code. I'd like to take one of those pieces >of VHDL, run it through FPGA_Express, and then simulate again using >the synthesized circuit instead of the VHDL code. Basically, I want to >incrementally replace VHDL code with circuits synthesized by >FPGA_Express. Eventually, I'll be generating an EDIF file of the whole >circuit (that contains some Xilinx components directly, and some >synthesized pieces) and running it through Xilinx place and route. So the goal I can help you with is to simulate (with viewsim) a piece of vhdl, post synthesis. Your other goal of then getting a netlist of this simulatable design into the Xilinx tools is not achievable. I'll explain later why. So I created a test design in verilog and pushed it through FE and got an EDIF file. I created a dummy schematic project with the hope of getting a schematic of the synthesized verilog. >Here's the problem: When I run a design through FPGA_express with >Xilinx XC4010XL as a target, the tool ONLY wants to generate an xnf >file! What I need is an EDIF file! (actually, what I need is a wir >file, but Powerview can read an EDIF file and turn it into a wir >file). right. >So, a couple questions: >1 - Is there a way to force FPGA_express v3.1 to produce an EDIF file >instead of an XNF file if your target is a Xilinx chip? No. But it doesn't matter. >2 - Is there something else that I'm just being stupid and overlooking >about this process? You aren't stupid (at least not on this topic). The documentation just sucks. Big time. >Thanks! > -Erik So a solution is coming, but let's review the difference in our setups. I believe that none of these differences are significant to your problem, and the solution I am presenting, but I list it anyway, just in case. (recommend mono spaced font here) Me You PC-Pentium Sun-Sparc W2000 Solaris EPD 1.1 Powerview 6.1 Viewdraw 7.7.0 Viewdraw x.xx FE 3.4 FE 3.1 FE output EDIF FE output XNF Target 4013XLA Target 4010XL Xilinx M3.1i Xilinx Mx.1 Verilog -> SCH VHDL -> SCH Line sep CRLF LF So here are the steps: Directories in the viewdraw.ini file : DIR [pw] . DIR [rm] G:\Xilinx\viewlog\data\xc4000x (xc4000x) DIR [r] G:\Xilinx\viewlog\data\logiblox (logiblox) DIR [rm] G:\Xilinx\viewlog\data\simprims (simprims) DIR [rm] G:\Xilinx\viewlog\data\builtin (builtin) DIR [rm] G:\Xilinx\viewlog\data\xbuiltin (xbuiltin) Push your HDL through FE, remember to set the option to disable adding I/O pads to the design. Run NGDBUILD, with a command line like : ngdbuild -p XC4013XLA-07-PQ208 -u test1.xnf test1.ngd This translates your source to NGD. (in my case, it was test1.edf, but the result is still .NGD Translate NGD to EDIF : ngd2edif -w -n -v viewlog test1.ngd test1 This creates an EDIF file, called test1.edn. The logic in this file is all made up of SIMPRIM primitives. This is why we wont be able to netlist the schematic at the end, for place and route. SIMPRIM things can only be used for simulation. (In my first draft of this message, I had a tirade about how stupid it is that ngd2edif creates edif that cant be processed by ngdbuild (how hard would it be to have ngdbuild recognize simprim primitives), or since there is a perfectly fine library of basic functions in xc4000x library, use these instead of simprims. I went on to comment that this had been pointed out several times to people at Xilinx, and the response was it was easier for them to maintain it as a separate library. I finished up with a comment about how nice it would be if Xilinx's developers had to use their programs to get their job done. In the end, I decided that this was not the place for that tirade, and I removed it.) Now we need to translate the EDIF to a WIR file. Run the edif netlist reader (edifneti) on the edn file, (run it in your project directory, the one with sch/sym/wir subdirectories) Something like : edifneti test1.edn This should result in a file test1.1 in your WIR directory Now convert this to a schematic: (run it in your project directory, the one with sch/sym/wir subdirectories) viewgen test1 test1 -makesym (you may not want to create a symbol, since you already have one for the VHDL code) There is probably some more screwing around to be done with command line options to edifneti and viewgen, to control number of schematic pages creation on a top level symbol using EDIF rename combining nets into busses library alias selection matching net names on the created schematic to pins on the symbols Sheet size getting VSM to netlist this correctly. So that is at least a guide to your simulation problem. On to compilation. I believe that at the moment you have a SCH top level with VHDL modules linked in by a symbol, and some real schematic design. This is compilable. You process each VHDL module separately, resulting in .XNF files, and when you netlist your top level schematic, the resultant file has calls to the external XNF files. Ngdbuild, given the schematic netlist then pulls in the XNF files to build the complete chip. When you netlist the schematic, one of the settings is a level command that stops the netlister from digging down to simulation primitives. It stops at the next level up, which are the gate primitives that ngdbuild will be expecting, plus the references to external XNF modules. As explained far above, the schematics created through FE -> ngdbuild -> ngd2edif -> edifneti -> viewgen do not have the gate primitives that ngdbuild wants. So no matter what you do, you still need the XNF files. But if you put a gate level simulation model below the VHDL place holder symbol, it will get netlisted too, which will blow up ngdbuild. But you need this to happen for simulation (different netlister, VSM). So here's an idea: On your VHDL symbols that have simulation model under them, as described above, add an attribute "LEVEL=XILINX". This is the flag to the netlister (for P&R, not VSM) not to dig any deeper. This will let you P&R with the external XNF files, but also run VSM and simulate your design. (another tirade/rant was here, but it go deleted too) Philip Freidin Philip Freidin Mindspring that acquired Earthlink that acquired Netcom has decided to kill off all Shell accounts, including mine. My new primary email address is philip@fliptronics.com I'm sure the inconvenience to you will be less than it is for me.Article: 25401
> Because that's the only way that they get lower pricing from Xilinx - it's > what Xilinx want them to do. --This is true. The design registration process guarantees that Xilinx will sell to the disty owning the registration at a lower price, thus allowing that particular disty to undercut the other disties and get the sale (unless the buyer is playing games). > If the rep in my area did this, the disties run would screaming to Xilinx, > no rep should ever do this, after all the rep can't sell the parts, only the > disties. --The rep in your area has no balls. If the rep has reason(s) to withhold information from the disties, then (s)he should do it, unless of course (s)he is YOUR rep. My reps have always honored my requests to withhold information. I give them reasons to, and they do it. I've seen disties run to the rep screaming, after the design cycle is over, that they helped me throughout the design process, and that without them, I couldn't have pulled it off. The rep(s) have all seen this before, knowing that sometimes the disties claim they did a lot of support work when in fact they didn't. In the final analysis, it all boils down to money. The disties want to make money on every deal, support or no support. The reps will always jump at a chance to make MORE money if you give them a good enough reason. Andy's request to keep the disties out of the picture so that he doesn't get bothered by them would be honored by my reps. > What's the point of asking the rep to ask the disty? ..and if the rep sells > direct from factory, the disty should immediately complain to Xilinx. --I've seen disties complain and lose. Xilinx wants to make money and sometimes that takes disty involvement. However, if the disties did not help me one bit or one byte, and the local Xilinx rep can make more money if (s)he leaves the disties out of the picture, I guarantee you again that the disties will lose. The disties basic recourse is to escalate the matter above the local rep, and they better have a damn good story. But from my experience, all it takes is the higher authority making a few phone calls to find out the several perpectives, including mine! The final result may be losing this particular sale and possible future ones, since they P.O.ed the rep. > Better just to tell the disty to leave his powerpoint slides at home. --Some disties can't talk to engineers without a PowerPoint presentation. They just aren't technical enough to pull it off. Just start asking hard questions, and they'll say "I'll get back to you on that." > Use the design registration as a carrot on a stick to wave in front of the > disty.....no support, no registration. --I agree with you here 100%. I bet that if Andy, the original poster, had a darn good Xilinx specific disty FAE, he wouldn't have the problem he is having. His problem (my opinion) is that the disties are asking him a lot of questions, contributing nothing to his cause, wasting his time, and they are still getting the registration! Therefore, what they're doing works for them. -Simon Ramirez, Consultant Synchronous Design, Inc.Article: 25402
Do a DG Nova 16 bit CPU. The Nova was able to fit on a single board in 1969, surely it can fit in a 4005. The Nova's instruction set requires almost no decoding, it has a fixed width 16 bit instruction and a tiny number of instructions. The instruction set is very simple, load, store, jump, and a single type of execute instruction called and ALC which combines a simple operation (add,sub, mov, neg, and, or, xor, com), with a carry in select (0,1,Carry,!Carry), a shift (left 1, right 1, no shift and byte swap), and a skip (noskip, always skip, skip on zero, skip on not zero, skip on carry 1, skip on carry 0, skip on neg, skip on pos). Tom Kerrigan wrote: > > I'm in a senior project class at the University of Colorado. My group has > opted to design a general purpose CPU, and we have easy access to 4005s (and > some 4010s) and the associated Xilinx tools. > > My professor told us that our CPU should be 8-bit, with ~20 instructions, > and that such a design would take 3 or 4 FPGAs. > > With that in mind, I just visited this web page, and was shocked: > http://www.io.com/~guccione/HW_list.html > > One guy says he fit a 32-bit RISC design (among other things) on a single > 4010. Another guy says he made a 16-bit RISC design that only takes up 75% > of a 4005. > > I'm worried about doing a 16-bit design because my professor thinks the > project would be doomed to fail. But now I'm not so sure anymore. Does > anyone have any comments or suggestions about this stuff? > > Please let me know (via e-mail) if you post a reply. Sometimes my news > server is flakey. > > Thanks, > Tom KerriganArticle: 25403
Hi Everyone! I'm having a problem in a fully synchronous design in a XILINX XC95108-10 CPLD using the schematic entry. All Registers in the design are driven by one clock over GCK1. The problems are spurious errors which depended on the existence of test connections from the inner circuit connections to a pad. With the connections it workes, without not. Using the timing simulation I have narrowed down the problem to a hold violation on some of the D-FF. The simulation shows that in a simple shift register structure containing two D-FF, the second one will not take the right value, if the second one changes its output. It seems, the clock of second D-FF is too late regarding the change of the data at the output of the first D-FF, even if both D-FF are clocked by the same single via GCK1. From my point of view the same situation is given in each synchronous counter, ands that makes me a bit scary. I'm not sure how to handle this situation and have the following questions: - In the beginning this design was not completely synchronous. After the first appearance of these problems I changed it to a complete synchronous one, but as it seems, the situation got worse. Is it better to do such a design not completely in synchronous logic? - Is it possible to split up the clock net? One reason for the problems may be a high load on the clock net GCK1. Generally I would also like to know if there is a systematic way to deal with such problems or to prevent their appearance. Thanks for any answer, Thomas FalkArticle: 25404
On Thu, 7 Sep 2000 17:05:10 +0200, Peter Desmet <peter.desmet@barco.com> wrote: >I hadn't changed any instantiation names in vhdl-code, so that wasn't >actually the problem. >What was apparently wrong was that the constraint when using an xnf file >looked something like > INST level1_level2_regname_reg TNM=group1; >whereas for the edif-file the constraint needs to look like: > INST level1/level2/regname_reg TNM = group1; > >I found this out when running the design (nearly) constraintless, letting >the router stop after mapping, and then defining my constraints using the >built-in Constraints Editor. > I think this has a different reason. FPGA express does now keep the hierarchy and does not flat the design by default. So, if you flatten down the design (option -eliminate to the create_chip command) you might get your old signal names back. I have to use the -eliminate option to get the I/O FFs used. I don't know if I'm doing something fundamentally wrong, but this was the only solution I could find after my design failed its I/O timing constraints with fexp 3.4. chm. -- cmautner@ - Christian Mautner mail.com - Vienna/Austria/EuropeArticle: 25405
hey, why virtex chips are rectangular and not square --ERIKA Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25406
Micheal, We have an ABEL tutorial on our Support webpage. You can accesss this from Xilinx support webpage, Software --> File Archive --> Documentation --> Tutorials. Here is the corresponding link http://support.xilinx.com/support/troubleshoot/htm_index/docs_tutorials.htm Hope this helps Vikram <br> Xilinx ApplicationsArticle: 25407
Hi CPU-Freaks, When i hear about Data General, i always must recommend the book "The soul of a new machine" from tracy kidder. It's an excellent story about motivation, and an exciting and funny reading about the people and the making of computers at Data General. The book is well known in the US and still available. The german version (Die Seele einer neuen Maschine) is a perfect translation but sold out (was rororo i expect). Happy reading... Ben Franchuk <bfranchuk@jetnet.ab.ca> schrieb in im Newsbeitrag: 39BA5D4A.2E385FCB@jetnet.ab.ca... > "B. Joshua Rosen" wrote: > > > > Do a DG Nova 16 bit CPU. The Nova was able to fit on a single board in > > 1969, surely it can fit in a 4005. The Nova's instruction set requires > > almost no decoding, it has a fixed width 16 bit instruction and a tiny > > number of instructions. The instruction set is very simple, load, store, > > jump, and a single type of execute instruction called and ALC which > > combines a simple operation (add,sub, mov, neg, and, or, xor, com), with > > a carry in select (0,1,Carry,!Carry), a shift (left 1, right 1, no shift > > and byte swap), and a skip (noskip, always skip, skip on zero, skip on > > not zero, skip on carry 1, skip on carry 0, skip on neg, skip on pos). > > > > Here is some photos of the Nova Computers ,and more information on the > instruction set. > http://www.ultranet.com/~crfriend/museum/ > Ben. > PS.I wonder how many 8008's does it take to replace the 586? > > -- > "We do not inherit our time on this planet from our parents... > We borrow it from our children." > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 25408
Because square is a special case of rectangular, and Xilinx didn't want to put them in a special case. <erika_uk@my-deja.com> wrote in message news:8pgrq7$83f$1@nnrp1.deja.com... > hey, > > why virtex chips are rectangular and not square > > --ERIKA > > > Sent via Deja.com http://www.deja.com/ > Before you buy. >Article: 25409
On Mon, 11 Sep 2000 02:02:05 +0200, "Michael Randelzhofer" <mrandelzhofer@compuserve.com> wrote: >Hi CPU-Freaks, > >When i hear about Data General, i always must recommend the book >"The soul of a new machine" from tracy kidder. > >It's an excellent story about motivation, and an exciting and funny reading >about the people >and the making of computers at Data General. > >The book is well known in the US and still available. >The german version (Die Seele einer neuen Maschine) is a perfect >translation but sold out (was rororo i expect). > >Happy reading... You're right; it's excellent. And if memory serves me, Josh Rosen's in it. Take care, Bob PerlmanArticle: 25410
Hi all,
is the Xilinx Student Edition 2.1 actually available from anywhere
or is it still on the way?
Last I heard was on 24/7/00:
Anna Acevedo wrote:
> The 2.1i Xilinx Student Edition will be available for the start of the
Fall
> semester
> You should be able to order it from www.amazon.com or www.xess.com by
> mid August.
>
> Pratip Mukherjee wrote:
>
> ? Does any body know when will the new version of Xilinx Student Edition
with
> ? Foundation 2.x be out? Since coming to know that there will be a new
version
> ? shortly, I am holding on from buying the new version for about two
months now.
> ? The wait is killing me.
> ?
> ? Pratip Mukherjee
>
> --
> *****************************
> Anna M. Acevedo
> Xilinx University Program
> 2100 Logic Drive
> San Jose, CA 95124
> PH: (408) 879-5338
> FAX: (408) 879-4780
>
> Email: anna.acevedo@xilinx.com
> http://www.xilinx.com/programs/univ.htm
> *****************************
Article: 25411In article <39B95187.93762D2E@egr.msu.edu>, Theron Hicks <hicksthe@egr.msu.edu> wrote: > Look at ICS has a couple of clock synthesizers. The easiest to use is the ICS525 You connect a crystal and apply multiplier and divisor on 17 input pins. The chip will do up to 160MHz. I got a low quantity quote from scantec of $3 a piece. CU, Kolja www.icst.com > http://www.micronetworks.com/ > > for programmable master clocks (M115 series). I heard that that part was > being dropped so it may not be available but it sounds like just what you > wanted. Note that the output levels were PECLl (Positive ECL) but there > are level translators available quite cheaply. The M115 was a full blown > oscillator and the last time I used one it went for about $175. Frequency > range was 100MHz to 1000MHz depending on model number. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25412
Right.
I was thinking of doing all the y[k] in parallel.
This will result in k instances of the circuit on your web page.
To do something like mpeg this shouldn't ne an overkill.
BTW: shouldn't it be ... sum_N(x[n]cos( ...
^
Otherwise the result is 0.
CU,
Kolja
In article <39B92A75.DA3C03A6@andraka.com>,
Ray Andraka <ray@andraka.com> wrote:
> Well, not exactly.
>
> DCT is the summation y[k]= c[k] sum_N(x[k]cos(pi*(2n+1)*k/2N))
>
> You can use distributed arithmetic, but it is a bit more complicated
than just
> setting the constants because the 'constant' is a function of k and n.
>
> kolja@prowokulta.org wrote:
> >
> > This is from Ray Andraka's web site:
> > http://www.andraka.com/distribu.htm
> >
> > Choose the right C's and you got your DCT.
> >
> > CU,
> > Kolja
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25413I loved that book. However, it described DG's work to build their 32 bit MV series intended to compete with the VAX. I think doing a MV on a small FPGA would be problematic at best as it had a huge microcode control store and lots of complex instructions. -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com "Michael Randelzhofer" <mrandelzhofer@compuserve.com> wrote in message news:39bc20ba$0$63@personalnews.de.uu.net... > Hi CPU-Freaks, > > When i hear about Data General, i always must recommend the book > "The soul of a new machine" from tracy kidder. > > It's an excellent story about motivation, and an exciting and funny reading > about the people > and the making of computers at Data General. > > The book is well known in the US and still available. > The german version (Die Seele einer neuen Maschine) is a perfect > translation but sold out (was rororo i expect). > > Happy reading... > > > > Ben Franchuk <bfranchuk@jetnet.ab.ca> schrieb in im Newsbeitrag: > 39BA5D4A.2E385FCB@jetnet.ab.ca... > > "B. Joshua Rosen" wrote: > > > > > > Do a DG Nova 16 bit CPU. The Nova was able to fit on a single board in > > > 1969, surely it can fit in a 4005. The Nova's instruction set requires > > > almost no decoding, it has a fixed width 16 bit instruction and a tiny > > > number of instructions. The instruction set is very simple, load, store, > > > jump, and a single type of execute instruction called and ALC which > > > combines a simple operation (add,sub, mov, neg, and, or, xor, com), with > > > a carry in select (0,1,Carry,!Carry), a shift (left 1, right 1, no shift > > > and byte swap), and a skip (noskip, always skip, skip on zero, skip on > > > not zero, skip on carry 1, skip on carry 0, skip on neg, skip on pos). > > > > > > > Here is some photos of the Nova Computers ,and more information on the > > instruction set. > > http://www.ultranet.com/~crfriend/museum/ > > Ben. > > PS.I wonder how many 8008's does it take to replace the 586? > > > > -- > > "We do not inherit our time on this planet from our parents... > > We borrow it from our children." > > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk > >Article: 25414
I once did a 16 bit Nova emulator using about 40 PALs and a microcode control store of 88 bits by 2k words, plus ordinary F type chips like 74F381's. On the Nova, the source and destination registers are specific bit fields, the type of operation is another bit field, and so forth. I/O operations to device code 77 octal were defined to be to the CPU itself and were used for things like halt and IO reset. Since the original Nova only understood 16 bit operations and a 15 bit memory address, life became easy. We implemented a MMU emulator using two small RAMs. I bet the whole thing would fit easily in a 4005, except possibly for the I/O pin count. If you make a Nova in a FPGA and need an assembler, I'll send you my brother's phone number. To this day he can still assemble Nova machine code in his head. -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:39BAF531.ECBB1857@polybus.com... > Do a DG Nova 16 bit CPU. The Nova was able to fit on a single board in > 1969, surely it can fit in a 4005. The Nova's instruction set requires > almost no decoding, it has a fixed width 16 bit instruction and a tiny > number of instructions. The instruction set is very simple, load, store, > jump, and a single type of execute instruction called and ALC which > combines a simple operation (add,sub, mov, neg, and, or, xor, com), with > a carry in select (0,1,Carry,!Carry), a shift (left 1, right 1, no shift > and byte swap), and a skip (noskip, always skip, skip on zero, skip on > not zero, skip on carry 1, skip on carry 0, skip on neg, skip on pos). > > Tom Kerrigan wrote: > > > > I'm in a senior project class at the University of Colorado. My group has > > opted to design a general purpose CPU, and we have easy access to 4005s (and > > some 4010s) and the associated Xilinx tools. > > > > My professor told us that our CPU should be 8-bit, with ~20 instructions, > > and that such a design would take 3 or 4 FPGAs. > > > > With that in mind, I just visited this web page, and was shocked: > > http://www.io.com/~guccione/HW_list.html > > > > One guy says he fit a 32-bit RISC design (among other things) on a single > > 4010. Another guy says he made a 16-bit RISC design that only takes up 75% > > of a 4005. > > > > I'm worried about doing a 16-bit design because my professor thinks the > > project would be doomed to fail. But now I'm not so sure anymore. Does > > anyone have any comments or suggestions about this stuff? > > > > Please let me know (via e-mail) if you post a reply. Sometimes my news > > server is flakey. > > > > Thanks, > > Tom KerriganArticle: 25415
Your right, I was. I'm the guy who said "I'm sick of nanoseconds, I'm going off to a commune in Vermont where I'll deal with no period of time shorter than a season". Josh Bob Perlman wrote: > > On Mon, 11 Sep 2000 02:02:05 +0200, "Michael Randelzhofer" > <mrandelzhofer@compuserve.com> wrote: > > >Hi CPU-Freaks, > > > >When i hear about Data General, i always must recommend the book > >"The soul of a new machine" from tracy kidder. > > > >It's an excellent story about motivation, and an exciting and funny reading > >about the people > >and the making of computers at Data General. > > > >The book is well known in the US and still available. > >The german version (Die Seele einer neuen Maschine) is a perfect > >translation but sold out (was rororo i expect). > > > >Happy reading... > > You're right; it's excellent. > > And if memory serves me, Josh Rosen's in it. > > Take care, > Bob PerlmanArticle: 25416
The MV8000 could be done on a small Virtex part but not in a 4005, the MV was a CISC machine the NOVA was am ultra simple RISC machine. The original Nova should be able to fit easily in a 4005. If you look at the Nova instruction set you will see that it requires no decoding and no microcode. The ALC instruction, which is the only operation instruction, has a pair of two bit fields for the register select, a two bit field which controls the carry mux, a 3 bit field which controls the skip mux, a two bit field which controls the shift mux, a bit which selects arithmetic/logical, a bit for zero/register, and a couple of bits of the operation. The load/store as I recall had only one addressing mode, base + offset. There was also a Jump and a Jump and Link instruction, and a couple of IO instructions and that was that. Gary Watson wrote: > > I loved that book. However, it described DG's work to build their 32 bit MV > series intended to compete with the VAX. I think doing a MV on a small FPGA > would be problematic at best as it had a huge microcode control store and > lots of complex instructions. > > -- > > Gary Watson > gary2@nexsan.com > Nexsan Technologies Ltd. > Derby DE21 7BF ENGLAND > http://www.nexsan.com > > "Michael Randelzhofer" <mrandelzhofer@compuserve.com> wrote in message > news:39bc20ba$0$63@personalnews.de.uu.net... > > Hi CPU-Freaks, > > > > When i hear about Data General, i always must recommend the book > > "The soul of a new machine" from tracy kidder. > > > > It's an excellent story about motivation, and an exciting and funny > reading > > about the people > > and the making of computers at Data General. > > > > The book is well known in the US and still available. > > The german version (Die Seele einer neuen Maschine) is a perfect > > translation but sold out (was rororo i expect). > > > > Happy reading... > > > > > > > > Ben Franchuk <bfranchuk@jetnet.ab.ca> schrieb in im Newsbeitrag: > > 39BA5D4A.2E385FCB@jetnet.ab.ca... > > > "B. Joshua Rosen" wrote: > > > > > > > > Do a DG Nova 16 bit CPU. The Nova was able to fit on a single board in > > > > 1969, surely it can fit in a 4005. The Nova's instruction set requires > > > > almost no decoding, it has a fixed width 16 bit instruction and a tiny > > > > number of instructions. The instruction set is very simple, load, > store, > > > > jump, and a single type of execute instruction called and ALC which > > > > combines a simple operation (add,sub, mov, neg, and, or, xor, com), > with > > > > a carry in select (0,1,Carry,!Carry), a shift (left 1, right 1, no > shift > > > > and byte swap), and a skip (noskip, always skip, skip on zero, skip on > > > > not zero, skip on carry 1, skip on carry 0, skip on neg, skip on pos). > > > > > > > > > > Here is some photos of the Nova Computers ,and more information on the > > > instruction set. > > > http://www.ultranet.com/~crfriend/museum/ > > > Ben. > > > PS.I wonder how many 8008's does it take to replace the 586? > > > > > > -- > > > "We do not inherit our time on this planet from our parents... > > > We borrow it from our children." > > > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk > > > >Article: 25417
That is great! I have remembered and retold that line for years... What are you doing back? Did the commune close up? Or did they have an IPO? ;) "B. Joshua Rosen" wrote: > > Your right, I was. I'm the guy who said "I'm sick of nanoseconds, I'm > going off to a commune in Vermont where I'll deal with no period of time > shorter than a season". > > Josh > > Bob Perlman wrote: > > > > On Mon, 11 Sep 2000 02:02:05 +0200, "Michael Randelzhofer" > > <mrandelzhofer@compuserve.com> wrote: > > > > >Hi CPU-Freaks, > > > > > >When i hear about Data General, i always must recommend the book > > >"The soul of a new machine" from tracy kidder. > > > > > >It's an excellent story about motivation, and an exciting and funny reading > > >about the people > > >and the making of computers at Data General. > > > > > >The book is well known in the US and still available. > > >The german version (Die Seele einer neuen Maschine) is a perfect > > >translation but sold out (was rororo i expect). > > > > > >Happy reading... > > > > You're right; it's excellent. > > > > And if memory serves me, Josh Rosen's in it. > > > > Take care, > > Bob Perlman -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25418
Hi, All There is a XCV100E in our design, some of pins are define as a LVCMOS input and were driven by a MC6800 CMOS MCU with an external 100 Ohm resister in series accroding as the databook, the related VCCO were driven by a 3.3V regulator. When the MCU is active and output a high level (5V) to the XCV100E's input, the circuit seems all work properly and the XCV100E was still cold, but the problem is that there is about 4.8V voltage present in the VCCO pin, should anyone tell me what was happen and if it will cause the chip burned out? Thanks a lot. Regards, Channing Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25419
Hi, All There is a XCV100E in our design, some of pins are define as a LVCMOS input and were driven by a MC6800 CMOS MCU with an external 100 Ohm resister in series accroding as the databook, the related VCCO were driven by a 3.3V regulator. When the MCU is active and output a high level (5V) to the XCV100E's input, the circuit seems all work properly and the XCV100E was still cold, but the problem is that there is about 4.8V voltage present in the VCCO pin, should anyone tell me what was happen and if it will cause the chip burned out? Thanks a lot. Regards, Channing Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25420
hey, accedding www.xilinx.com here from UK, has become really uncomfortable expecially after 1:00 p.m GMT. has xilinx mirror site in UK or in europe --Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25421
Evan, The spartan devices have fewer clb's (generally) and the transistors themselves are smaller (one more 1/2 step in the process improvement). Additionally, there is an attempt to keep the die size way down to meet their less than $10 selling price goal for the largest part (or better, in quantity). So you see, Spartan2 had the opportunity to touch just about everything. The smart part was keeping the overall Virtex architecture so the software is an easier job, and has a higher quality of results. Austin eml@riverside-machines.com.NOSPAM wrote: > On Fri, 08 Sep 2000 13:52:00 -0700, Austin Lesea > <austin.lesea@xilinx.com> wrote: > > >Spartan2 transistors are smaller than Virtex transistors, and there are > >fewer of them, and the engineers (just went a'visiting) improved the design. > > Can you tell us why there are fewer transistors in Spartan2? Is this > just a blockRAM size difference? I thought the only significant > difference was the geometry. > > EvanArticle: 25422
Rick, Virtex I parts require a 2A minimum current limited power supply if you intend to start up at -40C. Austin rickman wrote: > Austin Lesea wrote: > > > > Henryk, > > > > The INIT holdoff warning applies to 4K only. It does not apply to > > Virtex, and Virtex architecture derivatives. > > > > I am sorry for the confusion. > > > > In 4K, holding INIT and preventing clean out does not make the device > > HOT -- it may be that the 4K device is in contention from the Vcc not > > going down below a few hundred millivolts, and then the Vcc returns, > > and the 4K device is in a partially configured state, and drawing > > current. So the device is already HOT and getting hotter, and INIT > > prevents the clean out. > > > > Again, Virtex, Virtex E, Spartan2 do not have this behavior. The > > design is such that the means of contention that were caused by memory > > contents which occurred in 4K do not exist in Virtex. > > Can you be a little more specific as to what behaviour you are talking > about? The Virtex data sheet claims it needs up to 2 Amps of current for > startup. So I assume that you are saying that the Virtex does not > continue to draw heavy current when INIT is held low? Is that right? > > > > Henryk Cieslak wrote: > > > > > So, what is the smart method of delaying Virtex configuration? I > > > need to > > > keep Virtex non-configured for an arbitrary time. The config mode > > > can vary - > > > master or slave. > > > Previous data sheets have specified that PROGRAM can be held low to > > > make a > > > delay, but the latest data sheet (2.2) does not mention it - I think > > > it > > > means this method is not recommended. > > > Now you say that keeping INIT low can make the chip consume plenty > > > of > > > current = make hot. > > > What to do? Let it start configuration and wait infinitely for CCLK > > > (slave) > > > or configure with random data until it stops due to checksum error? > > > > > > Henryk Cieslak > > > Becker Elektronic Polska > > > > > > Austin Lesea wrote in message <39B7BF1E.B24BE76F@xilinx.com>... > > > >Alain, > > > > > > > >We recently (> 1 year ago) implemented a Power On Ramp Up current > > > specification > > > >for all parts. We have not gone all the way back to the original > > > 4K > > > family, but > > > >the data sheet now specifies the current capacity of the power > > > supply > > > required > > > >for clean out and startup prior to configuration. > > > > > > > >I would recommend that 1 amp be allowed for each older part (4K, > > > 4KE). > > > > > > > >I know the 4KXL, and all subsequent parts are characterized AND > > > TESTED. > > > > > > > >There are also things you can do which make this start up current > > > worse. A > > > >generally rising voltage, that rises no faster than 2 milliseconds, > > > and no > > > >slower than 50 milliseconds, and starts from near 0 Vdc (< 300 mV) > > > is > > > always the > > > >best way to go. Starting from a voltage around 450 mV to 700 mV > > > from a > > > >previously configured part, or holding INIT to prevent > > > configuration, or > > > passing > > > >through the POR trip point and then going below the POR trip point, > > > are > > > common > > > >causes of higher currents. > > > > > > > >In all cases, check the latest website data sheet. An example is > > > here: > > > > > > > >http://www.support.xilinx.com/partinfo/ds005.pdf > > > > > > > >page 2 of 16 > > > > > > > >For parts that have virtually no current requirement at starup, use > > > the > > > 4KXLA, > > > >4KXV, SpartanXL, or contact your sales office and FAE for assitance > > > in > > > >selection. > > > > > > > >Austin Lesea > > > >IC Design, Xilinx > > > > > > > >Alain Cloet wrote: > > > > > > > >> "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > > > >> news:8p6288$5k7$2@noao.edu... > > > >> > Alexandr V Shuvalov wrote: > > > >> > > > > >> > > Which voltage regulators ICs are commonly used to power > > > supply Xilinx > > > XL > > > >> > > and other low voltage (3.3-2.5v) devices? > > > >> > > > > >> > I used a National LM3940IS-3.3 to drop a VME 5V supply down to > > > 3.3V @ 1 > > > >> > A. > > > >> > > > > >> Can you power-up several Xilinx-FPGA's with this element ; or is > > > there a > > > >> work-around ? > > > >> > > > >> We had this problem recently (not completelly solved), and the > > > most > > > recent > > > >> idea is to supply 3 Xilinx FPGA's with one National LM3940 (other > > > version > > > : > > > >> WG ?). > > > >> > > > >> The element we used before had a fast power-up time which caused > > > the FPGA > > > >> (4013) to take up to 1 A, and the regulator couldn't give 3A (it > > > went ok > > > a > > > >> normal temperature, but in a cold phase at -40C it didn't go). > > > >> > > > >> Can the LM3940 do the job ? > > > >> > > > >> TIA, > > > >> Alain > > > > > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 25423
Nestor, A DDFS (direct digital frequency synthesizer) is an adder/accumulator. They have been around for perhaps 30 years now. I have used them for years in FPGAs. The sine look up table is only used if you want a sine wave. I have seen people use a sine look up table, a D/A, and then follow that mess with a comparator -- TO GET A SQUARE WAVE! Think about it. The MSB of the DDFS was already the signal they wanted! So, if you don't want a sine wave, don't add all that junk. The p-p jitter is the clock period used, and the Fout < 1/2 Fclock. I would use the highest frequency I could get away with. If you require even less jitter, the output can be passed through a single simple VCXO used in a PLL loop with an XOR phase detector and an external RC to remove practically all of the jitter if the frequency output range is narrow enough. Placing the DDFS in a locked loop, results in a complete digital locked loop (Patented -- look it up, under my name). There are many nice parts out there that package the whole thing, and are inexpensive, so you need to evaluate what it is going to be used for, and decide if you want to build it in, or not. Also look at: http://www.xilinx.com/xcell/xl31/xl31_32.pdf for fractional synthesis,and other NCO's. Austin Lesea Nestor wrote: > Hi. > > Does anyone know any manufacturer who fabricates > numerically-controlled crystal oscillators (NCXO), also known as > digitally-controlled crystal oscillators (DCXO) which are suitable for > digital phase-locked loop designs in VHDL and FPGAs? > > Although these blocks resemble a numerically-controlled oscillator > (NCO), they differ in that the NCXO is not oversampled to generate the > required output signal (an NCO needs to be oversampled by at least > 8-times in order to have an acceptable low jitter output). Rather, a > digital input word is fed to the NCXO and it synthesizes the required > output frequency using a standard, low-cost crystal oscillator. The > output is also a square wave, just like the standard crystal. In > general, the NCXO has a narrow tuning range similar to a > voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm relative > to a frequency in the MHz range. > > The NCXO technology is fairly recent from what I understand, but > allows one to replace a circuit composed of a digital-to-analog > converter (DAC) and a VCXO by one chip that performs the exact same > task will less design hassles. The DCXO is ideal for custom-made > phase-locked loop (PLL) circuits using digital sections that can be > implemented in VHDL and FPGAs. > > Since I haven't been able to find any NCXO manufacturers over the web, > I am now looking to the knowledgeable engineers, designers and friends > that frequent these newsgroups for some potential referrals and/or > links. > > Thanks in advance for your help. > > NestorArticle: 25424
That line was joke I love nanoseconds. After I left DG I went off to another company, then in early to mid 80's I was at a supercomputer startup that was composed mostly the same team as the MV8000 (went IPO, rich for a month then then the stock went down the tubes). Since the late 80's I've been consulting, mostly networking stuff these days. rickman wrote: > > That is great! I have remembered and retold that line for years... > > What are you doing back? Did the commune close up? Or did they have an > IPO? ;) > > "B. Joshua Rosen" wrote: > > > > Your right, I was. I'm the guy who said "I'm sick of nanoseconds, I'm > > going off to a commune in Vermont where I'll deal with no period of time > > shorter than a season". > > > > Josh > > > > Bob Perlman wrote: > > > > > > On Mon, 11 Sep 2000 02:02:05 +0200, "Michael Randelzhofer" > > > <mrandelzhofer@compuserve.com> wrote: > > > > > > >Hi CPU-Freaks, > > > > > > > >When i hear about Data General, i always must recommend the book > > > >"The soul of a new machine" from tracy kidder. > > > > > > > >It's an excellent story about motivation, and an exciting and funny reading > > > >about the people > > > >and the making of computers at Data General. > > > > > > > >The book is well known in the US and still available. > > > >The german version (Die Seele einer neuen Maschine) is a perfect > > > >translation but sold out (was rororo i expect). > > > > > > > >Happy reading... > > > > > > You're right; it's excellent. > > > > > > And if memory serves me, Josh Rosen's in it. > > > > > > Take care, > > > Bob Perlman > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com
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