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Different types of adders are available that offer different advantages. These adders are: Ripple Carry Adders Carry lookahead adders Carry Select adders Conditional Sum adders These adders when implemented in FPGAs deliver different performance in terms of speed and area. Both these things are critical for FPGAs. I implemented a Logiblox 4 bit adder and then implemented CLA adder. CLA was equivalent in resources to the logiblox and was faster. But bigger CLA consumes more resources than the Logiblox adder. Adders are the basic units that are extensively used in many designs. Has anyone done a thorough research on which adder is the best for say Xilinx FPGA, Altera, Atmel FPGAs. If someone has done a thorough work on Adders for say, Altera FPGAS, it will be worth sharing the experience. If someone knows that this topic has been discussed it will be helpful to mention the relevant site. Regards, SHAHZAD Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25651
This issue was covered a month or two ago and Peter Alfke indicated that pinout text files would be provided. I think he even made these files available for the Spartan II series. Now if he could do something about the high startup current of the parts. "Tobias F. Garde" wrote: > > Bill Blyth wrote: > > > > I would second the point on raw pinout data. This would beat copying the > > stuff from the pdf, reformatting it and subsequent symbol generation and > > checking. > > > > "Hal Murray" <murray@pa.dec.com> wrote in message > > news:8pprjq$9ju@src-news.pa.dec.com... > > > > > > Note that we also need the pinout info in some easy to process format, > > > probably raw text, so I/we can write some scripts to automate some > > > pinout processing rather than having to do it manually. Maybe you > > > could kill two birds with one stone? > > > > > It would be quite useful if Xilinx could provide the raw pinouts > in some readable format. Meanwhile, some information seems to be > available (though not directly) in the BSDL files residing in: > > $XILINX$\device_name\data > > For example, I have found pinout information about the XCV300E in > a BG432 package in the file: > > $XILINX$\virtexe\data\xcv300e_bg432.bsd > > Regards, > > Tobias F. Garde > ASIC Development Engineer > Tellabs Denmark A/S -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25652
This is very useful information, thanks. I was not asking about the internal design of the two families of parts, although that would be interesting. I was asking about the functional difference. In your earlier posts you seem to indicate that there is a large current draw under a wider range of conditions with the 4K series than with the Virtex series. This is what I am trying to understand. > > > In 4K, holding INIT and preventing clean out does not make the device > > > HOT -- it may be that the 4K device is in contention from the Vcc not > > > going down below a few hundred millivolts, and then the Vcc returns, > > > and the 4K device is in a partially configured state, and drawing > > > current. So the device is already HOT and getting hotter, and INIT > > > prevents the clean out. > > > ********************* This bit right here ******************************** > > > Again, Virtex, Virtex E, Spartan2 do not have this behavior. The ********************* This bit right here ******************************** This is the statement I am asking you to clarify. Tell us about the difference noted above. I do not understand exactly what is different about the behaviour of the two families of devices. I am not asking you to explain the internal proprietary design issues. I do not agree that there is such a significant difference in the markets for the Virtex and the Spartan parts. I don't know how you are targeting your parts, but I can tell you that the users only look at capability (size) and price. I have no reason to care about what the intended market for a family of parts is. So with the considerable overlap in size of the two families (50, 100 and 200K gates), I expect that I will be using either family depending on my specific needs for expandability and size. So I don't agree that you can just say, that there will only be a small number of people using the Virtex parts in designs with current limited power supplies... except for the fact that you won't support them when used that way. Austin Lesea wrote: > > Rick, > > The increased current draw occurs at about 0.6 to 0.8 Vdc in Virtex. > > It occurs at the POR trip point in 4K (see respective data sheets). > > The differences between the virtex and 4k power up cleanout circuits are not > something I can discuss. > > While a supply is ramping up, it is driving the filter capacitors to the > intended output voltage, and the supply is often current limited (can't supply > any more current than it already is) while doing this, and hence the power ramp > up time is constrained (i.e. not instant, by I=C*dV/dt). > > If I had 2000uF of capacitance, and it rises in 2 ms (typical of a really fast > power ramp), that is 2.5V into 2,000uF in 2 ms, or I=2.5A. > > If I had 2000uF of capacitance, and the device suddenly requires 500 mA, you can > see what the dV/dt would be. But, nothing is sudden, and the voltage and > current interact. > > Even hot swap PCI has a rise time due to the resistance and inductance of the > pcb traces to the bypass capacitors of usually no faster than 1 ms. > > You can think of Virtex as being a really big non-linear capacitor. It actually > draws less current as the ramp slows down. This makes this a chicken and egg > problem: how does the power ramp? Is the part connected? they affect one > another. We test to make sure that if a power supply could supply no more than > 500 mA (in Virtex C grade), the device would be ready for configuration and the > vccint is at the power supply vccint (not sagging, or collapsed). The Virtex > part may put a flat spot in the ramp up, but that is just fine (we just don't > like to see it foldback, and dip which is the case with a power supply that is > arranged for a foldback response -- datasheet recommends against this kind of > behavior!). > > We have noted that if you could only supply 100 mA, the ramp might be really > long (~100 ms), but the part would clean out, and start to configure. > > Virtex is not going to be characterized for low current startup, as most designs > require more than 500 mA while operating (no market push to do this). > > Spartan2 on the other hand will be considered (is now being characterized) for > lower current startup as the markets are different for the two parts (there is a > push to do this). > > I hope this answers the first question, and I hope you understand that I can not > discuss the internal circuit design and operation here required to answer you > second question, -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25653
Mark Harvey wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message > news:39BA438C.11D2C0CF@yahoo.com... > > It is also often a *good* idea to speak directly to the manufacturers > > rep as they can give you breaks on pricing that the disti can't, even if > > you are ultimately buying through the disti. Of course this only works > > if you are buying thousands of units. But even at 1000 pieces I have > > gotten better pricing than what the disti would quote me. > > mmm....not so sure about this one, the disti is free to add his own margin > but I still don't think > the rep should be able to undercut him I was not trying to say that the manufacturers rep will give a lower price by cutting out the disti, although they do that on large accounts. But I have called the disti who in turn got me hooked up with the rep who got me lower prices *through* the disti. Disti is limited by what they are paying and what they are willing to do with their profit margin. But if the manufacturer cuts their prices for your order, the disti can pass on the savings. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25654
Ulf Samuelsson wrote: > > "Darin Johnson" <darin@usa.net> wrote in message > news:uaed9o4fn.fsf@nokia.com... > > bjolin@lin.foa.se (Björn Lindgren) writes: > > > > > Intel also managed to get a patent on something published by another > company > > > several years earlier and thereby could be considered as common > knowledge. > > > > Lots of patents are this way. It depends upon how you phrase the > > patent (obfuscation, adding novel twists, etc). > > > ARM Ltd has some key patents that probably would not hold up in court. > One of the key requirements of any interrupt processing in a CPU > is that it must be able to execute the interrupt and return without > destroying > the current context. > In ARM , there is no specific interrupt handling except that the CPU > executes intstructions. > The it follows logically that the context must be protected from > another interrupt until the CPU has saved the current context. > Yet they patent it. Ridiculous..... I would like to understand this. You can't patent a concept, how did they reduce this to practice? If they have no hardware to save context, what did they patent, the software to save context, disabling interrupts or what? > Another patent is that they figured out that people are interested in > good code density. > The "thumb" patent is having two possibly totally unrelated instruction sets > execute on the same pipeline using a mode bit. > The only thing the instruction sets should have in common is that the data > path > of both instruction sets are of the same size. > Like noone knew that 32 bit RISC instructions had poor density. > The classical book on RISC (KAtevenis) states that > "Garrison and VanDyke havbe studied how much RISC code size would be > reduced by encoding the same instruction set vith variable length fields > and instructions [GaVD81]". > In the light of the ARM threats to the "www.open-cores.com" activity it > would be interesting to see how easy the ARM patents would fall down in > court...." I have not heard of the conflict with ARM. Is there a web page discussing it? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25655
Eric Smith wrote: > > "John L. Smith" <jsmith@visicom.com> writes: > > Surely there must be some appeal process available after this 'final' > > decision. Are you saying that if I've been building widgets for > > twenty years, and someone comes along, reverse engineers and patents > > a doohickey that is part of the widget, that person now has the right > > to ask me for royalties? If I can prove that I designed the doohickey > > twenty years ago, it _must_ be possible to overturn the patent > > examiner's > > decision to grant that patent!?!? > > Yes. Shipping a product that embodies an invention is considered > to be prior art for patent purposes. > > If you invented it, kept it secret, built four units, kept three on a > shelf, and gave one to your brother-in-law, that probably would NOT > count as prior art. Even this would count as prior art if you can prove that your invention on the shelf predates the competitor's work on his invention. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25656
Andy Peters wrote: > Anyone rich enough to own copies of all of the synthesizers? Yes. Not me personally, but the company I currently work for owns all three major synthesizers. Not because they are rich, but for some historical reasons. -- Phil HaysArticle: 25657
"John L. Smith" wrote: > > "Paul Hovnanian ®" wrote: > > all areas of industry. Alot of 'prior art' exists but is not known well enough > > outside of a specific industry where an examiner might be aware of it. In some > > cases, someone may have incorporated some technique or idea into a product > > for years without considering it to be patentable. Now, unaware of this (or worse > > yet, with full knowledge) a competitor 'discovers' this idea and applies for a > > patent. If the prior use of this isn't obvious to an outsider (you might have > > to reverse engineer a product or examine a manufacturing process), the first > > person has no defense in our patent system unless he(she) is lucky enough > > to intervene in the application prior to its final decision. > > Surely there must be some appeal process available after this 'final' > decision. Are you saying that if I've been building widgets for > twenty years, and someone comes along, reverse engineers and patents > a doohickey that is part of the widget, that person now has the right > to ask me for royalties? If I can prove that I designed the doohickey > twenty years ago, it _must_ be possible to overturn the patent > examiner's > decision to grant that patent!?!? Just because the patent office doesn't > know about my use of it, and I don't know the application is in process, > makes it legal to steal it!?!? This is very true, you can have an patent voided if you can prove prior art. This is not uncommon and goes back to the telephone and other important inventions. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25658
Joel Kolstad wrote: > <wq998@yahoo.com> wrote in message news:8pus5o$km1$1@nnrp1.deja.com... > > Overall, I like to use Synplicity much more. Its > > schematic view and critical path analysis are very helpful. > If you can believe it... in my experience it's timing estimates are pretty > far off. It tends to overestimate logic delay and underestimate route > delay. My comment is that this is a good indicator of a part of the design where floorplanning can improve the design speed. A synthesis tool can not know where components are placed, so the tool must make some sort of guess as to the lenght of routes. There are two different consequences of this: first the estimate is wrong, so I can't look at the timing estimate and know if the design will place and route, and I don't see the real critical path. The second is a bit little more subtle, and that is the synthesis tool can't build the best logic. I really like the feature in Xilinx 3.1i where the floorplanner will write out in UCF format. This allows me to continue to put the pinout into the UCF file and still use the graphical floorplanner. -- Phil HaysArticle: 25659
I have built a few high speed boards and looked at the capacitive decoupling issues in detail. I have not found a basis for adding the 0.01 uF caps. If you look at the data sheets for the caps you will find impedance vs. freq curves for many of these parts. AVX has very good data sheets in this regard. If you study the impedance curves you will find that all of these caps are inductive at the frequencies that are important for decoupling (>200 MHz). When a capacitor is operating in the inductive region, the characteristics are determined much more by the physical package than by the capacitance of the device. In this case the smaller packages are better, but more importantly, the *wider* packages are better. The inductance of a package very strongly related to the ratio of length to width. Another important feature is the manner of connecting the capacitor to the power pins. The shortest length trace possible should be used. This can be a large contributor to the overall decoupling impedance. So adding two different values of capacitor to a power pin will increase the length of the PC trace and may actually reduce the effectiveness of the decoupling. I looked in my archive of appnotes for information to support this, but could not find any data to quantify the contribution of trace length to decoupling impedance. Anyone have data on this? "S. Ramirez" wrote: > > Dan/Ben, > In general, as Ben said, both caps are a very good and much better > decoupling method than just 0.1uF. > I have seen both used and both work. The 0.01uF/0.1uF combination is a > more conservative and relaible design for high frequency designs. I have > never seen quantitative results, though, to determine just how much better > it really is. I have seen analytical results that say it is better. > I think Ben meant "power distribution system" rather than "power > supplies." The power distribution system includes but isn't limited to the > connector power and ground pins, the power and ground plane design, and the > decoupling caps. > The way I see it is that 0.01uF caps are cheap. If you have the real > estate and a few bucks to spare, why not use them? > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > > > Is such a recomendation useful ? > > > > > > Dan > > > > That is true, it is better than a cap of .11 uf? > > For the high frequencies the .01 cap has less > > inductance and is able to respond power supply fluctuations quickly until > > the .1 cap can catch up. With transistors switching in ps range you need > > very good high freq response on the power supplies. > > > > -- > > "We do not inherit our time on this planet from our parents... > > We borrow it from our children." > > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25660
Joel Kolstad wrote: > > <eml@riverside-machines.com.NOSPAM> wrote in message > news:39c205c4.14815385@news.dial.pipex.com... > > Except that, last time I looked, Synplify didn't know that Virtex had > > a sync reset. > > As someone who's just fixed a bunch of code to deal with this supposed > "problem," I can tell you that actually, Synplify DOES know about > synchronous resets. HOWEVER... it DOES NOT know about GSR. As you're > aware, the 'flops in a Virtex CLB can have an asynchronous or synchronous > set/reset -- but not both. So guess what happens with this code -- ...snip... > ...and you WILL get a synchronous reset. Woo hoo! Yes, in the words of Ray > Andraka, not having a global async. reset will "make an ASIC designer's > blood curdle," but just don't mention what you've done at your next design > review, and you'll be fine. > > In fact, if I recall correctly, the Xilinx power-on resetwill (in this case) > reset the 'flop anyway. Yeah, but what if you need some of those flops set on power-on? I guess there are some UCF constraints that you can add to have the flops set on GSR? If you use the async reset in your code you control this behaviour directly where it should be done. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25661
This is a multi-part message in MIME format. --------------B2CBC0171330FA2AC6D249A3 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Ben Franchuk wrote: > gk7eong wrote: > > > > Hi, > > > > I'm a final year electrical electronics engineering student. I'm using > > Max Plus 2 Baseline 9.6 to do my final year project. Is there anyone out > > there with full licences? Can you send me a copy of your license.dat or > > can anybody tell me how to get the partitioner features from it. Thanks > > in advance. > > > I think the best partitioner is still the old brain cells.I am also > using the Free version of Baseline in a home computer project.With what > little design I have done,I can route about 75% of the LCB's in FPGA. > The licence.dat is only for a specific hard drive, thus you need a > new license if your HD fails, preventing transferring between machines. > I realise this, but what is important is not the HD key to me. cause I already have mine. What I need is to unlock the feature with certain keyword. > > Ben. > -- > "We do not inherit our time on this planet from our parents... > We borrow it from our children." > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk --------------B2CBC0171330FA2AC6D249A3 Content-Type: text/x-vcard; charset=us-ascii; name="gk7eong.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for gk7eong Content-Disposition: attachment; filename="gk7eong.vcf" begin:vcard n:Goh;Kheng Teong x-mozilla-html:FALSE adr:;;;Johor Bahru;Johor;;Malaysia version:2.1 email;internet:gk7eong@pd.jaring.my fn:Kheng Teong Goh end:vcard --------------B2CBC0171330FA2AC6D249A3--Article: 25662
This is a multi-part message in MIME format. --------------6D94373B98B07506F3B33FA2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, yes I will appreciate it if you send the license.dat for ModelSim to me. About my school paying for the software? I think it is really fat hopes. The way things work here is kind of different. =) Thanks in advance. Kheng Teong Andy Peters wrote: > gk7eong wrote: > > > > Hi, > > > > I'm a final year electrical electronics engineering student. I'm using > > Max Plus 2 Baseline 9.6 to do my final year project. Is there anyone out > > there with full licences? Can you send me a copy of your license.dat or > > can anybody tell me how to get the partitioner features from it. Thanks > > in advance. > > I can send you a license.dat for ModelSim. It will be as useful to you > as anyone's Max+Plus 2 license.dat file, since the software is > node-locked. > > You could consider having your school pay for the software, which is the > Right Thing to do. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u --------------6D94373B98B07506F3B33FA2 Content-Type: text/x-vcard; charset=us-ascii; name="gk7eong.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for gk7eong Content-Disposition: attachment; filename="gk7eong.vcf" begin:vcard n:Goh;Kheng Teong x-mozilla-html:FALSE adr:;;;Johor Bahru;Johor;;Malaysia version:2.1 email;internet:gk7eong@pd.jaring.my fn:Kheng Teong Goh end:vcard --------------6D94373B98B07506F3B33FA2--Article: 25663
As always Xilinx feature promises remain very attractive. However, I have been "burnt" in the past on three projects where Xilinx was used (one scorched-earth [total project failure] and two roasts[massive time/cost over-runs]) in about the 1989 thru 1995 time-frames with XC200, XC3000, & XC4000 chips. In fairness, the two "roasts" occurred when management allowed a contractor to ignore my design specification guidelines on the grounds that the contractor knew more then I did! My basic Xilinx "Lessons Learned" were: 1. Chip Selection: Design estimate at 40% or less of chip capacity. 2. Chip Speed: Assume design can only achieve 25% of "expected" relative to chip ratings until proven otherwise. 3. Timing Simulator: If lucky, your implementated design will only be 125% of the critical-path timing predicted by the Timing Simulator. 4. Never go to Production PCB before the prototype works, "bugfixes" always seem to require IOB assignments to be "unlocked" before the design will "re-compile". During this same time frame, I used Altera with no equivalent problems. I would summerize my experience as: **Xilinx promises more, but implementation can only achieve about 40% of their promises. **Altera promises less, but implementation can achieve about 90% of their promises. I would be very interested to hear from current Xilinx End-Users to see if the performance of the current generation of Xilinx hardware/software is sufficiently improved to revise my lessons-learned and/or make me willing to again step into a "Xilinx-swamp". TIA and Bye while looking forward to an interesting thread. PS: I actually designed as well as "monitored" contractors doing design, so you can flame me as obsolete but hopefully not as ignorant.Article: 25664
In article <w4Fw5.943$ks.39056@newsread1.prod.itd.earthlink.net>, "Joel Kolstad" <Joel.Kolstad@USA.Net> wrote: > <wq998@yahoo.com> wrote in message news:8pus5o$km1$1@nnrp1.deja.com... > > I am not rich, but do have FPGA Express v3.4 (with Foundation v3.1) and > > Synplicity Pro v6.0. Overall, I like to use Synplicity much more. Its > > schematic view and critical path analysis are very helpful. > > If you can believe it... in my experience it's timing estimates are pretty > far off. It tends to overestimate logic delay and underestimate route > delay. Our current design has a 53MHz clock running around, and meets PAR > timing just fine, even though Synplify claims the timing margin is - 5.6ns. > Yeah, right. > In my experience, Synplify gives close or realistic estimates. It seems to me that Synopsys never count route delay in its estimates. In my current design, Synopsys gives 124MHz in estimation, PAR result is 87MHz. Sinplify's estimation is 93MHz. > FPGA Express is pretty dismal. People who bitch about how buggy > Microsoft's operating systems are should try FPGA Express for awhile... Agree. Exporting of timing constraints in FPGA Express v3.4 to Xilinx backend software causes Abort xxx everytime. I could not find that abort code number xxx in Xilinx database. -wq998 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25665
Hi - Some good papers on decoupling can be found at: http://www.qsl.net/wb6tpu/si_documents/docs.html Take a look at the first paper listed. Among other things, it describes the amount of inductance introduced by several different capacitor-pad-to-via geometries. Bob Perlman On Sat, 16 Sep 2000 11:28:57 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >I have built a few high speed boards and looked at the capacitive >decoupling issues in detail. I have not found a basis for adding the >0.01 uF caps. If you look at the data sheets for the caps you will find >impedance vs. freq curves for many of these parts. AVX has very good >data sheets in this regard. > >If you study the impedance curves you will find that all of these caps >are inductive at the frequencies that are important for decoupling (>200 >MHz). When a capacitor is operating in the inductive region, the >characteristics are determined much more by the physical package than by >the capacitance of the device. In this case the smaller packages are >better, but more importantly, the *wider* packages are better. The >inductance of a package very strongly related to the ratio of length to >width. > >Another important feature is the manner of connecting the capacitor to >the power pins. The shortest length trace possible should be used. This >can be a large contributor to the overall decoupling impedance. So >adding two different values of capacitor to a power pin will increase >the length of the PC trace and may actually reduce the effectiveness of >the decoupling. > >I looked in my archive of appnotes for information to support this, but >could not find any data to quantify the contribution of trace length to >decoupling impedance. Anyone have data on this? > > > >"S. Ramirez" wrote: >> >> Dan/Ben, >> In general, as Ben said, both caps are a very good and much better >> decoupling method than just 0.1uF. >> I have seen both used and both work. The 0.01uF/0.1uF combination is a >> more conservative and relaible design for high frequency designs. I have >> never seen quantitative results, though, to determine just how much better >> it really is. I have seen analytical results that say it is better. >> I think Ben meant "power distribution system" rather than "power >> supplies." The power distribution system includes but isn't limited to the >> connector power and ground pins, the power and ground plane design, and the >> decoupling caps. >> The way I see it is that 0.01uF caps are cheap. If you have the real >> estate and a few bucks to spare, why not use them? >> -Simon Ramirez, Consultant >> Synchronous Design, Inc. >> >> > > Is such a recomendation useful ? >> > > >> > > Dan >> > >> > That is true, it is better than a cap of .11 uf? >> > For the high frequencies the .01 cap has less >> > inductance and is able to respond power supply fluctuations quickly until >> > the .1 cap can catch up. With transistors switching in ps range you need >> > very good high freq response on the power supplies. >> > >> > -- >> > "We do not inherit our time on this planet from our parents... >> > We borrow it from our children." >> > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk >> >Article: 25666
What figures did you use for your estimates of capacity and speed? In my experience there is no substitute for knowing how well a particular type of design style maps into the architecture. The effective capacity of a Xilinx chip varies by a factor of as much as 10 to 1 depending on how hard you try to exploit the features of a particular FPGA family. For example I've done a bunch of XCV300 designs, those that I've taken a quick and dirty approach to might use 50K equivalent gates (Xilinx's number, the real number is lower), on the other hand I have one design where I pulled out all the stops to cram as much functionality as possible into the part and that has almost 500K Xilinx equiv gates. The same is true of clock speed. If you heavily pipeline a design then you can get 100Mhz in an XCV300-6, and as much as 200Mhz in small selective areas in you work hard enough at it. On the other hand for someone who is use to ASICs, where the tradeoffs are completely different, getting 50Mhz is hard just because they don't have a feel for what fits in a cycle and what doesn't and what sorts of things cause routing problems which will slow down the design. Things like pin location don't matter nearly as much as they use to. But here it's important to take advantage of Xilinx's registered IO, once again it's a matter of understanding what works and what doesn't. The safest approach is always to target a part that shares a package with a larger capacity part, preferably much larger, then you have a safety net if the project blows up. Duane Hague wrote: > > As always Xilinx feature promises remain very attractive. However, I > have been "burnt" in the past on three projects where Xilinx was used > (one scorched-earth [total project failure] and two roasts[massive > time/cost over-runs]) in about the 1989 thru 1995 time-frames with XC200, > XC3000, & XC4000 chips. In fairness, the two "roasts" occurred when > management allowed a contractor to ignore my design specification > guidelines on the grounds that the contractor knew more then I did! My > basic Xilinx "Lessons Learned" were: > > 1. Chip Selection: Design estimate at 40% or less of chip capacity. > 2. Chip Speed: Assume design can only achieve 25% of "expected" > relative to chip ratings until proven otherwise. > 3. Timing Simulator: If lucky, your implementated design will only be > 125% of the critical-path timing predicted by the Timing Simulator. > 4. Never go to Production PCB before the prototype works, "bugfixes" > always seem to require IOB assignments to be "unlocked" before the design > will "re-compile". > > During this same time frame, I used Altera with no equivalent problems. > I would summerize my experience as: > > **Xilinx promises more, but implementation can only achieve about 40% of > their promises. > > **Altera promises less, but implementation can achieve about 90% of their > promises. > > I would be very interested to hear from current Xilinx End-Users > to see if the performance of the current generation of Xilinx > hardware/software is sufficiently improved to revise my lessons-learned > and/or make me willing to again step into a "Xilinx-swamp". > > TIA and Bye while looking forward to an interesting thread. > > PS: I actually designed as well as "monitored" contractors doing design, > so you can flame me as obsolete but hopefully not as ignorant.Article: 25667
> Another important feature is the manner of connecting the capacitor to
> the power pins. The shortest length trace possible should be used. This
> can be a large contributor to the overall decoupling impedance. So
> adding two different values of capacitor to a power pin will increase
> the length of the PC trace and may actually reduce the effectiveness of
> the decoupling.
>
> I looked in my archive of appnotes for information to support this, but
> could not find any data to quantify the contribution of trace length to
> decoupling impedance. Anyone have data on this?
From High-Speed Digital Design, A Handbook of Black Magic
by Johnson and Graham, top of page 288.
When using any surface-mounted bypass capacitor, don't destroy its
effectiveness by connecting it to a long, skinny via leading down to
the power or ground plane. Use a larger via, or multiple vias, for
connecting bypass components. Also, use as short and as fat a trace
as possible leading from the via to the capacitor.
That's the first place I look for anything tricky/sneaky on the analog
side of a design. It's full of good stuff. Anybody interested in this
area should have a copy handy.
Page 259 discusses the inductance of vias.
--
These are my opinions, not necessarily my employers. I hate spam.
Article: 25668> 1. Chip Selection: Design estimate at 40% or less of chip capacity. > 2. Chip Speed: Assume design can only achieve 25% of "expected" > relative to chip ratings until proven otherwise. My experience is quite different. I think it depends upon what sort of problem you are working on and/or how you go about it. You can use most of the CLBs in a chip if your problem is mostly data-path and you lay things out cleanly. I've worked on several designs that used over 90% of the CLBs. You can get higher usage if you fill in the cracks around the edges with unrelated junk. I'm not sure what you mean by "expected" speed. You can make a design go a lot faster if you pipeline things. You can sometimes make control logic go a lot faster if you replicate critical signals. -- These are my opinions, not necessarily my employers. I hate spam.Article: 25669
On Sat, 16 Sep 2000 10:12:50 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >This is very true, you can have an patent voided if you can prove prior >art. This is not uncommon and goes back to the telephone and other >important inventions. The problem is that some court districts will take a patent issued by the patent office as prime evidence of its validity. The battle then isn't a 51/49 or better push on the evidence, but perhaps a 75/25 push in the disfavor of the challenger. Once that patent gets issued, it is often taken as strong evidence in its own justification, making the challenge that much harder to meet in court. JonArticle: 25670
On Sat, 16 Sep 2000 09:58:42 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >I would like to understand this. You can't patent a concept, how did >they reduce this to practice? If they have no hardware to save context, >what did they patent, the software to save context, disabling interrupts >or what? Worse, all the books for neophyte US patent types (like me) say that patents are issued for "novel" and "non-obvious to a practitioner in the field" kinds of things. Novel means, to me, NEW. And non-obvious means that if someone asks me to solve the same or similar task as the patenter did, that I wouldn't normally come up with the same things in a brain-storming session or two. It sometimes seems to me that US patents are issued for just about anything that isn't already common knowledge to 8th grade schoolers and which doesn't even have to be novel. I guess I still don't get it. JonArticle: 25671
"Jon Kirwan" <jkirwan@easystreet.com> wrote in message news:q818ssk8nlrfl1hai1g8viln3mcc5qdbrm@4ax.com... > On Sat, 16 Sep 2000 10:12:50 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >This is very true, you can have an patent voided if you can prove prior > >art. This is not uncommon and goes back to the telephone and other > >important inventions. > > The problem is that some court districts will take a patent issued by > the patent office as prime evidence of its validity. The battle then > isn't a 51/49 or better push on the evidence, but perhaps a 75/25 push > in the disfavor of the challenger. Once that patent gets issued, it > is often taken as strong evidence in its own justification, making the > challenge that much harder to meet in court. > > Jon My observations, is that despite wordings such as prior art, novelty, non-obvious to those skilled in the art etc... etc... the reality is that if there is no existing patent the new "invention" will automatically get a patent, and once granted, by and large, it is impossible to get nullified. Kevin Aylward , Warden of the Kings Ale kevin@anasoft.co.uk http://www.anasoft.co.uk - SuperSpice "Cheap, No Shit!", a currently free GUI xspice, unlimited component, mixed-mode Windows simulator with Schematic Capture, waveform display, FFT's and Filter Design. Opinions of my employer are not necessarily indicative of my own Oscillators don't, amplifiers do"Article: 25672
shahzad2512@my-deja.com wrote: > Different types of adders are available that offer different > advantages. These adders are: > Ripple Carry Adders > Carry lookahead adders > Carry Select adders > Conditional Sum adders > These adders when implemented in FPGAs deliver different performance in > terms of speed and area. In modern FPGAs with a dedicated fast (ripple) carry structure ( Xilinx as well as Altera), this simple structure is both the smallest and the fastest adder implementation, at least up to 32 bits. The incremental carry delay per bit is well below 100 ps per bit ( conservatively), which makes it hard to improve on, using any fancier schemes. Peter Alfke ( back in town after 3 weeks on the road in Austria and Poland )Article: 25673
The Spartan II has three sizes that come in the FG456 package: XC2S100-nFG456C XC2S150-nFG456C XC2S200-nFG456C The Spartan II has three sizes that come in the FG456 package: XCV100-nFG456C XCV150-nFG456C XCV200-nFG456C Are the footprints interchangable ??? The Spartans cost around $25-$45 The Virtex cost around $150-$300 I want to design a board with one of the Spartan FG456s (because of the cost issue) but they will not be in stock for months. Can I layout a PCB and stuff it with a Virtex for development ? I gave their pinouts a quick once over. They look the same but I need to be certain. DanArticle: 25674
LVDS needs 2.5V on Vcco. LVPECL uses 3.3. Suppose you want to get bits from a Virtex-E on one card through a cable to a Virtex-E on another card and you control both ends of the design. Is there any reason to prefer LVDS or LVPECL signaling? Is there any reason not to use LVPECL and avioid the extra power level if you don't have any other need for 2.5V? -- These are my opinions, not necessarily my employers. I hate spam.
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