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Messages from 99525

Article: 99525
Subject: Re: Nios II - Branch Prediction
From: "Paul Leventis" <paul.leventis@gmail.com>
Date: 25 Mar 2006 22:43:30 -0800
Links: << >>  << T >>  << A >>
Hi Isaac,

There are far fancier ones than this.  The DEC Alpha 21264 had a snazzy
scheme where they had two different branch predictors, and picked the
better of the two dynamically.  A global predictor used the results
(taken/not taken) of the last 12 branches to predict what the next
branch would do.  A local predictor tracked for a set of branches
whether they were taken or not taken for the past few times the branch
was evaluated, and predicts accordingly.

The 21264 would then store on a per-branch basis which predictor was
doing a better job.  Some branches (say, the end of a for loop with a
lot of iterations) are well predicted by a local predictor.  Some
branches (for example, a for loop that iterates exactly 4 times,
resulting in taken-taken-taken-not_taken pattern) are better predicted
by a global predictor.  So it woudl get the best of both worlds.

I did a school project on 21264 branch prediction, but can no longer
find the source material on the web.  However, I did come across this
fairly good presentation that describes branch prediction methods and
which processors use what.

http://meseec.ce.rit.edu/eecc551-winter2003/551-12-17-2003.pdf

Enjoy,

Paul Leventis
Altera Corp.


Article: 99526
Subject: chip reverse engineering
From: mikeotp@gmail.com
Date: 25 Mar 2006 23:48:50 -0800
Links: << >>  << T >>  << A >>
regards

is it possible from the driver of a chip and pin assignment

of a chip to reverse a chip,and to produce the same chip?

         
any positive suggestion is welcome
best regards to you all


Article: 99527
Subject: Re: OpenSPARC released
From: "Ira Baxter" <idbaxter@semdesigns.com>
Date: Sun, 26 Mar 2006 02:20:16 -0600
Links: << >>  << T >>  << A >>

"Pablo Bleyer Kocik" <pablobleyer@hotmail.com> wrote in message
news:1143352457.542187.192280@e56g2000cwe.googlegroups.com...
> Plain ol' verilog udp?

dff #4  park_reg(.din  (next_pv),
      .clk  (clk),
      .q    (park_vec),
      .se   (se), .si(), .so());

   ....

I don't see how the #4 is legal is Verilog 2001.


The Verilog standard says:

A.5.4

udp_instantiation = udp_identifier [ drive_strength ] [delay2] udp_instance
{ , udp_instance } ;
udp_instance = [name_of_udp_instance] ( output_terminal , ....

A.3.3:

output_terminal = net_lvalue

I can't see how from the Verilog grammar that  the sequence
     .din
is allowed as net_lvalue.

So, this must be a module instantiation, which doesn't allow the #4.

Am I missing something obvious?

A deriivation of output_terminal to the concrete terminals .din would be
appreciated.

-- IDB




Article: 99528
Subject: ERROR:NgdBuild:604
From: "Mich" <michiel.vanderlinden@gmail.com>
Date: 26 Mar 2006 01:07:58 -0800
Links: << >>  << T >>  << A >>
Hi

I have made a new IP using the create or import peripheral wizard. When
I add my own logic to this IP I get this error

"ERROR:NgdBuild:604 - logical block
   'ip_comp_0/ip_comp_0/USER_LOGIC_I/teller_laag' with type 'teller4'
could not
   be resolved. A pin name misspelling can cause this, a missing edif
or ngc
   file, or the misspelling of a type name. Symbol 'teller4' is not
supported in
   target 'virtex2p'."

I have split up my code in comonent so I have a better overvieuw. When
I don't do this and put everything in the same VHDL file I don't have
this error.

I have been searching the web and this discussion group but I don't
find an answer.

What do I have to do so I can still use components and don't get this
error?

Greets
Michiel


Article: 99529
Subject: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
From: "Arash Majd" <arash_majd@ee.sharif.edu>
Date: 26 Mar 2006 01:31:59 -0800
Links: << >>  << T >>  << A >>
Hello Dear friends
Thanks for all your careful attentions.
I found the solutions. I have set the slew rate setting to slow instead
of fast. When I did this,The jitter came down to .05 UIpp.

Arash Majd

Arash Majd wrote:
> Hello Dear friends
> The board we have designed uses of XC2C256 in its center which
> distributes and switches between different signals in system. We use of
> a timing chip which derives the the output of the optical interface of
> our board. The output clock of the timing chip (named zl_1944_clk)
> which is very exact is 19.44 MHz which we have connected to the CPLD's
> GCK0 input pin and assigned this net to an output on one of the
> ordinary I/O pins to the  clock net of the driving ASIC of the optical
> interface. At this case he measured output jitter on the optical
> interface is approximately 0.12  UIpp and fluctuates unacceptedly
> between 0.08 and 0.15. But when the same signal (zl_1944_clk) is input
> from another input (I/O) port,  the output jitter decreases down to
> 0.05 UIpp. (maenwhile when we bypass the cpld in this net the output
> jitter is 0.07 and doesn't fluctuate that much.)
> Besides, when I get the fitter report of the xilinx ISE 6.1i, it says
> "global clock nets unused".( Although I have connected the zl_1944_clk
> net to GCK0 pin)
> I checked my project with ISE 7.1i, too and it did not work, too.
> I would be grateful if someone help me about this problem and he
> following questions.
>
>
> 1-Is there any point in using GCK0 pin ?
> 2-Should I use of timing constraints to make ISE to route my clock
> signal as desired.
>
> I am under pressure and i should deliver the product as soon as
> possible.
> 
> 
> thanks


Article: 99530
Subject: Re: chip reverse engineering
From: Bevan Weiss <kaizen__@NOSPAM.hotmail.com>
Date: Sun, 26 Mar 2006 21:45:04 +1200
Links: << >>  << T >>  << A >>
mikeotp@gmail.com wrote:
> regards
> 
> is it possible from the driver of a chip and pin assignment
> 
> of a chip to reverse a chip,and to produce the same chip?
> 
>          
> any positive suggestion is welcome
> best regards to you all
> 

If I have two numbers, one an input of 53 and the other an output of 20 
is there any way to tell how I came by changing the input into the 
output?  Try and reflect this into the electrical realm and imagine them 
as chip inputs.  If you can't realize the point of that, then no you 
have absolutely no chance of producing the same chip at all.

Regards,
Bevan

Article: 99531
Subject: Re: BlockROM inference in XST - This is just plain silly
From: "Antti" <Antti.Lukats@xilant.com>
Date: 26 Mar 2006 01:45:21 -0800
Links: << >>  << T >>  << A >>
oh there are zillions of mockups, gotta get used to that.

for your case you may try using a "fake" 0 or 1, eg a signal that is
constant but is not recognized as constant by xilinx flow, this is
clever trick that helps in many different cases :)

Antti


Article: 99532
Subject: Re: OpenSPARC released
From: mk<kal*@dspia.*comdelete>
Date: Sun, 26 Mar 2006 10:09:52 GMT
Links: << >>  << T >>  << A >>
On Sat, 25 Mar 2006 22:59:57 -0600, "Ira Baxter"
<idbaxter@semdesigns.com> wrote:

>I found this in  design/sys/iop/sparc/ifu/rtl/sparc_ifu_rndrob.v
>
>   ....
>   assign  next_pv[0] = pv[0] | reset;
>
>   dff #4  park_reg(.din  (next_pv),
>      .clk  (clk),
>      .q    (park_vec),
>      .se   (se), .si(), .so());
>
>   ....
>
>I don't see how the #4 is legal is Verilog 2001.
>Can someone explain to me under what it means,
>and under what circumstances this is legal?
>Is this construct part of Verilog 2001, or is it vendor specific?

Looks like a parameter override. The standard specifies paranthesis
around the number but I bet if only one number is used most tools
accept one without a number. Is there parameter for the module "dff"?

Article: 99533
Subject: EDK 8.1 Problem: Adding *.h or *.c files ?
From: "Ben_M" <Ben.Marpe@gmx.de>
Date: 26 Mar 2006 02:14:27 -0800
Links: << >>  << T >>  << A >>
Hello everybody,

Starting with the Xilinx Microblaze Examples, I'd like to add my own .h
and .c files with function declarations and definitions for my custom
problem...

But by adding a file (right mouse click on "Sources" or "Headers" ->
"Add File" in the Application tab, the whole Programm still compiles
but doesn't run anymore on the Microblaze...

What's my mistake ? Do I have to change the Linkerscript ?
Where in the EDK projekt folder existing .c and .h files have to be
copied in order to be able to #include them ?


(I'm quite new to EDK...)
Thanks a lot...

Bye BEN


Article: 99534
Subject: Re: BlockROM inference in XST - This is just plain silly
From: "Maki" <prase.ruzicasto@gmail.com>
Date: 26 Mar 2006 02:16:37 -0800
Links: << >>  << T >>  << A >>
<snip>
>The 8.1i
> release of ISE has support for "synchronously controlled initialization
> of the RAM data outputs"  (pg 218 of XST User Guide) and for RAM
> initialization (pg 226). Thinking I can be clever about it, I code up a
> RAM with initial values and also with output initialization:
>
> type ram_type is array (0 to 255)
>               of std_logic_vector(7 downto 0);
> signal RAM : ram_type := (
>   X"12", X"34", yadda, yadda, yadda,
>
> constant Init_Value : std_logic_vector( 7 downto 0 )
>                       := x"FE";
> ...
> process( Clk ) begin
>   if RISING_EDGE( Clk ) then
>     if CE = '1' then
>       if WE = '1' then
>         RAM (TO_INTEGER(Addr)) <= DI;
>       end if;
>       if rst = '1' then -- optional reset
>         D_Out <= Init_Value;
>       else
>         D_Out <= RAM(TO_INTEGER(addr)) ;
>   end if; end if; end if;
> end process;
>
> and then just tie off we:
>
>   WE <= '0';
>
> What does XST do with this? It sees WE tied off, realizes this is a
> ROM, not a RAM, and spits out the message:
>
> INFO:Xst:1649 - Currently unable to implement this ROM as a read-only
> block RAM. Please look for coming sofware updates.

Hi John,
I have seen this message before when I successfully inferred Block ROM
256x72 for an instruction decoder. This message usually pops out when
You don't follow the template carefully. Why don't You use template for
ROM and just add preset? Something like this:
(Warning, copying from the manual with some modifications)

entity rominfr is
port (
	clk : in std_logic;
	en : in std_logic;
	addr : in std_logic_vector(4 downto 0);
	data : out std_logic_vector(3 downto 0));
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM : rom_type :=(
"0001","0010","0011","0100","0101","0110","0111","1000","1001",
"1010","1011","1100","1101","1110","1111","0001","0010","0011",
"0100","0101","0110","0111","1000","1001","1010","1011","1100",
"1101","1110","1111");
begin
process (clk)
begin
if (clk'event and clk = '1') then
	if (en = '1') then
		if rst = '1' then -- optional reset
			do <= Init_Value;
		else
			data <= ROM(conv_integer(addr);
		end if;
	end if; 
end if; 
end process; 
end syn;

Best regards,
M.


Article: 99535
Subject: Re: chip reverse engineering
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 26 Mar 2006 12:20:46 +0200
Links: << >>  << T >>  << A >>
"Bevan Weiss" <kaizen__@NOSPAM.hotmail.com> schrieb im Newsbeitrag 
news:zotVf.8703$JZ1.319019@news.xtra.co.nz...
> mikeotp@gmail.com wrote:
>> regards
>>
>> is it possible from the driver of a chip and pin assignment
>>
>> of a chip to reverse a chip,and to produce the same chip?
>>
>>          any positive suggestion is welcome
>> best regards to you all
>>
>
> If I have two numbers, one an input of 53 and the other an output of 20 is 
> there any way to tell how I came by changing the input into the output? 
> Try and reflect this into the electrical realm and imagine them as chip 
> inputs.  If you can't realize the point of that, then no you have 
> absolutely no chance of producing the same chip at all.
>
> Regards,
> Bevan

it all depends.

known info:

==================
1) Sattellite co-ordinates
2) transponder number
3) "has encrypted digital audio"
==================

from the info above and only from that info without ever seeing the original 
decoder I did produce a dual layer PCB holding

a Z80
13 Lattice GALs
27256 EEPROM program code and hamming correction table
2KB static RAM
8KB ram for digital sample storage

my board implemented all error correction built in the digital transmittion, 
learned new true random encryption keys in max 200 milliseconds.

the original was an Matsushita ASIC, but my box had better error tolerance 
as the original design !! Filmnet had to turn off encryption when snow fall 
onto sattellite dishes in Norway, under that condtions the replica was still 
operating ok.

This is not possible? I would say so, but I did do it.

Today i would implement all that of that design in one single Lattice XP :)

so its all about what it is, and who is the one doing the design ...

Antti

























Article: 99536
Subject: Re: ERROR:NgdBuild:604
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Sun, 26 Mar 2006 12:56:31 +0200
Links: << >>  << T >>  << A >>
Mich wrote:
> Hi
> 
> I have made a new IP using the create or import peripheral wizard. When
> I add my own logic to this IP I get this error
> 
> "ERROR:NgdBuild:604 - logical block
>    'ip_comp_0/ip_comp_0/USER_LOGIC_I/teller_laag' with type 'teller4'
> could not
>    be resolved. A pin name misspelling can cause this, a missing edif
> or ngc
>    file, or the misspelling of a type name. Symbol 'teller4' is not
> supported in
>    target 'virtex2p'."
> 
> I have split up my code in comonent so I have a better overvieuw. When
> I don't do this and put everything in the same VHDL file I don't have
> this error.
> 
> I have been searching the web and this discussion group but I don't
> find an answer.
> 
> What do I have to do so I can still use components and don't get this
> error?
> 
> Greets
> Michiel
> 

You have to add them into the data/your_ip_name.pao file.
Open it and you'll see the syntax is obvious ... you have to put them
'in-order' IIRC (not sure ...), that is, the sub modules first.


Sylvain

Article: 99537
Subject: Re: miniuart
From: preet <preet723@hotmail.com>
Date: Sun, 26 Mar 2006 03:57:42 -0800
Links: << >>  << T >>  << A >>
Hi, Please someone help me too.

As a school project i am designing a Viterbi Decoder, now i have to test it on FPGA.

Please can you give me the guidelines or the pointers to how can i actually test the code.

Someone gave me a clue that using RS232 will help. But, i have no clue, how to transfer the data from my PC to FPGA and how to receive the output. In which format am i supposed to send the data, which data file?

Please if someone can guide me.

thanks and regards

Article: 99538
Subject: need help,test on Spartan3 starter kit
From: preet <preet723@hotmail.com>
Date: Sun, 26 Mar 2006 04:00:56 -0800
Links: << >>  << T >>  << A >>
Hi, Please someone help me.

As a school project i am designing a Viterbi Decoder, now i have to test it on FPGA.

Please can you give me the guidelines or the pointers to how can i actually test the code.

Someone gave me a clue that using RS232 will help. But, i have no clue, how to transfer the data from my PC to FPGA and how to receive the output. In which format am i supposed to send the data, which data file? What all steps are needed?

Please if someone can guide me.

thanks and regards

Article: 99539
Subject: Re: chip reverse engineering
From: Bevan Weiss <kaizen__@NOSPAM.hotmail.com>
Date: Mon, 27 Mar 2006 00:01:24 +1200
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> "Bevan Weiss" <kaizen__@NOSPAM.hotmail.com> schrieb im Newsbeitrag 
> news:zotVf.8703$JZ1.319019@news.xtra.co.nz...
>> mikeotp@gmail.com wrote:
>>> regards
>>>
>>> is it possible from the driver of a chip and pin assignment
>>>
>>> of a chip to reverse a chip,and to produce the same chip?
>>>
>>>          any positive suggestion is welcome
>>> best regards to you all
>>>
>> If I have two numbers, one an input of 53 and the other an output of 20 is 
>> there any way to tell how I came by changing the input into the output? 
>> Try and reflect this into the electrical realm and imagine them as chip 
>> inputs.  If you can't realize the point of that, then no you have 
>> absolutely no chance of producing the same chip at all.
>>
>> Regards,
>> Bevan
> 
> it all depends.
> 
> known info:
> 
> ==================
> 1) Sattellite co-ordinates
> 2) transponder number
> 3) "has encrypted digital audio"
> ==================
> 
> from the info above and only from that info without ever seeing the original 
> decoder I did produce a dual layer PCB holding
> 
> a Z80
> 13 Lattice GALs
> 27256 EEPROM program code and hamming correction table
> 2KB static RAM
> 8KB ram for digital sample storage
> 
> my board implemented all error correction built in the digital transmittion, 
> learned new true random encryption keys in max 200 milliseconds.
> 
> the original was an Matsushita ASIC, but my box had better error tolerance 
> as the original design !! Filmnet had to turn off encryption when snow fall 
> onto sattellite dishes in Norway, under that condtions the replica was still 
> operating ok.
> 
> This is not possible? I would say so, but I did do it.
> 
> Today i would implement all that of that design in one single Lattice XP :)
> 
> so its all about what it is, and who is the one doing the design ...
> 
> Antti

Ahh, but you obviously didn't fully read what the OP asked for...

 >is it possible from the driver of a chip and pin assignment
 >of a chip to reverse a chip,and to produce the same chip?

it might be possible to create a different design that performs the same 
(or sufficiently similar) operation, however it will almost certainly 
not be the same design as the original (apart from in a very simple case).

Even take the simplest case of a inverter.  If you were to design this 
from the silicon up, do you think it would be the same as something from 
TI etc?  How about if you knew exactly what kind of process they used, 
there's just so many different options still.

Copying the design just isn't viable.  Unless you really have the time 
and money to invest in getting the packaging open, and inspecting the 
actual silicon itself.

Article: 99540
Subject: Re: ERROR:NgdBuild:604
From: "Mich" <michiel.vanderlinden@gmail.com>
Date: 26 Mar 2006 04:01:31 -0800
Links: << >>  << T >>  << A >>
Hi

I have added it in the pao file and placed the sub module first

lib IP_COMP_v1_00_a teller4 vhdl
lib IP_COMP_v1_00_a user_logic vhdl
lib IP_COMP_v1_00_a IP_COMP vhdl

I still get the same error.

Is there something I do wrong?

Greets
Michiel


Article: 99541
Subject: Re: need help,test on Spartan3 starter kit
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sun, 26 Mar 2006 14:17:05 +0200
Links: << >>  << T >>  << A >>
preet schrieb:
> Hi, Please someone help me.
> 
> As a school project i am designing a Viterbi Decoder, now i have to test it on FPGA.
> 
> Please can you give me the guidelines or the pointers to how can i actually test the code.
> 
> Someone gave me a clue that using RS232 will help. But, i have no clue, how to transfer the data from my PC to FPGA and how to receive the output. In which format am i supposed to send the data, which data file? What all steps are needed?

For such live test, I used the famous Picoblaze to make a local teminal 
controler inside the FPGA. Add the RS232 UART from xapp 233?? and you 
are done. Now just program the Picoblaze to receive data from RS232, 
feed the Viterbi decoder and send the output from the decoder back to 
the PC. This will need probably some block rams for data storage.

Regards
Falk

Article: 99542
Subject: Re: OpenSPARC released
From: Allan Herriman <allanherriman@hotmail.com>
Date: Sun, 26 Mar 2006 22:47:13 +1000
Links: << >>  << T >>  << A >>
On Sun, 26 Mar 2006 10:09:52 GMT, mk<kal*@dspia.*comdelete> wrote:

>On Sat, 25 Mar 2006 22:59:57 -0600, "Ira Baxter"
><idbaxter@semdesigns.com> wrote:
>
>>I found this in  design/sys/iop/sparc/ifu/rtl/sparc_ifu_rndrob.v
>>
>>   ....
>>   assign  next_pv[0] = pv[0] | reset;
>>
>>   dff #4  park_reg(.din  (next_pv),
>>      .clk  (clk),
>>      .q    (park_vec),
>>      .se   (se), .si(), .so());
>>
>>   ....
>>
>>I don't see how the #4 is legal is Verilog 2001.
>>Can someone explain to me under what it means,
>>and under what circumstances this is legal?
>>Is this construct part of Verilog 2001, or is it vendor specific?
>
>Looks like a parameter override. The standard specifies paranthesis
>around the number but I bet if only one number is used most tools
>accept one without a number. Is there parameter for the module "dff"?

No, the #4 matches the syntax of a delay specification.  Parameter
overrides alway have the ().

Delays specifications are legal between the "module" id and the
instance name in an instantiation of a gate primitive or UDP, but not
in a module instantiation.

dff isn't a gate primitive, so it must be a UDP.  However, it seems
that the standard only allows ordered parameter assignments and not
named parameter assigments for UDPs.


Therefore the code isn't legal according to the standard.

This seems to be a mistake in the standard.  Does anyone know why it
doesn't allow named parameter assignments for UDPs?


Regards,
Allan

Article: 99543
Subject: Re: XST takes unusually long
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Sun, 26 Mar 2006 13:03:41 GMT
Links: << >>  << T >>  << A >>
On a sunny day (25 Mar 2006 19:20:44 -0800) it happened "Brian Davis"
<brimdavis@aol.com> wrote in
<1143343244.771414.32680@z34g2000cwc.googlegroups.com>:

>>The older code was getting synthesized in around 20 mins, but the new
>> code takes hours together to get synthesized, and so does the PAR.


ZE xsT programmmmers forGot to Comment oud ze lunch break in ze code.

Article: 99544
Subject: Re: chip reverse engineering
From: Tank <webmaster@tankstage.co.uk>
Date: Sun, 26 Mar 2006 13:59:49 GMT
Links: << >>  << T >>  << A >>
In message <1143359330.846497.90580@j33g2000cwa.googlegroups.com>
          mikeotp@gmail.com wrote:

> regards
> 
> is it possible from the driver of a chip and pin assignment
> 
> of a chip to reverse a chip,and to produce the same chip?
> 
>          
> any positive suggestion is welcome
> best regards to you all
> 
On a similar note, is it possible to get back to the design from a .bit file?

Cheers

Tank
-- 
webmaster@tankstage.co.uk   
Iyonix PC

Article: 99545
Subject: Re: chip reverse engineering
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 26 Mar 2006 16:08:05 +0200
Links: << >>  << T >>  << A >>
"Tank" <webmaster@tankstage.co.uk> schrieb im Newsbeitrag 
news:9d55af0d4e.tank@tankstage.co.uk...
> In message <1143359330.846497.90580@j33g2000cwa.googlegroups.com>
>          mikeotp@gmail.com wrote:
>
>> regards
>>
>> is it possible from the driver of a chip and pin assignment
>>
>> of a chip to reverse a chip,and to produce the same chip?
>>
>>
>> any positive suggestion is welcome
>> best regards to you all
>>
> On a similar note, is it possible to get back to the design from a .bit 
> file?
>
> Cheers
>
> Tank
> -- 
> webmaster@tankstage.co.uk
> Iyonix PC

that *IS* possibe, but usually VERY time-consuming and from that point of 
view un reasonable.

Antti 



Article: 99546
Subject: Re: VHDL LUT
From: "chris_ivan" <chris.ivan@gmail.com>
Date: 26 Mar 2006 06:33:20 -0800
Links: << >>  << T >>  << A >>
hi,

If I were you, I prefer using synchronous LUT to get a clearer result
using proces. So the change of the output signals are controlled by
rising/falling edge of a clock signal. If you wanna use concurrent one,
use D flip-flop to buffer the output signals, and to read the signal,
use such a clock signal. I think it gives you better result. The
drawback is the result doesn't come up instantly, delayed 1 clock
period. Hope this help.

Ivan


al99999 wrote:
> Hi,
>
> Can anybody please tell me what is wrong with the following code?  In
> post-translate simulation there are a few unexpected short pulses.
> Thanks,
>
> Alastair
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity divcontrol is
>    port (
> q      : in    std_logic_vector (7 downto 0);
>           pulse, shift, rstout,ledinc,ledread: out   std_logic
>         );
> end divcontrol;
>
> architecture BEHAVIORAL of divcontrol is
> begin
>
> with q select
>    pulse <= '1' when x"00",
> 	'1' when x"14",
> 	'1' when x"28",
> 	'1' when x"3C",
>    '0' when others;
>
> with q select
>    rstout <= '1' when x"4D",
>    '1' when x"4E",
>    '1' when x"4F",
>    '0' when others;
>
> with q select
>    shift <= '1' when x"03",
> 	'1' when x"04",
> 	'1' when x"17",
> 	'1' when x"18",
> 	'1' when x"2B",
> 	'1' when x"2C",
> 	'1' when x"3F",
> 	'1' when x"40",
>   	'0' when others;
>
> with q select
>    ledinc <= '1' when x"49",
> 	'1' when x"4A",
> 	'1' when x"4B",
> 	'1' when x"4C",
>   	'0' when others;
>
> with q select
>    ledread <= '1' when x"41",
> 	'1' when x"42",
> 	'1' when x"43",
> 	'1' when x"44",
>   	'0' when others;
> 
> 
> end BEHAVIORAL;


Article: 99547
Subject: Re: OpenSPARC released
From: chrisbw@gmail.com
Date: 26 Mar 2006 07:06:10 -0800
Links: << >>  << T >>  << A >>
You're right. In some designs there is a weak correlation between
Verilog line count and gate count. But unless you take that to an
extreme, this is still quite a large design.


Article: 99548
Subject: Re: need help,test on Spartan3 starter kit
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Sun, 26 Mar 2006 07:29:30 -0800
Links: << >>  << T >>  << A >>
preet wrote:

> As a school project i am designing a Viterbi Decoder, now i have to test it on FPGA.
> Please can you give me the guidelines or the pointers to how can i actually test the code.

I test code by writing a testbench
and running a simulation to
stimulate inputs and verify outputs.
This might take a long time, but
trial and error synthesis
on the bench will take longer.

> Someone gave me a clue that using RS232 will help. But, i have no clue, how to transfer the data from my PC to FPGA and how to receive the output. In which format am i supposed to send the data, which data file? What all steps are needed?

Once the code is working in simulation,
you need some way to stimulate inputs
and verify outputs in hardware.
The best way to do this depends on what devices
are already connected to the fpga on your board.
Using a terminal emulator program and a serial port
is one way to interface to a PC

      -- Mike Treseler

Article: 99549
Subject: Re: this JTAG thing is a joke
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 26 Mar 2006 15:46:28 GMT
Links: << >>  << T >>  << A >>
henk <henk@mediatronix.com> wrote:
>Brannon wrote:
>> 1. Support for a lot of chips, say 2048 of them.

>Have you considered an approach like the National SCANSTA112?

http://www.national.com/ds.cgi/SC/SCANSTA112.pdf




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