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Good explanation. Xilinx uses the drawn dimension, the most conservative number. So when we say "130 nm", Leff is an even smaller number... Peter Alfke ===================== MR wrote: > No it's not the "effective gate length", its the "drawn gate length". > > As the original poster can probably see by now, there never has > been total agreement on this question. The most widely accepted > definition is as I have stated, the "drawn gate length". But, > there are certain manufacturers who from time-to-time like to > spout-off that they have the most advanced technology... then > they give you the "effective channel length". > > Definitions: > > Drawn Dimensions > - what the design rules tell you, and what you draw in the layout. > > Mask Dimensions > - what ends up physically on the mask, after some size adjustments > to compensate for fabrication. > (there are manufacturing variations involved) > > Physical Dimensions > - what ends up on the wafer > (more manufacturing variations here too) > > Effective Channel Length > - what an electron (or hole) sees... after processing, including > the shortening of the channel due to depletion around the S/D. > (that's what it's been called for the last 25 years at least) > > When in doubt, ask... is that the drawn dimension or the physical > gate length? They are usually pretty close. Don't ever accept > the effective channel length dimension. > > Jay wrote: > > > This is the CMOS process technology used to manufacture that part. > > Specifically it is the effective gate length of the transistors that > > make up all the circuitry on the die. > > > > Regards > > > > "xtalca" <xtalca@hotmail.com> wrote in message news:<anrbht$gp6u2$1@ID-159866.news.dfncis.de>... > > > >>hi all, > >> all ic manufacturers says that there IC is made of some .13 micron or .18 > >>micron technology. what exactly this dimension correspond to ? > >>Article: 47926
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<y4%m9.1568$pk1.28677390@newssvr21.news.prodigy.com>... > Anyhow, just a thought. Check out the Silicon Image site for more details: > http://www.siimage.com/home.asp Good luck getting tech support from them. Unless, of course, your e-mail address ends in dell.com, or something. If you call their main phone number, you get dumped into a black hole. I tried to get a data sheet from them for one of their ATAPI controller chips, and the person at the switchboard didn't even know where to route my call. I finally got ahold of someone in sales, who told me that my REP (!) would have the datasheet. So, I called the rep, who said, "Huh?" A couple of days later, the rep's field apps guy called, and I told him that I wasn't going to even consider using one of their products in a design. I said that if I designed in a complex part without a direct line to vendor tech support, my boss would chew my ass all along I-8. Which is true. --apArticle: 47927
itsme,
While I don't use VHDL myself (I use Verilog.), I have some experiences
dealing with trying to get XST to pack FFs into IOBs.
You are absolutely correct that setting "Pack I/O Registers into IOBs"
synthesis option to "Yes" should always pack IOB FFs into IOBs, but for
some reason, XST doesn't always do the necessary duplication to allow
the packing.
You are also correct that if output or tri-state enable IOB FF doesn't
have fan-out of 1, that register cannot be pushed into an IOB.
I don't have a Virtex-II datasheet right now, so I am not 100% sure, but
the use of Clock Enable should not cause any problems when dealing with
IOB, so you should feel free to use it.
So, in order to push FFs into IOBs, "normally" (Not always though.) you
need to get XST to duplicate the FFs so that you get FFs with fan-out of
1.
MAP (The tool that runs after NGDBUILD.) has no power to duplicate IOB
FFs even if you wanted it to, and that's a job of the synthesis tool.
Here are the instructions on how it can your problem can likely
be solved.
First of all, write a synthesis constraint file for XST.
The syntax of the XST constraint file is explained in XST's manual, so
you may want to download a copy of it from Xilinx.
____________________________________________________________________
begin TEST_OUT_FF
attribute offset_out_after of P_DR_BANK : signal is "5ns";
end TEST_OUT_FF;
____________________________________________________________________
Cut and paste the above code to a text editor, and save it as
"TEST_OUT_FF.cst". (I don't care about the file name.)
Go to XST's properties, and click "Synthesis Options" tab.
Click "Synthesis Constraints File," and specify the path
"TEST_OUT_FF.cst" is located.
Also, "Pack I/O Registers into IOBs" to "Auto" instead of "Yes" for the
time being.
Synthesize your design, and make sure XST correctly recognized
"attribute offset_out_after of P_DR_BANK : signal is "5ns";
"
The synthesis log file will display that it recognized the above
synthesis constraint, or you should get a warning message.
If everything goes right, near the end of synthesis, XST should tell you
that it duplicated FFs to satisfy the "Pack I/O Registers into IOBs"
option.
If what I wrote didn't help you (XST didn't mention that it duplicated
IOB FFs.), change "Pack I/O Registers into IOBs" option to "Yes," and
replace the synthesis constraint file with the following one.
____________________________________________________________________
begin TEST_OUT_FF
attribute offset_out_after of P_DR_BANK<1> : signal is "5ns";
attribute offset_out_after of P_DR_BANK<0> : signal is "5ns";
end TEST_OUT_FF;
____________________________________________________________________
Resynthesize the design, and when doing so, make sure the
constraint is correctly recognized by XST.
If neither synthesis constraint file worked, try changing the "5ns" to
something smaller (i.e., "3ns") or larger (i.e., "7ns").
The reason "Pack I/O Registers into IOBs" option should be
"Auto" rather than "Yes" and you have to specify offset_out_after's
value is that, I have observed that if they aren't like that, XST
doesn't seem to want to duplicate FFs for some reason.
At this point, I believe it is to your advantage to see whether
or not the synthesis did indeed duplicated IOB FFs.
Assuming that you are using ISE 4.x (4.1 or 4.2), you are might be aware
that XST no longer generates an EDIF netlist of your design, and instead
generates an encrypted NGC netlist.
This has been a huge problem for some power users who want to see what
XST did when it synthesized the design.
To workaround this nasty problem, and to obtain an EDIF netlist, take a
look at this link.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=aceeac%249fj%241%40newsreader.mailgate.org
In case you are using ISE 4.2, you can obtain an EDIF netlist
from ISE's GUI.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=ad2sbv%248u0%2401%241%40news.t-online.com
Wondering why ISE 4.x's XST doesn't normally generate an EDIF
netlist? Here is an answer from a Xilinx employee.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=3D77B576.7166323B%40xilinx.com
When you take a look at the EDIF netlist, if XST correctly
duplicated the FF, you will see something like P_DR_BANK_0 and
P_DR_BANK_0_1 (Same thing will also apply to P_DR_BANK_1. There should
be P_DR_BANK_1 and P_DR_BANK_1_1).
One of the FF should be a complete duplicate that has fan-out of 1.
After you make sure the FFs were duplicated, run NGDBUILD and MAP, and
when running MAP, "Pack I/O Registers/Latches into IOBs" should be "For
Outputs Only" or "For Inputs and Outputs."
MAP's report or floorplanner can tell you if the FFs were indeed pushed
into IOBs.
Hopefully, the above instructions will help solve your problem,
and let me know if it worked or not.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
itsme wrote:
>
> Hello,
> here is my little "test design"
> All I want is that all Outputs P_DR_BANK are packed into registers of an IOB
> in a Virtex2.
> However all Outputs are Registers only P_DR_BANK(0) is mapped in a IOB
> register.
> P_DR_BANK(1) uses a Slice FF.
> I found in the FPGA Editor that the Register which should be
> placed in the IOB has a feedback. So it can't be
> moved in the IOB.
>
> In my VHDL code (see below) I have some conditional assignments
> to the output signal and in some cases it should hold
> its old value.
> How can I tell the XST not to use the output of
> a register also as input?
> It should rather use the ClockEnable auf the Register which is
> also available in IOBs.
> I thought the XST Option - Pack I/O Registers into IOBs
> will do that.
>
> please help
> peter
>
> ----------------------------------------------------------------------
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity TEST_OUT_FF is
> Port ( CLK: in std_logic;
> REQUEST: in std_logic;
>
> --- PAD Signals, should be in IOB Register
> P_DR_BANK : out STD_LOGIC_VECTOR (1 DOWNTO 0)
>
> );
> end TEST_OUT_FF;
>
> architecture Behavioral of TEST_OUT_FF is
>
> -------------------------------------------------------
> ---------------------------------- State machine
> type STATE_TYPE is (S_Idle, S_Active, S_Access);
>
> signal State: STATE_TYPE;
>
> BEGIN
> ---------Statemachine
> FSM:process(CLK)
> begin
> if Clk'event and clk='1' then
>
> P_DR_Bank(0)<='0'; -- Use this to get Register in IOB !! Why?
> -- P_DR_Bank(1) with no IOB Reg!!
> case State is
> ------------------
> when S_Idle =>
> if Request='1' then
> State <= S_Active;
> end if;
>
> -------------------
> when S_Active =>
> P_DR_Bank <= "10";
> State <= S_Access;
>
> -------------------
> when S_Access =>
> P_DR_Bank <= "01";
> State <= S_Idle;
>
> when others =>
> State <= S_Idle;
>
> end case;
> end if; -- CLK
> end process;
>
> end Behavioral;
Article: 47928
A while back we considered USB in the FPGA, but when push came to shove, it was
cheaper to use an external USB chip. In our case, it was the original USB, and
we used a National Semi chip, I think it was a USBN9603 which has both the
controller and the PHY in one package for about $2.25. When we sized the USB
for putting in the FPGA we still needed an external PHY, and it would have
pushed us into a larger part costing far more than the off the shelf chip. I
don't know if the situation is similar for USB2 or not, although I suspect that
it is.
Theron Hicks wrote:
> Hello,
> I am developing an instrument that is currently communicating over a
> special high speed parallel board. The data rate is 6.4 million 8 bit words
> per second. The board works great but it costs in excess of $1600 US per
> copy. It also occupies a full sized PCI slot. We are considering
> implementing an alternative I/O arrangement such as USB2 or ethernet
> (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some
> other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if
> absolutely necessary, Virtex2).
>
> Thanks,
> Theron
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47929Brett Cline wrote: > - The product will duplicate resources when needed depending on the > constraints. It is quite possible that having an additional multiplier to > meet the performance goal uses less area than the muxing needed to reuse the > existing ones. The product will figure that out. What if it's wrong? The C++ to VHDL converter has no idea how long a route is, so how can it make a wise decision on sharing or duplicating logic? Remember that the longest path in a FPGA design is often 2/3 or more (66%+) routing delay... > And we can get there in 20% of the time that it takes > you to get there by hand. Amusing. Would this be for all designs? > - What advantage do you believe that you will have using any C-based flow? > Why would you move from VHDL for a language that is not a lot higher-level > than RTL? Handel-C might be enough better of "RTL" than VHDL to make it worth using. Maybe. For some designs, surely not all. And if it's not, simulation might be enough easier to make up the shortfall. Again, maybe. Or maybe not. -- Phil HaysArticle: 47930
Brett, > In every case so far, we met or > beat the performance targets for the device. In most cases we will beat area > as well, but not all. That's about the most amorphous claim I've ever heard. Of what significance is this claim? What's important, is how does it compare with OTHER technologies, not some arbitrary target! > This is simply a progression in hardware design much as a C compiler was > a progression beyond assembly in software. Er, huh? C is merely a software programming language, how is that a "progression in hardware design"??? I highly disagree with that statement, and see no basis for it. There are already hardware HDLs that work reasonably well, this is NOT a progression from instantiating things gate by gate (assembly language), as that progression has already been made long before this. > ...the value of time to market > dramatically overshadows most other costs in the process. Yes, but unreal expectations made by unrealistic claims of tools and wasted time trying to force fit a tool to do something it just simply can't is not going to get one to market faster. The thing to do is set honestly based claims and expectations, as well as honest comparisons with other technologies. Not amorphous claims and marketing fluff. > Clearly the design > must meet timing - clearly it must be in some tolerance of area -- but if > you can save 3,6, or more months to market -- what is the savings (or gain) > there? If, if....if. What if the same design could have been done by someone using another design methodology that would fit in a part for 1/3rd the cost? > For the "Show Me" part, let's talk about that - the proof is in real > results. Yes, the key word is "real". I know this sounds a bit nasty, but what do you expect with all the snake oil that has been peddled over the years with HDLs, much less now with stuff like this. Granted, HDLs are now a viable design entry methodology, but...they have always been designed TO be hardware design entry tools, and lots of time has passed for them to become refined to the point they are today. AustinArticle: 47931
Gaga: I am the Aerospace sales manager for Actel covering Texas. Actel has a very large portfolio of products which have been fully space qualified for many years. We have radiation hard and radiation tolerant devices with TID specs up to 300Krads, latch-up and SEU immune. Actel's devices are designed into virtually every spacecraft launched in the last few years. My contact data is listed below and please feel free to let me know if there is anything we can do for you. Thank you, Jeff Wetch Aerospace Sales Manager Actel Corporation phone: 303-420-4335 email: jeff.wetch@actel.com "Gaga" <blah@blah.org> wrote in message news:al5bim$f9o$1@news.tamu.edu... > I am a graduate student at Texas A&M University. We are building a fpga > based device for space applications. Originally the plan was to use the > virtex qpro line. But some people we talked to suggested that actel line > would be better in terms of radiation characteristics and reliability. Does > any one have any previous experiences with either brands? Or if you are from > xilinx or actel do you know whom I should contact to acquire further > information on this matter? > >Article: 47932
Heheh i tried quite a bit to find 4.1... no luck.
Xilinx website says they will have a "classics" section soon with old
webpacks.
It doesnt matter now anyways. I completely commented out the 3 lines:
#if { !$xcpldFitDesFastConnectUIM } {
# lappend Options "-nouim"
# }
thus always enabliing FastConnect... and removing the errors. It implements
now!
Tony
"Spam Hater" <spam_hater_7@email.com> wrote in message
news:f922qu8330mhc44dppi8scu4v1eg5ld4at@4ax.com...
>
> Hi Tony,
>
> This is probably not the answer you want, but...
> See if you can find a copy of version 4.1.
>
> I have not heard any good things about version 5 yet. My big worry
> stems from the service pack arriving before the product.
>
> SH7
>
>
> On Sun, 06 Oct 2002 01:51:01 GMT, "Tony M" <tonym_98@hotmail.com>
> wrote:
>
> >Hey all...
> >
> >In the past I've used ActiveHDL (great product!) But this semester I had
a
> >tighter budget so I'm giving the Xilinx WebPack ISE 5.1i + Service Pack 1
a
> >try.
> >
> >I have a XC95108 CPLD next to my Virtex chip and need to download some
> >simple VHDL to the CPLD... but ISE won't Fit the code...
> >
> >here's the error I get:
> >Started process "Fit".
> >
> >can't read "xcpldFitDesFastConnectUIM": no such variable
> > while executing
> >"if { !$xcpldFitDesFastConnectUIM } {
> > lappend Options "-nouim"
> > }"
> > invoked from within
> >"if { [string equal $p_DevFamily xc9500] } {
> > if { !$xcpldFitDesFastConnectUIM } {
> > lappend Options "-nouim"
> > }
> > switch -- $xcpldFitDesLocal..."
> > (file "C:/Xilinx/data/projnav/scripts/_cpldfitrun.tcl" line 95)
> >
> >Now... I disabled the FastConnect optimization routine in the options and
it
> >still gives that error. What can I do? I'm not familiar enough yet with
> >ISE to figure this out on my own!
> >
> >Thanks,
> >Tony
> >
>
Article: 47933"xtalca" <xtalca@hotmail.com> wrote in message news:<anrbht$gp6u2$1@ID-159866.news.dfncis.de>... > hi all, > all ic manufacturers says that there IC is made of some .13 micron or .18 > micron technology. what exactly this dimension correspond to ? Hi, Actually this is the size of a transitor in that IC ? Since all circuits is build using the transistors, the transistor size will decide about the packing densitiy and the size of the chip. Best regards, MuthuArticle: 47934
"Andy Peters" <Bassman59a@yahoo.com> wrote in message news:9a2c3a75.0210071528.17ed50f2@posting.google.com... > > Anyhow, just a thought. Check out the Silicon Image site for more details: > > http://www.siimage.com/home.asp > > Good luck getting tech support from them. Unless, of course, your > e-mail address ends in dell.com, or something. > > If you call their main phone number, you get dumped into a black hole. ... That certainly doesn't match my experience with them. -- Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 47935
Mike Treseler <mike.treseler@flukenetworks.com> wrote in news:3D949722.2080001@flukenetworks.com: > Michael Tornow wrote: > > >> I have checked this vhdl code with Leonardo Spectrum too. No errors >> were found. > > > If you have leo available, use that to make a .edf for Quartus. > Quartus vhdl synthesis is a work in progress. > > Leo will accept, with warning, component instances for vendor > functions, but consider writing your own code. I do it this way but it produces the same error... Do you know an arithmetik vhdl-library, where pipelining is available? My work is in the early beginning(proof of concept) I don't want to waste time with writing arithmetik function for something that maybe dosen't fit to my problem... Michael TornowArticle: 47937
Hi, i am trying to implement a simple algorithm into a FPGA. I intent to use A C A D E M I C C A D T O O L S. Already i have found available tools from the UCLA and from Toronto FPGA Reseach group. The main dissadvantage for both of them is that they don't have full design flow. I mean that they don't have synthesizer and bitstream generator. I would like to know if anyone has found any fpga tools, apart of two that mentioned above, that could help me. The tools must be based on O P E N S O U R C E. P.S. If it is possible please response to: ksiop@ee.duth.gr Thanks in advanceArticle: 47938
Kostas Siozios <ksiop@ee.duth.gr> wrote: : Hi, i am trying to implement a simple algorithm into a FPGA. : I intent to use A C A D E M I C C A D T O O L S. Already i have : found available tools from the UCLA and from Toronto FPGA Reseach group. : The main dissadvantage for both of them is that they don't have full : design flow. I mean that they don't have synthesizer and bitstream : generator. : I would like to know if anyone has found any fpga tools, apart of two : that mentioned above, that could help me. : The tools must be based on O P E N S O U R C E. Icarus Verilog (http://www.icarus.com/) has some support for Synthesis on Xilinx parts Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 47939
Muthu wrote: > > Hi, > > I am using a Logic which is generated from Xilinx's coregen. I am > usign that logic in my design as a black box. In synpify_pro we have > to mention the Timing Modles of a black box to perform the correct > timing analysis. > > So, How can i get the stamp files (.mod,.data) for that coregen logic. > > Best regards, > Muthu I think it is impossible to generate STAMP models for a part of the chip, with Xilinx technology. Xilinx tools generate STAMP models only for the complete FPGA. I don't know the case for other technologies. UtkuArticle: 47940
Uwe Bonnes wrote: > > Kostas Siozios <ksiop@ee.duth.gr> wrote: > : Hi, i am trying to implement a simple algorithm into a FPGA. > > : I intent to use A C A D E M I C C A D T O O L S. Already i have > : found available tools from the UCLA and from Toronto FPGA Reseach group. > > : The main dissadvantage for both of them is that they don't have full > : design flow. I mean that they don't have synthesizer and bitstream > : generator. > > : I would like to know if anyone has found any fpga tools, apart of two > : that mentioned above, that could help me. > : The tools must be based on O P E N S O U R C E. > > Icarus Verilog (http://www.icarus.com/) has some support for Synthesis on > Xilinx parts > > Bye Also, in GNU distribution is Alliance (not Xilinx), developed by a French site (probably a university?) http://www-asim.lip6.fr/alliance/ I am aware of this tool since 1997. There is continuous development effort on it. In GNU distribution directory: http://www.gnu.org/directory/design/cad/alliance.html UtkuArticle: 47941
Thanks for the comment. To be honest, we didn't solder the pins, one by one, under that microscope. What we did was to order the PCB manufacturer to put a lead-tin coating on all exposed coopers. Now, we just glued the chip on its place and the used hot air on the pins to melt the coating layer of the pads (and apparently the chip pins are coated too). In the end, we finished soldering the whole chip without any solder :) In the final phase, we just checked all pins under that microscope.... "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:ansf0o$guqi1$1@ID-84877.news.dfncis.de... > "Arash Salarian" <arash.salarian@epfl.ch> schrieb im Newsbeitrag > news:3da1511a$1@epflnews.epfl.ch... > > I remember doing a FPGA based project with 10K100E parts from Altera in > > QFP208 packages on a two layer board. We had to solder the pins using a > > microscope but finally it was running like a charm! Using PROM did not add > > To solder a 0.5 mm pitch QFP you dont need a microscope. Just place it > carefully, then use a big amount of solder on a big tip and flush the pins. > Yes, flush them. The solder-flux will make the trick. After removing the > unneeded solder with solder sucker, check the pins with a magnifiying glas. > > -- > MfG > Falk > > > >Article: 47942
Kolja Sulimma wrote: > Here is a schematic of xilinxs parallel download cable: > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html > > As you can see, you need to enable the output with CTRL=0. > To read TDO you need to set PROG=1. > > The voltage levels are never the less very problematic, as the typical > PC parallel port drives the signal quickly to about 1.5V. The > Following slope to 5V is extremely slow with a lot of noise added. If > the 74HC125 is powered by 3V you are in trouble. > > Kolja Sulimma > > That's an interesting comment since its 180 degrees reversed from my experience! We build the P-III logic onto the board so we can just use a standard Centronics extension cable. In the original version we used 74LS125 parts powered from 5V and had no end of trouble programming XC18V04s (and just very occasionally XC95K CPLDs)! In fact allowing for the Schottky drop and the ATX PSU's 5.1V it was about 4.8V. Removing the Schottky made the problem worse. Reverting to HC125s powered from 3.3V "fixed" it.Article: 47943
rickman wrote: > > This can be a tough one. There should be guidelines on how to encourage > XST to use the clock enable. But if the entire logic block fits into a > single LUT, it may not want to use the CE since that would use an extra > LUT. > > In the end you may need to use a pair of FFs, one in the IOB and one in > a CLB. You can design the combinatorial logic separate from the > sequential logic so that both FFs use the same combinatorial signal as > the D input to the FF. Then only the CLB FF will need to be used for > the feedback and the other FF can be pushed into the IOB. > As rickman says this is a tediously perennial problem and the fix is the same one I normally use with the addition of some sort of directive to tell the synthesis tool to *not* optimise away one of the FFs. For Synplify the directive is "syn_preserve=1", don't know what it is for XST. If this fails to work there's one other thing you can try which is to feed some signal into the logic equations that comes from outside the module being synthesised and is always set to 1 or 0. Very ugly & kludgy but it does the job sometimes.Article: 47944
The ALTERA Mercury family doesn't specify jitter on the LVDS outputs. The next close family Stratix, specifies 200ps from one slope to the next which appears unlikely, a legal statement it seems. Did anyone working with Mercury measure the actual jitter ? Since that measurement isn't trivial, not even with a 16 GS/s scope, I'd be happy with a phase noise figure obtained by looking at the sidebands of a spectrumanalyzer when outputting an infinite 0101010101010101 sequence. We'd input 400MHz or so and have the PLL generate 800 or 1200 from that, meaning an integer multiply by 2 or 3. Thanks Rene Tschaggelar -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 47945
Hi, I wonder if it is possible to allocate I/O pins in VHDL submodule. For example, I'm going to have SRAM interface, parallel port interface, TV out, ADC etc, and I already know which pins are going to be used by which modules. I would like to assign IO pins within modules so that when I include one in my top-level design I don't have to pull all these IO lines all the way up to the top and assign pins to them again. I tried to instantiate IOPAD primitives directly and assigning LOC constranis to them but it does not seem to work. Synthesis refuses to compile modules with no outputs and mapper does not know about IOPADs (even though they are described in Library Guide). It knows about IOBUFs but it removes them as reduntant if I leave the output unconnected. If I want the impossible, can I at least create a global package and define all my I/O signals there along with their LOC attributes? My board has 8 identical pin headers. Ideally I would like to define 8 global ports and assign pins to them once and forever. Then, when I want to instantiate for example ADC module I would tell it which port to use. Is there a way to do it? On similar topic, is it possible to force ISE to treat any unconstrained IOs as an error? Also stop it from producing designs for all but top-level entries? Several times I nearly blew my board because wrong file was selected in the project view when I clicked "implement design". Thanks DmitriArticle: 47946
Hi Peter, I would go for a small Spartan2 (or 2E 1.8V instead of 2.5V). The price, as John said, is something like $10-$15 which is not much and if you include an OTP ROM (< $3) you are around $13-18. I agree that the price of a 9500 is smaller than that (I had a look and you could save ~30%) but if you can save the PROM using FLASH in you card for example, or if you want to upgrade your system later on and you run out of resources, or if you have different images for a chip... Also Lattice devices are well known in the CPLD arena, they are always claiming to be the leaders in that field. Regards. Ulises Hernandez Design Engineer ECS Technology Ltd. www.ecs-tech.com "Peter Hiscocks" <phiscock@pascal.ee.ryerson.ca> wrote in message news:anllh2$bcg$3@ns2.ryerson.ca... > We're building a function generator that uses a 24 bit Direct Digital > Synthesis oscillator. It will fit into an FPGA with no problem, but I'd > really like to shoehorn this thing into a PLD to avoid the need for a boot > ROM chip and to keep the cost down. > > The Xilinx 9000 series PLD's I've tried won't do because of the requirement > for a 24 bit adder. Anyone have any suggestions of other chips I should > investigate for this? > > Thanks for the help - > Peter > > -- > Peter D. Hiscocks > Department of Electrical and Computer Engineering > Ryerson University, > 350 Victoria Street, > Toronto, Ontario, M5B 2K3, Canada > > Phone: (416) 979-5000 Ext 6109 > Fax: (416) 979-5280 > Email: phiscock@ee.ryerson.ca > URL: http://www.ee.ryerson.ca/~phiscock >Article: 47947
Hello, is there somewhere a reference design or some information about booting a SRAM-based FPGA via a USB interface? I am thinking to use one of Cypress's USB interfaces to programm a Spartan 2 via JTAG. This would be a very convenient solution for further programm updates. Any suggestions ? Regards, Jens NiemannArticle: 47948
Jens Niemann <Jensniemann@gmx.de> wrote: > Hello, > is there somewhere a reference design or some information about booting a > SRAM-based FPGA via a USB interface? > I am thinking to use one of Cypress's USB interfaces to programm a Spartan > 2 via JTAG. This would be a very convenient solution for further programm > updates. > Any suggestions ? Look at www.trenz-electronic.de; their prototype system provides this in some way, i.e. they use the FPGA itself as a USB interface and have logic in it to load the FPGA configuration into an onboard flash ROM. The boot code that programs the FPGA itself as a USB device is in a protected part of the flash itself. This is reasonably fast. Holger -- Please update your tables to my new e-mail address: holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection)Article: 47949
Hi! Does anyone have experiences with above topic in ISE 4.x or 5.x? How about simulation with ModelSim? Thanks very much! Nico
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