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Why is logic partioning considered better on pre mapped design only and not on post mapped netlists ..... one reason i can see is that probbaly clustering will give good results on pre mapped design ..... any inputs >??Article: 107801
Thanks to KJ and Antti for your prompt answers!!! I see - I will need a enable signal for each direction, because I want a synthesizable code not a simulation (I thought this is easy, just a connection :-( ). the PCA9515 is a really nice bidirectional level converter, but I think he has a enable signal, too. Not a external direction signal, but internally generated out of weak low (the output of the PCA9515) and hard low (if the input is low). Manfred "KJ" <Kevin.Jennings@Unisys.com> schrieb im Newsbeitrag news:1157109054.812511.131460@b28g2000cwb.googlegroups.com... > > Antti wrote: >> > >> > What you probably need to add is the concept of an output enable for >> > both port1 and port2 and only drive the outputs when that output is >> > enabled... >> > >> > port1 <= port2 when (port1_output_enable = '1') else 'Z'; >> > >> > KJ >> >> KJ >> >> bidir connections between to io's are sometimes possible also when >> no enable signal exists, see NXP's I2C extender as one example >> >> http://www.nxp.com/pip/PCA9515DP.html > > Yes, and an even simpler example of a bi-directional connection between > two I/Os with no enable or direction signal is a resistor. > > Since I wasn't quite sure exactly what the original poster was trying > to do, I mentioned "What you probably need...." on the assumption that > he is trying to come up with synthesizable code targetting some > FPGA/CPLD or such (in which case I believe he will be needing the > enable). > > If instead the poster was interested in a non-synthesizable simulation > model that connects two things bi-directionally without a 'direction' > or 'enable' signal (i.e. like a resistor or the part you linked) than > he will be wanting a different code entirely. > > KJ >Article: 107802
John Larkin wrote: > There's nothing wrong with a cap being inductive as long as the > inductance is low. If somebody made a 10 farad 0603 cap, its SRF might > be a kilohertz or something, but having more C, and operating above > srf, doesn't make it any worse a high-frequency bypass. I figure the > more C, the better for any given size. Another country heard from! John, no one is saying more C is not better than less C. The question is how do you provide *enough* C to do the job in the most cost effective manner and be sure you have done the job right? My point about the caps being inductive is that where a cap is near its SRF, the impedance is much lower than either the capacitive curve or the inductive curve. If you draw the impedance line for the equivalent inductance and for the pure capacitance, they approximate the true impedance of the part anywhere that is not near the SRF. So when I talk about the region where the cap is inductive, I am talking about the impedance rising to a point that it is no longer low impedance. > PCB planes are a big, lossy, many-nF capacitors (or, if you prefer, > big, lossy, super-low Z transmission lines), and adding lots of, say, > 0.33 uF 0603 caps just makes it better. All this stuff about Spicing > staggered srf nulls is silly, given that the caps aren't out in space, > they're soldered to the huge low-z lossy power planes. Well, I didn't know that "silly" was a technical evaluation. I guess if you are designing a board for Jerry Lewis you should calculate the SF (Silly Factor) as part of your evaluation. I think you are proving my point. The caps are on a plane that will resonate with the caps. So you can't just say adding caps will lower the impedance across the bandwidth. In fact, however, adding a single value of capacitor to a power plane is likely to produce a parallel resonance (with a higher impedance than the plane by itself) at a frequency that you care about. This can be mitigated by the ESR of the caps which will damp the parallel resonance. The data I saw showed that using 0603 caps of 0.1 uF will produce a pretty healthy impedance peak in the 50-100 MHz range, of course depending on the details of your board. This is a bad place to have an impedance rise when you are looking for the caps to lower the impedance. A lot of people here seem to think that you can analyze this on paper or with words. I have seen the simulation results and the measurement results of real boards, so I am inclinded to believe that over any paper analysis which may or may not be correct for a real board. Sure, you might be able to make your board work with a hundred 0603 parts. But wouldn't it save money by reducing the routing congestion on your board if you could reduce that to maybe 20 parts of three different values? It certainly would save time in layout and may even save you a pair of layers in a close board.Article: 107803
yy wrote: > Ayon kay John_H: > > "yy" <yy7d6@yahoo.com.ph> wrote in message > > news:1157037993.495350.96860@b28g2000cwb.googlegroups.com... > > > Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with > > > a SBC (without backplane), the Spec says that IDSEL for the first slot > > > be routed to AD32, IDSEL for the 2nd slot is AD31 and so on, does this > > > mean that i don't need to have an I/O assigned for IDSEL in my FPGA? > > > and refer to AD32 for IDSEL during configuration transaction? > > > > > > BTW, i use Xilinx Spartan 3 fpga. > > > Thanks. > > > > > > I don't believe AD32 is a specific requirement, just a suggestion. If your > > FPGA is embedded on the PCI bus and not interfaces to a slot that has a slot > > IDSEL assigned, then yes, you can hard-wire the IDSEL of your PCI core to > > the selected AD line either inside your device or through a resister > > external to the device. It won't matter to your embedded system which > > approach you use. > > > The Single Board Computer (SBC) to which the PCI Device is to connect > does not have IDSEL on its Edge fingers, also it has CLKA,CLKB,CLKC, > and CLKD to pair with REQ0#-GNT0# to REQ3#-GNT3#. So i will have to > either try both. Typical single board computers with edge fingers expect to plug into a passive backplane that routes the multiple REQ/GNT pairs and clocks to individual slots and gives each slot an associated IDSEL. So you really only need to pick one of the expected configurations, for example REQ0#-GNT0# and IDSEL on AD32. Make sure to pull up unused REQ# signals. As a side note, I would double check the IDSEL routing recommendations. Normally only bits 16 through 31 are used, where 16 corresponds to slot 0 and 31 to slot 15. I've never seen AD32 or any of the extended 64-bit signals used for IDSEL. Regards, GaborArticle: 107804
Manfred Balik schrieb: > Thanks to KJ and Antti for your prompt answers!!! > > I see - I will need a enable signal for each direction, because I want a > synthesizable code not a simulation (I thought this is easy, just a > connection :-( ). > > the PCA9515 is a really nice bidirectional level converter, but I think he > has a enable signal, too. Not a external direction signal, but internally > generated out of weak low (the output of the PCA9515) and hard low (if the > input is low). > > Manfred > > "KJ" <Kevin.Jennings@Unisys.com> schrieb im Newsbeitrag > news:1157109054.812511.131460@b28g2000cwb.googlegroups.com... > > > > Antti wrote: > >> > > >> > What you probably need to add is the concept of an output enable for > >> > both port1 and port2 and only drive the outputs when that output is > >> > enabled... > >> > > >> > port1 <= port2 when (port1_output_enable = '1') else 'Z'; > >> > > >> > KJ > >> > >> KJ > >> > >> bidir connections between to io's are sometimes possible also when > >> no enable signal exists, see NXP's I2C extender as one example > >> > >> http://www.nxp.com/pip/PCA9515DP.html > > > > Yes, and an even simpler example of a bi-directional connection between > > two I/Os with no enable or direction signal is a resistor. > > > > Since I wasn't quite sure exactly what the original poster was trying > > to do, I mentioned "What you probably need...." on the assumption that > > he is trying to come up with synthesizable code targetting some > > FPGA/CPLD or such (in which case I believe he will be needing the > > enable). > > > > If instead the poster was interested in a non-synthesizable simulation > > model that connects two things bi-directionally without a 'direction' > > or 'enable' signal (i.e. like a resistor or the part you linked) than > > he will be wanting a different code entirely. > > > > KJ > > the PCA9515 was just an example reference. it is not generic bidir buffer - such thing is not possible by definition. PCA9515 is somwehat 'protocol aware' and can be used as if it would be transparent bidir buffer for the constrained use of the I2C bus. sometimes similar bidirectional buffer is possible to be implemented in PLD or FPGA or MCU also, but it always needs some 'protocol awareness' and some timing reference to avoid self-lockup. AnttiArticle: 107805
On 1 Sep 2006 05:10:53 -0700, "rickman" <gnuarm@gmail.com> wrote: >John Larkin wrote: >> There's nothing wrong with a cap being inductive as long as the >> inductance is low. If somebody made a 10 farad 0603 cap, its SRF might >> be a kilohertz or something, but having more C, and operating above >> srf, doesn't make it any worse a high-frequency bypass. I figure the >> more C, the better for any given size. > >Another country heard from! > >John, no one is saying more C is not better than less C. The question >is how do you provide *enough* C to do the job in the most cost >effective manner and be sure you have done the job right? > >My point about the caps being inductive is that where a cap is near its >SRF, the impedance is much lower than either the capacitive curve or >the inductive curve. If you draw the impedance line for the equivalent >inductance and for the pure capacitance, they approximate the true >impedance of the part anywhere that is not near the SRF. So when I >talk about the region where the cap is inductive, I am talking about >the impedance rising to a point that it is no longer low impedance. > > >> PCB planes are a big, lossy, many-nF capacitors (or, if you prefer, >> big, lossy, super-low Z transmission lines), and adding lots of, say, >> 0.33 uF 0603 caps just makes it better. All this stuff about Spicing >> staggered srf nulls is silly, given that the caps aren't out in space, >> they're soldered to the huge low-z lossy power planes. > >Well, I didn't know that "silly" was a technical evaluation. I guess >if you are designing a board for Jerry Lewis you should calculate the >SF (Silly Factor) as part of your evaluation. I think you are proving >my point. The caps are on a plane that will resonate with the caps. >So you can't just say adding caps will lower the impedance across the >bandwidth. Except that, when you measure it, they do. > >In fact, however, adding a single value of capacitor to a power plane >is likely to produce a parallel resonance (with a higher impedance than >the plane by itself) at a frequency that you care about. This can be >mitigated by the ESR of the caps which will damp the parallel >resonance. The data I saw showed that using 0603 caps of 0.1 uF will >produce a pretty healthy impedance peak in the 50-100 MHz range, of >course depending on the details of your board. This is a bad place to >have an impedance rise when you are looking for the caps to lower the >impedance. A scattering of 0.1 or 0.33 uf ceramic caps here and there about a power plane will not induce meaningful resonances, as far as I can measure. The only mistake I have ever made on multilayer boards was using too many bypass caps. Lately I use four 0.33 uf caps per supply per FPGA, and even that's probably overkill. > >A lot of people here seem to think that you can analyze this on paper >or with words. I have seen the simulation results and the measurement >results of real boards, so I am inclinded to believe that over any >paper analysis which may or may not be correct for a real board. I have seen a number of simulations that were absurd, generally - surprise! - performed by guys who sell caps. What I believe are TDR measurents on unpowered boards and plane noise measurements on operating products. > >Sure, you might be able to make your board work with a hundred 0603 >parts. But wouldn't it save money by reducing the routing congestion >on your board if you could reduce that to maybe 20 parts of three >different values? It certainly would save time in layout and may even >save you a pair of layers in a close board. All of my boards work as described. The reason there are so many opinions about bypassing is that most everybody's approach works. I know one guy who doesn't use bypass caps at all, and his boards work too. JohnArticle: 107806
John Larkin wrote: > All of my boards work as described. The reason there are so many > opinions about bypassing is that most everybody's approach works. I > know one guy who doesn't use bypass caps at all, and his boards work > too. No caps at all on fpga boards :) Now I know we need a bake off!!!Article: 107807
John Larkin wrote: > On 1 Sep 2006 05:10:53 -0700, "rickman" <gnuarm@gmail.com> wrote: > >So you can't just say adding caps will lower the impedance across the > >bandwidth. > > Except that, when you measure it, they do. I don't know how you measured this. The measurement data I have seen clearly shows this resonance. But it was not my data, it was from someone much more knowledgeable than myself. > All of my boards work as described. The reason there are so many > opinions about bypassing is that most everybody's approach works. I > know one guy who doesn't use bypass caps at all, and his boards work > too. I don't doubt that there are many ways to skin a cat. But I have seen for myself boards that did not work well because of power decoupling problems. The biggest symptom from poor power distribution is general flakeyness. Often this is misdiagnosed as an SI issue, which I guess is not totally wrong. But now I realize that the proper cause of poor edge rates and some portion of bounce problems is in the power distribution. With no caps I would expect you have to be designing board with very limited IO and low current devices. I seriously doubt that his method would work on every product. The real point that was made in the class I took was that you need to evaluate your power decoupling needs rather than just applying a "rule of thumb". I guess some people do their evaluation by saying, "I don't need no stinkin' caps". ;^)Article: 107808
Hello Bill, >>> >>>>Know what? What really bad typos indicate? Pretty clear, if someone >>>>affords his or her resume that little attention to detail I assume it'll >>>>be the same for a design. Can't use that. >>> >>>Or the person is dyslexic with a foriegn native tounge, language >>>impaired, but with experience and genuis in design that can easily be >>>offset by using good clerical assistant to help the designer with >>>writing, editing, and other written language issues. >> >>Wouldn't you then expect that genius to be smart enough to have a friend >>critique and correct their resume? Or at least click Tools -> Spell >>Check? That ain't rocket science... > > We had one very bright but dyslexic engieer at Cambridge Instruments, > who never really got the idea that it mattered how you spelled a word > as long as what you wrote sounded right, so he used "their", "there" > and "they're" as if they were interchangeable, and - while he > appreciated the theory behind our complaints about his spelling, he > never took us really seriously, because he couldn't imagine that we > didn't hear the words printed on the page. > That's ok. > I offered to spell check his written output on a number of occasions, > but he never took me up on it. > That's not ok. Not seeking help in an area where you have a lack is a mistake. Sometimes a serious one, like when it affects safety (Oh, we don't need that EMC consultant...). Sure I could do the biz taxes myself. Do I do that? Nope. To avoid costly mistakes I am using an attorney/CPA who is expert in that matter. In the same way that my clients use me. -- Regards, Joerg http://www.analogconsultants.comArticle: 107809
Hello John, >> That's a common misconception even among professional translators. >> They think that you don't need to be an engineer to translate >> technical stuff. > > REALLY professional translators ask for help on the translators' > newsgroup. Most of its traffic is about queries on technical terms. Interesting. Which NG is that? Might have to point some folks there ;-) -- Regards, Joerg http://www.analogconsultants.comArticle: 107810
bill.sloman@ieee.org wrote: > We had one very bright but dyslexic engieer at Cambridge Instruments, > who never really got the idea that it mattered how you spelled a word > as long as what you wrote sounded right, so he used "their", "there" > and "they're" as if they were interchangeable, and - while he > appreciated the theory behind our complaints about his spelling, he > never took us really seriously, because he couldn't imagine that we > didn't hear the words printed on the page. > > I offered to spell check his written output on a number of occasions, > but he never took me up on it. One of the things that you learn being dyslexic, is miss spellings are frequently valid words in the dictionary, and that spell checkers are marginally useful at best. "their", "there" and "they're" are all valid spellings, and spell check is useless. I know when I write, I internally know what I want in correct english. What the brain writes thru my fingers and seen by my eyes is quite frequently different. Especially when tired, stressed, etc. One example is that I frequently will replace a word with the word that follows it, such that it's there twice. Or that a completely different word will pop out ... such as replacing "the" with "and", or "this" with "there", or "that" with "this". I proof right over these mistakes when writing most of the time. If I wait about 3 days, and reproof, I spot it immediately. Frequently, what comes out my fingers will be the wrong suffix for a word construction, such as "confident" will be replaced with "confidence". Transpositions are also a problem, but for some reason they are a little easier for me to spot while writing, but not always. This is one area where spell check makes a difference, some times. I worked for a boss for several years that was worse than me. We used to proof each others writings. Only about 50% of the time could we spot the others mistakes, the rest of the time our brain would automatically correct their mistake too, and continue to do so every time we reread that section. Then, for whatever reason, several days later it would be obviously wrong if proofed again. I realize that your coworkers actions may have seemed, indifferent. That in your mind, these kind of mistakes are just careless. But again, your brain isn't wired that way.Article: 107811
On Fri, 01 Sep 2006 04:40:39 GMT, John_H <newsgroup@johnhandwork.com> wrote: >John Larkin wrote: >> On 27 Aug 2006 20:39:49 -0700, "rickman" <gnuarm@gmail.com> wrote: >> >>> Austin Lesea wrote: >>>> To the subject at hand: placing additional caps across existing caps >>>> does not reduce the noise (unless the dominant cause is lack of adequate >>>> capacitance). >>>> >>>> The reason why the noise is bad is that the L (as in Ldi/dt) is most >>>> likely the largest, and most dominant factor, in the form of the via and >>>> traces to the bypass capacitor. >>>> >>>> Many times people have placed additional caps on top of the the existing >>>> caps and wondered why the noise is not reduced: well, you did not >>>> change the L in the equation, did you. So why did you expect V to change? >>>> >>>> You may have moved the resonant frequency (more often not), but often >>>> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a >>>> 0.001uF in parallel. You can see that if the series L is dominant, you >>>> haven't even moved the frequency by more than a few percent by the small >>>> amount of additional capacitance. >>> What do you think about the idea that if the caps are connected >>> directly to good low impedance power planes that the location of the >>> caps are not critical at all. I have been discussing this in >>> comp.arch.embedded and have not gotten much negative feedback except >>> some claim that more is always better and that multiple values are not >>> needed. >>> >> >> I sometimes add a few SMA connector footprints to multilayer boards so >> I can TDR the planes. As near as I can measure with my Tek 20 GHz TDR, >> on a bare VME-sized (6U) board, good parallel planes look like an >> ideal capacitor, with no evidence of edge reflections or anything like >> that. And as you load ceramic bypass caps *anywhere* on the board, the >> value of the ideal cap increases. So it doesn't much matter where you >> put bypass caps. >> >> The planes are a better cap than any discrete parts. Keep the >> powerplane to ground dielectric thin, 5 mils or less, to keep the >> plane capacitance high. >> >> John > >Have you verified that you can use a 50 ohm TDR to effectively measure >impedance around 1 ohm and less? > >Measurements have been made by others that suggest your readings aren't >telling you the whole story. It's possible the others are wrong and >you're correct but it seems there are several sources suggesting that a >6U board will NOT look like an ideal capacitor without inductive or >transmission line effects. The complementary measurement is to use the same SMA tap to measure plane noise on the operating board, which is a good way to verify theory. I do boards that mix FPGA's, Eclips, uPs, fiber optics, PLLs, VME interfaces, and precision delay generators, and they all work at picosecond jitter levels. So far, close planes and reasonably scattered 0.1 or 0.33 uF 0603 bypasses have always worked. JohnArticle: 107812
I need to interface some 12 and 24V signals to an FPGA/CPLD, it'll probably be one of the low end Spartans or Cyclones. These are _very_ low bandwidth signals, 10's of hz at the most. Because of the signal density, cost and restrictions of board space I am unable to implement any voltage regulation/clamping pre the FPGA inputs. I am planning to using a very large in line resistor (100K ?) to limit current into the device pins. I know that one of the recommended techniques for interfacing to 5V PCI signals is to use an in-line current limiting resistor. What I'm planning is an extension of this but I've previously always used quickswitches to clamp higher volates to safe limits and intuitively don't like applying these higher voltages to the pins. Should this be OK? NialArticle: 107813
Nial Stewart schrieb: > I need to interface some 12 and 24V signals to an FPGA/CPLD, > it'll probably be one of the low end Spartans or Cyclones. > > These are _very_ low bandwidth signals, 10's of hz at the most. > > Because of the signal density, cost and restrictions of board > space I am unable to implement any voltage regulation/clamping > pre the FPGA inputs. > > I am planning to using a very large in line resistor (100K ?) to > limit current into the device pins. > > I know that one of the recommended techniques for interfacing to > 5V PCI signals is to use an in-line current limiting resistor. > What I'm planning is an extension of this but I've previously > always used quickswitches to clamp higher volates to safe limits > and intuitively don't like applying these higher voltages to the > pins. > > Should this be OK? > > Nial probably. but the thing with the 'clamp diodes' is that they are not necessarily always enabled! and then the actual voltages on the io pad would rise well above 5V. So it makes sense to checkout if the clamp diodes are there when FPGA is not configured. I have had some FPGA to get internal VCCINT short circuit an a board that had a few hundred ohms series resistor from an 5V RS232C driver IC to FPGA pin. I cant know that this was the reason for the FPGAs to burn, but I would be rather careful with the non-3.3V inputs (24V!) and series resistors. AnttiArticle: 107814
fpga_toys@yahoo.com wrote: > I realize that your coworkers actions may have seemed, indifferent. > That in your mind, these kind of mistakes are just careless. But again, > your brain isn't wired that way. A while back this was passed around on various mailing lists: i cdnuolt blveiee taht I cluod aulaclty uesdnatnrd waht I was rdanieg. The phaonmneal pweor of the hmuan mnid, aoccdrnig to a rscheearch at Cmabrigde Uinervtisy, it dseno't mtaetr in waht oerdr the ltteres in a wrod are, the olny iproamtnt tihng is taht the frsit and lsat ltteer be in the rghit pclae. The rset can be a taotl mses and you can sitll raed it whotuit a pboerlm. Tihs is bcuseae the huamn mnid deos not raed ervey lteter by istlef, but the wrod as a wlohe. Azanmig huh? yaeh and I awlyas tghuhot slpeling was ipmorantt! It was interesting that most of my friends could struggle thru it with little trouble. Those of us that are also dyslexic, found it was MUCH easier. Besides language, this less rigid form of viewing the world is frequently useful, and productive, at following others work, spotting errors in others designs, and following non-traditional design approaches that are outside what others would consider, even when they are boxed in and see no other solution. So the abnormality of our brains, which includes dyslexia and a number of other "different" wirings in our brains, also turns out to also be a gift. It's also genetic ... my mom and son both are too.Article: 107815
Nial Stewart wrote: > I need to interface some 12 and 24V signals to an FPGA/CPLD, > it'll probably be one of the low end Spartans or Cyclones. > Because of the signal density, cost and restrictions of board > space I am unable to implement any voltage regulation/clamping > pre the FPGA inputs. > > I am planning to using a very large in line resistor (100K ?) to > limit current into the device pins. Is there no space for a zener diode from the signal line to ground additionally to a series resistor? RalfArticle: 107816
"Ralf Hildebrandt" <Ralf-Hildebrandt@gmx.de> wrote in message news:4lr2t3F3a937U1@individual.net... > Is there no space for a zener diode from the signal line to ground > additionally to a series resistor? Possibly, I can possibly negotiate a bit more space with my client if I can convince him it's going to make things more reliable. We were trying to fit things into an enclosure bought off the shelf, but he's been enthusing about a custom enclosure manufacturer he went to see yesterday. If their quotes are reasonable I should be able to get a bit more space. Nial.Article: 107817
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1157124085.509196.151500@h48g2000cwc.googlegroups.com... > Nial Stewart schrieb: > probably. but the thing with the 'clamp diodes' is that they are not > necessarily always enabled! and then the actual voltages on the io pad > would rise well above 5V. So it makes sense to checkout if the clamp > diodes are there when FPGA is not configured. > > I have had some FPGA to get internal VCCINT short circuit an a board > that had a few hundred ohms series resistor from an 5V RS232C > driver IC to FPGA pin. I cant know that this was the reason for the > FPGAs to burn, but I would be rather careful with the non-3.3V inputs > (24V!) > and series resistors. I'll check the clamp diode situation, I thought they were always enables (should RTFM I supposed). Thanks for the heads up Antti. Nial.Article: 107818
In message <1157122820.519008.213790@p79g2000cwp.googlegroups.com>, dated Fri, 1 Sep 2006, fpga_toys@yahoo.com writes > We used to proof each others writings. Only about 50% of the time >could we spot the others mistakes, the rest of the time our brain would >automatically correct their mistake too, and continue to do so every >time we reread that section. Yes, because you both had the same trait, 'brain wired that way'). You needed a third party. >Then, for whatever reason, several days later it would be obviously >wrong if proofed again. Even skilled proof-readers find that. But even at first reading, it's almost as if the errors are printed in a different colour, they are so obvious. And this can extend to poor sentence construction, like 'only' being in the wrong place. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107819
In message <1157125162.199701.238490@i3g2000cwc.googlegroups.com>, dated Fri, 1 Sep 2006, fpga_toys@yahoo.com writes >So the abnormality of our brains, which includes dyslexia and a number >of other "different" wirings in our brains, also turns out to also be a >gift. > >It's also genetic ... my mom and son both are too. It's more rare in females. But there are 57 varieties of 'dyslexia'. Are you left-handed? -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107820
Nial Stewart schrieb: > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1157124085.509196.151500@h48g2000cwc.googlegroups.com... > > Nial Stewart schrieb: > > > probably. but the thing with the 'clamp diodes' is that they are not > > necessarily always enabled! and then the actual voltages on the io pad > > would rise well above 5V. So it makes sense to checkout if the clamp > > diodes are there when FPGA is not configured. > > > > I have had some FPGA to get internal VCCINT short circuit an a board > > that had a few hundred ohms series resistor from an 5V RS232C > > driver IC to FPGA pin. I cant know that this was the reason for the > > FPGAs to burn, but I would be rather careful with the non-3.3V inputs > > (24V!) > > and series resistors. > > > I'll check the clamp diode situation, I thought they were always > enables (should RTFM I supposed). > > Thanks for the heads up Antti. > > Nial. Hi Nial, well in case the clamp diode can be specified with FPGA config settings, like PCI Clamp ON-OFF, then it obviously can not be permanently on. just make some experiments with large resistor, multimeter and adjustable power supply, while keeping the FPGA unconfigured. if you can have some external zener or tvs its better of course solution AnttiArticle: 107821
On Fri, 1 Sep 2006 16:13:19 +0100, "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote: >I need to interface some 12 and 24V signals to an FPGA/CPLD, >it'll probably be one of the low end Spartans or Cyclones. >These are _very_ low bandwidth signals, 10's of hz at the most. Oh, tell me about it. In a previous existence, that sort of thing was the bane of my life. Mind-numbingly simple stuff, but there's no well-integrated support for it; it costs space, components, PCB trackery, power supply fuss and bother, and all manner of general horribleness. I would be very nervous of adding 100K-ish resistors in series with an FPGA input; the very slow rise times you would thus get sound to me like a recipe for nasty stuff to happen on the inputs. (Note to self: must check data sheet; how much hysteresis do they have on FPGA inputs these days?) Of course you will be applying all sorts of filtering, debouncing and other good stuff to the signals once inside the FPGA, but... You can get clamp diode arrays in reasonably small packages; would that help? >Because of the signal density, cost and restrictions of board >space I am unable to implement any voltage regulation/clamping >pre the FPGA inputs. That statement bothers me a little. If these are the usual 24V industrial sensor type inputs, then each input has a cost and space penalty associated with it (connectors, wiring, EMC filtering gubbins like clamp-on ferrites...) that vastly outweighs the cost and area of a couple of small SM components. I know that sometimes we poor electronics grunts are squeezed into absurdly tight spaces because "the electronics doesn't take up much room, does it?". But there's also the small matter that these 24V signals probably come from badly-shielded wiring that's spent most of its life in close proximity to a 5kW electric motor, or an arc welding set, or some other macho equipment. I used to reckon that effort spent on dealing with those risks in a paranoid way *always* paid for itself in reduced hassle later. If your electrical environment is much kinder than I was used to, then please forgive my irrelevant ramblings. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 107822
In message <XQXJg.7281$q63.7073@newssvr13.news.prodigy.com>, dated Fri, 1 Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes >>> That's a common misconception even among professional translators. >>>They think that you don't need to be an engineer to translate >>>technical stuff. >> REALLY professional translators ask for help on the translators' >>newsgroup. Most of its traffic is about queries on technical terms. > > >Interesting. Which NG is that? Might have to point some folks there ;-) sci.lang.translation For time to time, it can get as surreal as this NG, but there is much less traffic. And no abuse now. About five years ago, we had a real nutter; Spanish and good at translation (and, incidentally, an expert at retrieving stuff from the Internet), but he went as far as making threatening phone calls, and someone with contacts in the Spanish police arranged for him to be shown the error of his ways. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107823
fpga_toys@yahoo.com wrote: > >>I realize that your coworkers actions may have seemed, indifferent. >>That in your mind, these kind of mistakes are just careless. But again, >>your brain isn't wired that way. > > A while back this was passed around on various mailing lists: > > i cdnuolt blveiee taht I cluod aulaclty uesdnatnrd waht I was rdanieg. > The phaonmneal pweor of the hmuan mnid, aoccdrnig to a rscheearch at > Cmabrigde Uinervtisy, it dseno't mtaetr in waht oerdr the ltteres in a > wrod are, the olny iproamtnt tihng is taht the frsit and lsat ltteer be > in the rghit pclae. The rset can be a taotl mses and you can sitll raed > it whotuit a pboerlm. Tihs is bcuseae the huamn mnid deos not raed > ervey lteter by istlef, but the wrod as a wlohe. Azanmig huh? yaeh and > I awlyas tghuhot slpeling was ipmorantt! > > It was interesting that most of my friends could struggle thru it with > little trouble. Those of us that are also dyslexic, found it was MUCH > easier. > Amazing. I could actually read it about as fast as if it were regular text. Then again most of us are used to piece together incomplete data on the fly. Like when you can barely hear a PA announcement over the din of an airport crowd. PA system: "... teen fifty .... ver ... celled". Brain: "Oh drat, now I'm not going to make the meeting in Denver on time". > Besides language, this less rigid form of viewing the world is > frequently useful, and productive, at following others work, spotting > errors in others designs, and following non-traditional design > approaches that are outside what others would consider, even when they > are boxed in and see no other solution. So the abnormality of our > brains, which includes dyslexia and a number of other "different" > wirings in our brains, also turns out to also be a gift. > That would mean that analog folks often fall into that group. We have a knack for stepping back, squinting and then coming up with some outlandish and really unorthodox solution. "You mean, this can be done without a micro?" > It's also genetic ... my mom and son both are too. > But you did the right thing: Realized it and either proof read a few days later or let others proof. Way to go. -- Regards, Joerg http://www.analogconsultants.comArticle: 107824
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:u1wqv2aak.fsf@trw.com... > "Symon" <symon_brewer@hotmail.com> writes: > > > > I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any > > decoupling at frequencies above a few hundred MHz is useless because of the > > package impedance at these frequencies. > and > > > To repeat myself, I don't care what the impedance is above a few hundred > > MHz. This 'threadlet' starting with Martin's post is addressing mini-plane > > resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz > > now! :-) > > As I understand it, the reason you don't care above a few hundred MHz > is because you are doing mini-planes? If you were doing whole board > planes, then there may be problems above the "package frequency" due > to the PCB radiating at a frequency which is not "well-decoupled" even > at several hundred MHz. With a bigger plane, this is more likely. > > Or have I misunderstood? > > Cheers, > Martin > Hi Martin, Right. That's my reasoning. Cheers, Syms.
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