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On Wed, 10 Nov 1999 10:42:35 +1000, anup kumar raghavan
<anup@elec.uq.edu.au> wrote:
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Article: 18726Arnold Beland wrote: > > I have decided to use the CAN bus for a variety of control projects. I > would appreciate any suggestions. > > Thanks in advance, > > Arnold Beland try: http://www.lawicel.com/candip/ Don McKenzie mailto:don@dontronics.com http://www.dontronics.com Don's Download Dungeon: http://www.dontronics.com/download.html World's Largest Range of Atmel and PICmicro Hardware and SoftwareArticle: 18727
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Hi Anton, <br>thank you for your reply. I would like to know if you have another e-mail <br>address than antera@mweb.co.za for future contacts, because I have serious <br>problems with sending any new messages via my connection (I don not why!) <br>Maybe you would know what it may mean and how I will be able to send you <br>anything without newsgroup usage (see attachment). <p>Regards <br>Jessie <p>ATTACHMENT (previoulsy sent messages to you): <p>The original message was received at Tue, 9 Nov 1999 08:15:56 GMT <br>from [195.117.19.230] <p> ----- The following addresses had permanent fatal errors ----- <br><antera@mweb.co.za> <p> ----- Transcript of session follows ----- <br>... while talking to jhb-proxy.mweb.co.za.: <br>>>> RCPT To:<antera@mweb.co.za> <br><<< 550 5.7.1 Baddomain, your domain has been blocked from sending to : <br>antera@mweb.co.za <br>550 <antera@mweb.co.za>... User unknow <p>Anton Erasmus wrote: <blockquote TYPE=CITE>Hi, <p>I am trying to get a 16MHz Frequency from a 24MHz Clock on a Altera <br>EPM7128. The 24MHz Clock is connected to one of the global clock <br>inputs. Can anyone help me in doing this in AHDL ? <p>Regards <br> Anton Erasmus</blockquote> </html>Article: 18728
Arnold, My company, Arcom Control Systems, manufacturers a single-channel opto-isolated CAN interface module using the Philips SJA1000 chip in PC/104 form-factor, the AIM104-CAN. DeviceNet software is available for this board and drivers for Dos or Windows CE operating systems. For more information, please visit the link below for the AIM104-CAN, or please do not hesitate to contact me. http://www.arcomcontrols.com/products/icp/pc104/modules/AIMcan1.htm Thanks, Steve Lovell Arcom Control Systems 13510 South Oak Street Kansas City, MO 64145 Phone: 816-941-7025, x255 E-mail: slovell@arcomcontrols.com Web: www.arcomcontrols.com Arnold Beland wrote in message <80a9nk$127v@enews4.newsguy.com>... >I have decided to use the CAN bus for a variety of control projects. I >would appreciate any suggestions. > >Thanks in advance, > >Arnold Beland > >Article: 18729
Brian Philofsky wrote: > The reason I suggested the Map route is because the original request > was to simulate the logic delays but not routing delays. Most > netlists produced by synthesis tools do not have any delay information > therefore only a unit delay simulation would be possible. By > processing the design through map, you will get true logic level > delays but not routing delays. Performing a post-synthesis simulation > is fine if you are interested in only a unit delay simulation and will > save you a few steps through our tools although in general the netlist > translation and map stage do not take too much CPU time. > > True you will have to use the SIMPRIM libraries with this approach > rather than the UNISIM libraries however I don't understand the > problems you mention. I successfully use both types of simulation > models all the time for both VHDL and Verilog simulations. The only > major things that come to mind that you may be referring to are in the > 1.5 release of the LUT models (for Verilog), you must drive all design > inputs or sourced LUTs will go to a simulation value of X. All that > was needed to be done is to tie undriven design inputs to a known > value. With the 2.1 release, that requirement has been lifted and you > should only see X's on the outputs of undriven LUTs when that input > has a direct correlation to the result. The only other problems I > generally see when a global reset is not performed on the design > before beginning simulation. The methodology for global reset has > been changed for Verilog in the 2.1 release so that it will work > better with pre-compiled libraries which seems to be the trend of most > Verilog simulators today. This methodology is explained in our > documentation. Without this global reset, it is possible the design > might come up in a unknown state. > > I am not trying to say the Xilinx libraries are without fault however > they should work with most simulation/design scenarios. There are > always going to be corner cases which can not be easily accounted for > and as those are encountered, we will try to fix them. > > If you would like to go into more detail as to the problems you > mention, I would like to hear them. Although I am not directly > involved with the simulation group, I can pass on any > comments/experiences you or anyone else might have about the > simulation libraries. I would like to change this perception that > they are error-prone. > > Thanks, > > > -- Brian Philofsky > -- Xilinx Design Engineer > > Brian, I've emailed you directly a summary of my Verilog post MAP/PAR simulations. In general the 2.1i Verilog stuff can be made to work well but you might need a couple of modifications. I would like to clear up a couple of points here though. First the description of the LUT problem is not complete. As well as the issues you mention above the 1.5 models themselves were wrong and couldn't handle _legitimate_ `x' conditions. If anybody wants to try this all they have to do is configure a 1.5 LUT2 model as a simple ``and gate'' [INIT = 4'h8], set one input to 0 and the other to `x' and see what happens. This was very depressing since at the time I badly needed at least post-MAP simulation in my hunt for the Virtex MAPper ``disappearing inverter'' bug. The 2.1i LUT models have been completely re-written. Secondly, and directly relevant to the original posting, is a problem with post-MAP Virtex simulation where the design contains BlockRAMs with several inputs e.g. addresses tied to GND. The Verilog netlist generator may sometimes leave these inconnected. This doesn't seem to happen with PAR simulation. Finally the 2.1i UNISIMS Verilog models seem to be a step backwards from the 1.5 ones. They have been rewritten as behavioural and seem to have lost all attempts to e.g. handle `x' conditions which the 1.5 versions for the most part modeled correctly. This means that anyone using them for post-synth simulation is likely to get differences when they come to post-route simulation. Of course you can always push on through NGDBUILD & then use the SIMPRIMS lib. If anybody else is interested in my findings please mail me & I'll try to make a summary available on our FTP. Anybody had any experience with the VHDL simulation ?Article: 18730
Armold: The NSI Canpocket analyser is a handy little tool and is pretty useful. I liked it a lot, although the version I used had only French language support, I believe it now supports English. About 1000 UKP last time I looked... Vector Software's Canalyzer is an expensive but heavyweight tool which needs a PC with a PCMCIA slot for their own CAN card. Comprehensive but only for those with about 4000 UKP to spend... Both available from Hitex, who are in England, Germany and the USA. On the other hand, if you buy a cheapo CAN card for your PC you can knock up an analyser program using your preferred PC development tool. We did one using a National Instruments CAN card and LabWindows CVI. There are much cheaper CAN cards available than the NI ones. Check the CAN In Automation journal for details. Cheers TW Any views expressed in this message are those of the individual sender, except where the sender specifically states them to be the views of Sortex Ltd Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18731
Hi Arnold, Be sure to check through the CAN mailing list archives, you can find them in the "News"-section at http://www.vector-informatik.de/. Please check out my web page for both PC interfaces, HC11 with CAN and Infineon C505C boards. www.zanthic.com Also check out Lar's page for a really neat, small and low cost CAN node http://www.lawicel.com/candip/ (and other neat CAN stuff) Good luck, Steve Zanthic Technologies Inc. located at http://www.zanthic.com Controller Area Network boards for HC11, ISA/PC104 and Parallel I/O boards for ISA and Parallel, Win95/98 and NT drivers included Arnold Beland wrote in message <80a9nk$127v@enews4.newsguy.com>... >I have decided to use the CAN bus for a variety of control projects. I >would appreciate any suggestions. > >Thanks in advance, > >Arnold Beland > >Article: 18732
You might want to check out http://www.ibutton.com/TINI/index.html . A SIMM JAVA controller with Ethernet, 4 Mb RAM, RTC, CAN interface and other goodies. $50 Qty 1. Very cool. Arnold Beland wrote: > > I have decided to use the CAN bus for a variety of control projects. I > would appreciate any suggestions. > > Thanks in advance, > > Arnold Beland -- Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 18733
Do not waste your time and money on OrCAD Express. In article <38285ffc@ant.wmin.ac.uk>, seamang@westminster.ac.uk (Graham Seaman) wrote: > I'm new to using ORCAD (I have tried mailing them/using their notice board > with no response so far) - does anyone have any experience of using > the Express synthesis for simpleplds (actually GAL22V10)? > I have a little behavioural VHDL FSM which analyzes ok; when I try to build > it Express generates an error message telling me I have too many > product terms for a couple of rows. On inspecting the vhdl netlist > its generated, there are actually not many PTs in the expressions > its complaining about - well within the powers of a 22V10! > Is there a common user error which could generate this? Or is this > a known problem for which a patch is available? (I have v. 7.1) > > Thanks for any advice, > > Graham Seaman > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18734
wq998@my-deja.com wrote: > Do not waste your time and money on OrCAD Express. > Now there's a helpful answer! Are the pins constrained? The 22v10 has 10 product terms on the 'outside' outputs and 16 on the center ones. If you have, say 12 product terms, there are four outputs that the equation can't be assigned to. > In article <38285ffc@ant.wmin.ac.uk>, > seamang@westminster.ac.uk (Graham Seaman) wrote: > > I'm new to using ORCAD (I have tried mailing them/using their notice > board > > with no response so far) - does anyone have any experience of using > > the Express synthesis for simpleplds (actually GAL22V10)? > > I have a little behavioural VHDL FSM which analyzes ok; when I try to > build > > it Express generates an error message telling me I have too many > > product terms for a couple of rows. On inspecting the vhdl netlist > > its generated, there are actually not many PTs in the expressions > > its complaining about - well within the powers of a 22V10! > > Is there a common user error which could generate this? Or is this > > a known problem for which a patch is available? (I have v. 7.1) > > > > Thanks for any advice, > > > > Graham Seaman > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18735
Hi All, Check this site out - http://www.KnowToday.com I recently registered on an interesting new site called - KnowToday.com that allows its members to buy and sell information! They are currently recruiting new members and will launch the site in several months. For a limited time, they are offering an incentive plan, where they pay you for successful referrals. It sounds really interesting. You can go on their site and ask detailed questions or make money by answering questions. They are designing the site with many different categories, so almost anyone will be able to ask and answer questions. Also, you can make money if any of your referrals use the site. It only takes a minute to join - http://www.knowtoday.com/ - they explain everything on the web site. It's totally free and you have no further obligations after registering Hope you like it! John mzjhqujmzfwylkwlwmsykbermgdctgyjrlxdqjxbjthkjvdcxptmzwleudgizvhvxbfckwvwgxfArticle: 18736
Precise has a CAN implementation with their RTOS. www.psti.com. Arnold Beland wrote: > I have decided to use the CAN bus for a variety of control projects. I > would appreciate any suggestions. > > Thanks in advance, > > Arnold BelandArticle: 18737
Hi, I'm selling a full Altera MAX+Plus II package, V9.01. It's new and still sealed (I never used it). This package is their "Magnum" product which supports full VHDL. Great for DSP design. Includes manual, CD-ROM and dongle. The standard 3-month maintainance has expired. I can transfer registration to you upon purchase. Originally $7000, will sacrifice for $1000 including shipping. - Chris fidonews2@my-deja.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18738
giuseppe giachella wrote: > After placing and routing my design on an Altera Flex 10KA250, Maxplus2 > created two output files .vho and .sdo in order to start > a postlayout simulation. These two files have a dimension of 16 MB > each. It is almost impossible for me to compile such a vhdl and load > an sdf file so big (I have tried using Modelsim and VSS). > > Is there anyone who succeeded in simulating files so big ? > > What should I expect if I migrate my design an a APEX or VIRTEX > (they contain much more gates than a Flex 10KA250) ? > One approach would be to use a perl script to split the postroute netlist into separate pieces and compile them seprately into a library. Alternatively if VHDL makes that difficult and you have the co-simulation version of ModelSim you could output the netlist in the more compact & easy to split Verilog form. For my postlayout Virtex XCV300 simulation I get an 8MB Verilog netlist+8MB SDF and ModelSim [5.3aPE] handles this with no problems, takes just under 2 minutes to compile - 450MHz P-II + 512MBytes.Article: 18739
Does anyone know a FPGA evaluation (demonstration) board for Xilinx FPGA's larger PC84 packages or reprogrammable Actel FPGA's ? Where can I get it ? Thanks Andreas BarthelArticle: 18740
Ray Andraka (randraka@ids.net) wrote: : wq998@my-deja.com wrote: : : > Do not waste your time and money on OrCAD Express. : > : : Now there's a helpful answer! And I don't have any choice... but it sounds like there are well known problems with it. What are they? : : Are the pins constrained? The 22v10 has 10 product terms on the 'outside' : outputs and 16 on the center ones. If you have, say 12 product terms, : there are four outputs that the equation can't be assigned to. : No, no pins constrained at all. 6 outputs are used, 2 registered with 3 PTs each (none of the pts have more than 4 variables). These are the ones I get the error messages for. The rest are combinational and only need 1 pt. So its clearly not a 'real' fitting problem. My guess is that maybe there's a problem with the simplepld library - perhaps something I haven't included, the documentation is very patchy. I guess I have to track down an Orcad user... GrahamArticle: 18741
Can any one point me to a design for a programmable divide-by-n using an XC4002xl device? I plan on using the fastest speed grade available in this part. I need to divide by n, where n can be any integer from 2 to 32. I don't care if the counter is up or down or whatever but it needs to count with a 50% clock at 102.4 MHz. Also I am looking for as detailed a schematic as I can find on how to connect the 4002 to an EPROM, etc. I have hired a grad student to design the actual FPGA code and he seems to be doing a good job but the actual hardware connection between the FPGA and the EPROM is still unclear to me. If anyone has any comments on how to decouple the FPGA, etc. I would be thankful. I currently have a discrete version of this system in the prototyping stage but the switching noise in the digital system is killing my analog performance. By the way I guess I should explain that this system involves a relatively slow ramp driving a comparator. The output of the comparator is coupled to the digital section. The basic nature of the system precludes using hysteresis to clean up the signal so I need to clean up the digital noise before the comparator. Thanks, Theron HicksArticle: 18742
I would like to know if i can ReadBack an Altera FPGA so I can get the file that it is programmed. I have an Altera Programmer (the card, mpu unit and the serial cable)Article: 18743
Use a loadable down-counter that uses the carry chain. Invert and connect the tc output to the load input so that the counter automatically reloads on the next rising edge after the counter reaches zero. The parallel load input is one less than the count length. You can use the Xilinx logiblox downcounter, but you are better off rolling your own if you use the count enable because the xilinx macro puts an OR gate on the CE input, which will degrade maximum performance. In an XLA-07 this circuit will run at around 140 MHz for a 16 bit counter. That curcuit should give you 103 MHz performance in a Spartan XSC05XL as well. I'd send a picture, but I'm having trouble with my viewlogic license at the moment. The EEPROM connections for the FPGA are outlined pretty well in the data book. Also look on http://www.xilinx.com in the support answers for additional information on configuration and eeproms. For bypassing, you want to put a cap at each voltage pin. Keep the caps as close as possible, and connect them so that the trace from the via from the vcc plane to the device goes through one of the cap pads. The connection to the ground plane from the other cap pad should be kept as short as possible as well. The idea here is to keep the inductance in series with the cap as low as possible, and to use the trace inductance in the supply lead to your advantage. Also, keep the traces from the FPGA ground pins to the ground plane vias as short a possible. Use at least a 4 layer board with solid VCC and ground planes. You might want to separate the digital and analog voltage and ground planes as well. Theron Hicks wrote: > Can any one point me to a design for a programmable divide-by-n using an > XC4002xl device? I plan on using the fastest speed grade available in > this part. I need to divide by n, where n can be any integer from 2 to > 32. I don't care if the counter is up or down or whatever but it needs > to count with a 50% clock at 102.4 MHz. Also I am looking for as > detailed a schematic as I can find on how to connect the 4002 to an > EPROM, etc. I have hired a grad student to design the actual FPGA code > and he seems to be doing a good job but the actual hardware connection > between the FPGA and the EPROM is still unclear to me. If anyone has > any comments on how to decouple the FPGA, etc. I would be thankful. I > currently have a discrete version of this system in the prototyping > stage but the switching noise in the digital system is killing my analog > performance. By the way I guess I should explain that this system > involves a relatively slow ramp driving a comparator. The output of the > comparator is coupled to the digital section. The basic nature of the > system precludes using hysteresis to clean up the signal so I need to > clean up the digital noise before the comparator. > > Thanks, > Theron Hicks -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18744
After placing and routing my design on an Altera Flex 10KA250, Maxplus2 created two output files .vho and .sdo in order to start a postlayout simulation. These two files have a dimension of 16 MB each. It is almost impossible for me to compile such a vhdl and load an sdf file so big (I have tried using Modelsim and VSS). Is there anyone who succeeded in simulating files so big ? What should I expect if I migrate my design an a APEX or VIRTEX (they contain much more gates than a Flex 10KA250) ? ______________________________________________________ Get Your Private, Free Email at http://www.hotmail.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18745
Try www.xess.com. Good luck! In article <382AC088.B56986B7@htwm.de>, barthel@htwm.de wrote: > Does anyone know a FPGA evaluation (demonstration) board for Xilinx > FPGA's > larger PC84 packages or reprogrammable Actel FPGA's ? > Where can I get it ? > > Thanks > > Andreas Barthel > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18746
I haven't seen a board for Actel's reprogrammable FPGAs but there are a number of Xilinx boards, supporting the larger devices, listed on The Programmable Logic Jump Station at http://www.optimagic.com/boards.html. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Andreas Barthel <barthel@htwm.de> wrote in message news:382AC088.B56986B7@htwm.de... > Does anyone know a FPGA evaluation (demonstration) board for Xilinx > FPGA's > larger PC84 packages or reprogrammable Actel FPGA's ? > Where can I get it ? > > Thanks > > Andreas BarthelArticle: 18747
In article <38285ffc@ant.wmin.ac.uk>, seamang@westminster.ac.uk (Graham Seaman) wrote: > I'm new to using ORCAD (I have tried mailing them/using their notice board > with no response so far) - does anyone have any experience of using > the Express synthesis for simpleplds (actually GAL22V10)? > I have a little behavioural VHDL FSM which analyzes ok; when I try to build > it Express generates an error message telling me I have too many > product terms for a couple of rows. On inspecting the vhdl netlist > its generated, there are actually not many PTs in the expressions > its complaining about - well within the powers of a 22V10! > Is there a common user error which could generate this? Or is this > a known problem for which a patch is available? (I have v. 7.1) > > Thanks for any advice, > > Graham Seaman > We have encountered a number of problems using OrCAD Express. OrCAD themselves admit that the synthesis engine they wrote was less than perfect. That's why they bolted in the Exemplar synthesis engine in release 9. They still use the homegrown synthesizer for simple PLDs though. We are working with Xilinx CPLDs and FPGAs. The problems that we are experiencing are mostly related to the interface between Capture and Express, and the interface between Express and the Xilinx A2.1i tools. We have problems passing constraints through, and we have found one bad macro (XIL_M1\XC4000E\CB2CLE.EDN). -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18748
We are evaluating these tools. I would appreciate any comments from those of you that have experience with at least two of the following tools: Synopsys FPGA Express Synplicity Synplify Exemplar Leonardo Spectrum -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18749
Theron Hicks wrote: > Can any one point me to a design for a programmable divide-by-n using an > XC4002xl device? I plan on using the fastest speed grade available in > this part. I need to divide by n, where n can be any integer from 2 to > 32. I don't care if the counter is up or down or whatever but it needs > to count with a 50% clock at 102.4 MHz. In the 1992 Xilinx Data Book ( page 6-28) I published a design called: "Fully Synchronous 5-Bit Counter Uses Only Three CLBs." This design would easily run at >150 MHz in XC4002, and even faster in the newer 'XL devices.There is no carry involved, it's a Linear-Feedback Shift Register Counter. Output wave-shape is also programmable. This particular design defines the modulus during configuration, but it can easily be made programmable from a 5-bit input at the expense of a few more CLBs. If you want, I can fax you the design, it's very simple, but non-obvious, something a grad student might appreciate. Today I would use a 3.3 V device (XL), either XC4000XL or Spartan XL. But that may depend on your power supply situation. For purely digital designs, 5 V is history ( albeit a long history!) Peter Alfke, Xilinx Applications
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