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I'd recommend the Tyan 2518 ServerWorks board: http://www.tyan.com/products/html/thunderlet.html They are relatively cheap, and are quite fully contained...no audio though, but you can get USB speakers that will do the audio over the USB, not simply take power from the USB...Philips made some, DSS350 I think they were...but for PCI testing, that's really not an issue. Regards, Austin "Ray Andraka" <ray@andraka.com> wrote in message news:3DF7ADDB.D7FB132C@andraka.com... > My mistake, I needed to find a motherboard with 64/66 PCI slots to be > guaranteed the 3V needed for the board. > > > Austin Franklin wrote: > > > Hi Ray, > > > > That may not be quite right. 64 bit has nothing to do with 3V or 5V, it's > > 66MHz that's 3V only. 64 bit can be either 3V or 5V, as it is merely adding > > 32 bits to the data path, with no change in signaling or timing. > > > > I have seen motherboards that support 64 bit, but are only 5V 33MHz. > > > > Regards, > > > > Austin > > > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:3DF580B1.FEDF0293@andraka.com... > > > The 64 bit PCI supports 3v, and any motherboard with it will work with the > > 3v > > > cards. Some of the FPGA cards such as the ISI Osiris board require a 64 > > bit slot > > > because they are 3v boards. It is rare to find 32bit PCI motherboards > > with 3v > > > support. > > > > > > Hal Murray wrote: > > > > > > > > Did 3V PCI ever take off > > > > > > > > Thanks for all the feedback. Sorry my question wasn't clear. > > > > > > > > There are two possible meanings for 3V. One is power. The other > > > > is the signaling level. > > > > > > > > First, the power stuff: > > > > > > > > The PCI connector has power pins for 5V, and 3.3V, and also a > > > > few more pins for IO power. They are either 3 or 5, depending > > > > upon the signaling voltage, the idea being that you can wire > > > > them to the supply rail for your IO pads and make a board that > > > > supports either 3V signaling or 5V, depending upon the power the > > > > motherboard supplies on those pins. > > > > > > > > The PCI connector has a plug that matches with a cutout on the > > > > board. The plug goes in either of two positions (turn the connector > > > > around), one for 5V signaling, the other for 3V. So in theory, > > > > you can make three types of cards. The normal card in wide use > > > > is 5V signaling, though they may only drive the outputs with a > > > > 3V CMOS driver. You can also make 3V only card by putting the > > > > cutout on the other end of the card. You can also make 3V/5V > > > > cards by cutting out both slots and maybe wiring the IO pad > > > > rail on your chip to the IO supply from the PCI connector. > > > > > > > > I've never seen any 3V or dual cards. > > > > > > > > The main question I was trying to ask was if anybody had seen > > > > any 3V or dual signaling level cards. If so, I might think more > > > > about taking advantage of that. Since I didn't see many > > > > encouraging responses I'll probably but this on the back burner. > > > > > > > > Some early systems didn't actually supply any 3.3V power. You > > > > can dance around that with an on-board regulator. I plan to > > > > ignore that. (But I'll check my systems first, just in case, > > > > and listen for tales of troubles with not-so-early boards.) > > > > > > > > Now for the signaling: > > > > > > > > The 3V signaling rules overlap the 5V rules enough so that a > > > > card that drives high to 3V will work in a 5V system. The > > > > catch is that some other card driving to 5V on a system that > > > > produces worst-case reflections might generate an 11V spike. > > > > "5V tolerant" is the critical term for that. > > > > > > > > The Spartan-II is 5V tolerant but doesn't have DLLs. The -IIE > > > > has DLLs, but doesn't tolerate 5V signaling. > > > > > > > > Since 3V systems don't seem to be very popular, I probably won't > > > > build a card expecting to find a 3V only slot. > > > > > > > > Several years ago, I put a scope on a system that had the connector > > > > pegs set for 5V. I never saw anything go over 3V. Obviously that > > > > depends upon what cards are plugged in. Somebody could add an > > > > old/evil card that really does drive to 5V. > > > > > > > > For hack/research systems it might make sense to use a FPGA that > > > > wasn't 5V tolerant on a card that could be plugged into a 5V system. > > > > You would have to remember to get out the scope before adding a card > > > > that hadn't been tested yet. I'm probably not desperate enough > > > > to get the DLLs that I will do this. (But I'm still scheming.) > > > > > > > > Thanks for the PLX suggestions. Their web site expects me to > > > > register before they give me data sheets so I'll put that on the > > > > back burner. > > > > > > > > Thanks for the heads-up about using DLLs on PCI clocks. Is > > > > that a clear don't-do-that, or just another worm for the list? > > > > > > > > -- > > > > The suespammers.org mail server is located in California. So are all my > > > > other mailboxes. Please do not send unsolicited bulk e-mail or > > unsolicited > > > > commercial e-mail to my suespammers.org address or any of my other > > addresses. > > > > These are my opinions, not necessarily my employer's. I hate spam. > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 50526
Hal wrote:
>I'm scheming about building a hobby/hack project that
>needs an FPGA on a PCI card. Volumes will be very low.
As others have mentioned, the original (discontinued)
Insight XCS150 PCI card was a great value; also, unlike
any other <$150 boards I've found, the expansion headers
were well grounded. [1]
By far the cheapest PCI/FPGA boards I've seen are the
original versions of the Lava PCI Parallel cards; they
used an XCS05 as the PCI interface, with a '245 buffering
the data lines to the outside world.
Unfortunately, the current production cards have switched
to an ASIC ( at least for the single parallel port version
of the card; Lava has some combo serial/parallel boards that
may still use an FPGA ). The original versions of the card
show up on ebay for $5-$10 (search for "lava PCI").
Although the XCS05 is fairly small, and has no free
synthesis tool included in the Xilinx "Webpack Classic",
you can't beat the price of a mass-produced consumer PCI
product. You could probably get at 10-20 FPGA I/O lines
on the dual version with the internal ribbon header for
the second DB25.
( and even if it never gets hacked into anything useful,
you can always plug it into your computer and use it as
a spare parallel port for the download cable needed to
program its' brethren )
see
http://www.xilinx.com/company/success/lava.htm
ftp://members.aol.com/fpgastuff/consumer_fpga_products.zip
zip file contents:
lava_rev0.jpg rev0 XCS05 PC84 (box picture)
lava_rev1.jpg rev1 XCS05 VQ100
lava_rev2.jpg rev2 ASIC
jamcam_top.jpg JamCam XCS05XL VQ100 (top)
jamcam_bot.jpg " (bottom)
Those last two .jpg's are pictures of a cheap consumer camera
product with an XCS05XL FPGA, x8 RAM, flash, imager, etc.:
a perfect target for that tiny Forth stack machine over on
some other thread :)
old JamCam 3.0 posts:
http://groups.yahoo.com/group/fpga-cpu/message/561
Brian
[1] Expansion Header Grounding (or lack thereof)
<rant on>
I've got no complaints with the choice of dual row 0.1" headers
as expansion connectors, but if the companies selling these
inexpensive boards want the end user to be able do something
other than read DIP switches and blink LEDs, put some more
grounds on those expansion headers!
The typical cards I've found hook between 20 and 84 FPGA I/O
pins, with modern CMOS sub-ns edge rates, up to a header with
maybe one GND and one VCC, which are often huddled together
for warmth at one end of the expansion header.
( Student assignment: simulate a connector with an edge sensitive
strobe held at logic '0' on pin 1, 48 addr/data lines toggling
from '1'<->'0'on pins 2-49, and one ground on pin 50; assume
2.5V CMOS with 400 ps edge rates. )
My personal inclination would be to ground one entire side of the
dual row header, but some might consider that extreme; there should
be at least one nearby ground (or bypassed VCC) pin for every few
signal pins to support high speed I/O to an expansion card.
<rant off>
Article: 50527
A better solution is to use GSR for general reset, and then use a locally
synchronized version of it to hold off release to the flip flops that must come
out of reset together, that way you don't chew up a bunch of routing resources.
Falk Brunner wrote:
> "hristo" <hristostev@yahoo.com> schrieb im Newsbeitrag
> news:b0ab35d4.0212110739.377c8625@posting.google.com...
> > as a follow up to my previous messages
> > will the user clock be running during the Fpga startup phase?
> > we have read a lot about the GSR slow propagation through the chip, so
> > why not just delay the input data for some clock cyles till we will be
> > sure that GSR has run through all the chip?
>
> Hmm, not so practicable. The effect you describe is a possible lock-up of
> state-machines if the reset is not fast enough, so a half of the state
> machine is already running where the other half is still held in reset. The
> solution against such bad things is to use normal routing ressources to
> drive the reset for FSMs, which is MUCH faster but required some routing
> ressources. No bad deal after all.
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50528I wrote: >Unfortunately, the current production cards have switched >to an ASIC ( at least for the single parallel port version Upon re-visiting the Lava website tonight, I also found: http://www.lavalink.com/techsupport/specialty/sup_8255_pio.html Advertised as an 8255 I/O card, it looks like consists of an FPGA with 24 I/O lines brought straight out to a DB-25. (Hmmm, 25 pins - 24 I/O signals leaves one,uno,ein GND pin.) $99 list, $69 at http://www.buyiocard.com/pciserial/8255pio.asp I can't read the part number in the datasheet picture, it looks like the same XCS05 VQ100 used on the older boards. BrianArticle: 50529
Uwe Bonnes wrote: > > Austin Lesea <austin.lesea@xilinx.com> wrote: > : Uwe, > > : The 2VP4 and 2VP7 (Virtex II Pro) consume only a few hundred milliamperes > : when the > : junction temeprature is 85C from internal leakage. > > : Just because Intel designs in a particular fashion does not mean that > : everyone has > : to do the same thing. > > > http://www.theinquirer.net/?article=6677 I take it you have not read about the new transistors that are being designed to deal with this problem? They are trying transistors with dual gates and "fins" and other structures to force the channel to turn off more fully at lower voltages and geometries. I can't give you a link, but you can go to the Yahoo! stock pages and look at the news for INTC and AMD. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50530
Hi I have a vhdl project that makes use of a package that lives in an external vhdl file. The package contains a whole lot of constants. It is basically a look-up table. The project compiles & simulates perfectly in Quartus 2.1. Now when I come to make a symbol for it to use in another project, the wheels fall off! I open the vhdl logic file, click on tools and then click on "Create symbol files for entities in current file". Then a whole lot of errors come up to do with the external package. Now if I cut the package and paste it into the logic vhdl file, then it creates a symbol for the block no problem. What am I doing wrong? Suggestions would be most welcome. Thanks RyanArticle: 50531
prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0212100912.34df6440@posting.google.com>... > Hi, > Use the website below to get a free layout editing tool. It has user > manuals which help you build your multiplier as well as many other > features such as schematics. You can also build a schematic and then > automatically generate a layout. I have used the tool and found it to > be fairly decent for class projects. The best part is that the tool is > absolutely FREE !! > > http://intrage.insa-tlse.fr/~etienne/Microwind/index.html > > > bye, > Prashant Microwind seems to be a good solution. However, I don't want to draw every single transistor. I want to connect building blocks like full adders and 4:2 compressors to built the multiplier easily. Another problem is portability. What if I complete the layout for 0.5um technology and want to port it to .1um . Do I have to redraw the complete layout? Thanks > > > compresstransform2002@hotmail.com (transformer) wrote in message news:<4a96bae1.0212081216.60ca70bf@posting.google.com>... > > Dear All, > > I have completed my work on a radix-4 booth multiplier. Now I have to > > complete its vlsi layout. Unfortunately, I have only some vhdl > > knowledge and completely new to vlsi design. Which free or low-priced > > vhdl design software is suitable for my needs. > > ThanksArticle: 50532
Hi,
Following is a Handel-C program which reads a 128-bit data,
copies the data to a buffer and, finally, the buffer contents are
given to the output pins.
The data input/output interface is 32-bit unidirectional.
After implementing the given design on a Xilinx Virtex-II FPGA,
I'm getting a clock speed of 126.374MHz.
How can a better clock speed can be achieved?
Any assistance appreciated.
Regards,
Saurabh Pal
--------------------------------------------------------------------------------
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 4773 paths, 458 nets, and 1241 connections (100.0%
coverage)
Design statistics:
Minimum period: 7.913ns (Maximum frequency: 126.374MHz)
Maximum net delay: 2.905ns
--------------------------------------------------------------------------------
set clock = external;
interface bus_clock_in (unsigned int 32) DinBus();
unsigned int 32 bus_out;
interface bus_out () DoutBus(unsigned int 32 out = bus_out);
macro proc getData(data)
{
unsigned int 2 index;
signal <unsigned int 32> sig_data;
do
{
par {
index++;
sig_data = DinBus.in;
data[0][index] = sig_data[31:24];
data[1][index] = sig_data[23:16];
data[2][index] = sig_data[15:8];
data[3][index] = sig_data[7:0];
}
} while (index != 0);
}
macro proc putData(data)
{
unsigned int 2 index;
signal <unsigned int 32> sig_data;
do
{
par {
index++;
sig_data = data[0][index] @ data[1][index] @ data[2][index] @
data[3][index];
bus_out = sig_data;
}
} while (index != 0);
}
macro proc Copy(state_in, state_out)
{
unsigned 3 row,col;
par(col=0; col<=3; col++)
{
par(row=0; row<=3; row++)
{
state_out[(row<-2)][(col<-2)] = state_in[((row)<-2)][(col<-2)];
}
}
}
void main()
{
unsigned 8 data_in[4][4], data_out[4][4];
do{
par{
getData(data_in);
Copy(data_in, data_out);
putData(data_out);
}
} while(1);
}
Article: 50533Hi, I have an asynchronous input to a synchronous system. I want to calculate MTBF for a simple synchronizer(using only one synchonizing FF). Details are here below. 1.Device Virtex-E, -8 speed grade, CLB flip-flops used 2.Asynchronous input rate = 8KHz 3.Clock frequency = 80MHz Could anybody in the group help me in finding out the MTBF? Regards, NagarajArticle: 50534
> No, there is no guarantee you will get 3.3V power, unless you are in a 3.3V
> slot!
> I would not ignore that. Most systems don't have the 3.3V power, not just
> "early" ones.
Thanks! I'd missed that.
> Well, not really. The important issue isn't voltage but the VI curve.
Thanks again. Another important concept I'd missed.
> > I've never seen any 3V or dual cards.
> I have done quite a few of them.
My sample is probably biased by being a couple of years old.
I found some/many from the SGI list and browsing the web,
But no serial cards that I could put into a 3V system?
Maybe I'm supposed to do serial over USB now.
[PLX web site requires registration]
> Why is registering a problem?
0) Why should I register to get a data sheet?
Why should I encourage people to require registration?
I can get the chips via Yahoo so they can't be
protecting any secrets.
1) I'm a privacy nut.
2) I hate wasting my time explaining why I'm interested
and that I'm not going by buy a truckload of their chips.
3) I hate spam...
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 50535
This is probably a trivial question, be patient :). I have the following
VHDL module:
architecture Behavioral of cntdiv is
begin
process( CLKIN, PULSE)
variable cnt2: std_logic_vector( 7 downto 0);
begin
if CLKIN='1' and CLKIN'event then
QOUT <= cnt2;
cnt2 := "00000000";
elsif PULSE='1' and PULSE'event then
cnt2 := cnt2+1;
end if;
end process;
end Behavioral;
XST returns the error: "Signal cnt2 cannot be synthesized, bad synchronous
description". I have two questions:
1) Why?
2) How can I syntesize a module like that (something that counts the number
of clock pulses between the period of another clock - obviously PULSE has a
frequency greater than CLKIN)?
--
Lorenzo
Article: 50536Hi, I am planning to use an Altera Cyclone/ACEX device in place of my existing XC2S200E device. However, as I use lot of distributed RAM, I cannot easily go to Cyclone/ACEX as they do not support distributed RAM like Xilinx. Can anyone tell me how to efficiently convert the spartan-2e distributed RAM primitives into Cyclone/ACEX block ram architecture. What i need to know is how to convert 80 nos of 16X1 RAM, I have implemented in spartan-2e to cyclone architecture w/o consuming too much space. Thanks!Article: 50537
"Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0212120136.519f0b2b@posting.google.com... > Hi, > I have an asynchronous input to a synchronous system. I want to > calculate MTBF for a simple synchronizer(using only one synchonizing > FF). > Details are here below. > 1.Device Virtex-E, -8 speed grade, CLB flip-flops used > 2.Asynchronous input rate = 8KHz > 3.Clock frequency = 80MHz > > Could anybody in the group help me in finding out the MTBF? There's a Xilinx app note XAPP094 which has details of metastability for older devices. There's a nice application note at www.cypress.com Go to "support" and search for "metastable" and you can find the note "Are your PLDs metastable?" which explains how to calculate the probability of a metastable event. I hope this helps, Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 50538
Hi, When you create a symbol Quartus must find the symbol in the current project - so I think you have to add the design files to the project in the Project menu. Perhaps that could help you!? Regards, Thomas "Ryan" <ryans@cat.co.za> wrote in message news:<3df8b929.0@obiwan.eastcoast.co.za>... > Hi > > I have a vhdl project that makes use of a package that lives in an external > vhdl file. The package contains a whole lot of constants. It is basically a > look-up table. The project compiles & simulates perfectly in Quartus 2.1. > Now when I come to make a symbol for it to use in another project, the > wheels fall off! I open the vhdl logic file, click on tools and then click > on "Create symbol files for entities in current file". Then a whole lot of > errors come up to do with the external package. Now if I cut the package and > paste it into the logic vhdl file, then it creates a symbol for the block no > problem. > > What am I doing wrong? Suggestions would be most welcome. > > Thanks > RyanArticle: 50539
Hi, I'm currently programming a NIOS Processor in C. Does anyone know how to access the STATUS register to stop interupts for parts of the program. Or does anyone know how to implement NIOS Assembler Routines in C Code? Thanks for your help! ThomasArticle: 50540
Hi! About handling interrupt enable (IE): look at Nios 32-bit (or 16-bit) Programmer's Refference Manual (page 5). http://www.altera.com/literature/manual/mnl_nios_programmers32.pdf http://www.altera.com/literature/manual/mnl_nios_programmers16.pdf About asm in C: You can make macro functions of asm in a separate c or header file and define it and reference it just like a c function. It suits for me fine. Take a look at: http://www.redhat.com/docs/manuals/gnupro/GNUPro-Toolkit-99r1/2_comp/Using_G NU_CC/gccAssembler_Instructions_with_C_Ex.html Regards, Matjaz "Thomas Pollischansky" <polly@rz.fh-augsburg.de> wrote in message news:6b0e63fc.0212120528.20dc335@posting.google.com... > Hi, > > I'm currently programming a NIOS Processor in C. > Does anyone know how to access the STATUS register to > stop interupts for parts of the program. > Or does anyone know how to implement NIOS Assembler Routines in C Code? > Thanks for your help! > ThomasArticle: 50541
Hi, I have generated a RPM using Xilinx's ISE5.1i FloorPlanner as per the XAPP422. I got a .ucf file which contains the RLOC contrains for all FFs, LUTs...etc., Which element is took a a reference for this RLOC creation. I viewed the element which is located in X0Y0 in the Floor Planner is some FG. But if i see the corresponding RLOC in .ucf, it is not X0Y0. It is some other location. My Macro occupied the FPGA as below. ------------------- | | | FPGA | | | | | |------- | | MD | | |------------------| MD- My design macro. Since it used .ucf file generated from the floor planner (RPM) it is placing as above. Say i want to shift MD to the upper Right Corner. I know that this can be done with RLOC_ORIGIN. But my question is to which instance i have give the RLOC_ORIGIN. I tried as below. I have just gave the RLOC_ORIGIN for the very first RLOC element in the .ucf file. But it is giving, out of boundary error. And one more question is, MD is having some BRAMs too. The RLOC for the BRAM is not written in the .ucf ( i hope so) so, BRAMs are placed randomly. How can i freeze the BRAM position too. Xilinx XAPP412 talks something about RPM_GRIDs. But any one can give some examples on this. Thanks in advance. Best regards, MuthuArticle: 50542
Hi Is it possible to write data to a file while simulating in Quartus 2.1? I am debugging a project at the moment and it would be extremely handy if you could. If anybody has, please could you post such an example. I am battling to get the line variable/signals correct! Thanks RyanArticle: 50543
What are the correct black box component declarations for the READBACK, RDBK, and RDCLK components?<br> <br> These are what I thought were correct:<br> <br> component RDCLK<br> port (I: in std_logic);<br> end component;<br> <br> component RDBK<br> port (TRIG: in std_logic;<br> DATA: out std_logic);<br> end component;<br> <br> component READBACK<br> port (CLK: in std_logic;<br> TRIG: in std_logic;<br> DATA: out std_logic);<br> end component;<br> <br> I initially was only going to use the READBACK declaration. I wish to use my user clock instead of CCLK, however I received an error after synthesis during implementation that the component READBLOCK could not be expanded.<br> <br> I then switched to the RDBK and RDCLK macros that according to the XC4000XL library guide make up the READBACK macro. This eliminated the unexpanded block error I received during Translate.<br> <br> However, after implementation according to the map report the RDCLK component was loadless and removed as well as te RDBK component. My TRIG input port was not placed althought the DATA port was still placed, albeit with no connected signals to drive the pad. I verified this in the FPGA editor.<br> <br> Thanks for any insight<br> AEArticle: 50544
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote in message news:<JWYJ9.8756$ab2.251993@news1.tin.it>... > This is probably a trivial question, be patient :). I have the following > VHDL module: > > architecture Behavioral of cntdiv is > begin > process( CLKIN, PULSE) > variable cnt2: std_logic_vector( 7 downto 0); > begin > if CLKIN='1' and CLKIN'event then > QOUT <= cnt2; > cnt2 := "00000000"; > elsif PULSE='1' and PULSE'event then > cnt2 := cnt2+1; > end if; > end process; > end Behavioral; > > > XST returns the error: "Signal cnt2 cannot be synthesized, bad synchronous > description". I have two questions: > > 1) Why? Since the standard FF has only one input which is operating on the edges.(i.e., clock input), no other edge active inputs are not allowed. > 2) How can I syntesize a module like that (something that counts the number > of clock pulses between the period of another clock - obviously PULSE has a > frequency greater than CLKIN)? Interesting....I will put your example in different manner. say the HCLK ---> High frequency clock. LCLK ---> Low frequency clock. The aim is to count the number of HCLK positive edges in between the LCLK positive edges. Since this is an asynchronous Design The trick is as below: 1. Just Increment a counter with HCLK always 2. Detect a the rising edge of the LCLK by sampling the LCLK with respect to HCLK edges, and generate a Pulse with respect to HCLK. 3. This pulse has to go as a Asynchronous RESET input to the Counter. Hope this helps. Regards, MuthuArticle: 50545
Muthu, When using RLOC_ORIGIN, make sure you're appending it to comp that has RLOC of X0Y0 since RLOC values accumulates. ex. RLOC_ORGIN at slice_x10Y10 on comp that has RLOC of X5Y5 will result in the comp be loc-ed at X15Y15. So when you're trying to Loc down the RPM, make sure the accumulated RLOC_ORIGIN value isn't pushing part of your RPM out of the device slice boundary. As for BRAMs, MULTs, Floorplanner's RPM creation will leave them unconstrained. You can either manually create another RPM for the BRAM/MULTs, or go over XAPP416 on the exact detail of using it. Basically, user has to read teh RPM_GRID coordinate from FPGA Editor and manually append the RPM_GRID coordinate value to the RPM. Note that Floorplanner doesn't fully support RPM_GRID yet. Regards, Wei Muthu wrote: > Hi, > > I have generated a RPM using Xilinx's ISE5.1i FloorPlanner as per the > XAPP422. > > I got a .ucf file which contains the RLOC contrains for all FFs, > LUTs...etc., > > Which element is took a a reference for this RLOC creation. I viewed > the element which is located in X0Y0 in the Floor Planner is some FG. > But if i see the corresponding RLOC in .ucf, it is not X0Y0. It is > some other location. > > My Macro occupied the FPGA as below. > > ------------------- > | | > | FPGA | > | | > | | > |------- | > | MD | | > |------------------| > > MD- My design macro. > > Since it used .ucf file generated from the floor planner (RPM) it is > placing as above. > > Say i want to shift MD to the upper Right Corner. > > I know that this can be done with RLOC_ORIGIN. But my question is to > which instance i have give the RLOC_ORIGIN. > > I tried as below. I have just gave the RLOC_ORIGIN for the very first > RLOC element in the .ucf file. But it is giving, out of boundary > error. > > And one more question is, MD is having some BRAMs too. The RLOC for > the BRAM is not written in the .ucf ( i hope so) so, BRAMs are placed > randomly. How can i freeze the BRAM position too. > > Xilinx XAPP412 talks something about RPM_GRIDs. But any one can give > some examples on this. > > Thanks in advance. > > Best regards, > MuthuArticle: 50546
Is it possible to use a smaller configuration device with Xilinx FPGA than forseen? I my case I have forseen a XC2S200 on the board and I have XC18V01 and XC2S200 on stock. The XC2S200 has about 1.3 million configuration bits, but the xc18v01 can only hold one milion. The Spartan is only partial filled (with all block ram used): The mapper report tells: Number of Slices: 629 out of 2,352 26% PS: I found the bitgen compress option, but only about 50000 bits where saved. Any other option? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50547
"Muthu" <muthu_nano@yahoo.co.in> ha scritto nel messaggio
news:28c66cd3.0212120657.2814b0d6@posting.google.com...
> 1. Just Increment a counter with HCLK always
> 2. Detect a the rising edge of the LCLK by sampling the
> LCLK with
> respect to HCLK edges, and generate a Pulse with respect
> to HCLK.
> 3. This pulse has to go as a Asynchronous RESET input to
> the Counter.
>
> Hope this helps.
Thank you, I'll try. In the meanwhile I've found a way that works, but I
don't fully understand how: :-)
architecture Behavioral of cntdiv is
begin
process( CLKIN, PULSE)
variable cnt: std_logic_vector( 7 downto 0);
variable oldcnt: std_logic_vector( 7 downto 0);
begin
if CLKIN='1' and CLKIN'event then
QOUT <= cnt-oldcnt;
oldcnt := cnt;
end if;
if PULSE='1' and PULSE'event then
cnt := cnt+1;
end if;
end process;
end Behavioral;
--
Lorenzo
Article: 50548compresstransform2002@hotmail.com (transformer) wrote in message news:<4a96bae1.0212120056.1d9a791f@posting.google.com>... > prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0212100912.34df6440@posting.google.com>... > > Hi, > > Use the website below to get a free layout editing tool. It has user > > manuals which help you build your multiplier as well as many other > > features such as schematics. You can also build a schematic and then > > automatically generate a layout. I have used the tool and found it to > > be fairly decent for class projects. The best part is that the tool is > > absolutely FREE !! > > > > http://intrage.insa-tlse.fr/~etienne/Microwind/index.html > > > > > > bye, > > Prashant > > Microwind seems to be a good solution. However, I don't want to draw > every single transistor. I want to connect building blocks like full > adders and 4:2 compressors to built the multiplier easily. Another > problem is portability. What if I complete the layout for 0.5um > technology and want to port it to .1um . Do I have to redraw the > complete layout? > > Thanks > > > > > > > > > compresstransform2002@hotmail.com (transformer) wrote in message news:<4a96bae1.0212081216.60ca70bf@posting.google.com>... > > > Dear All, > > > I have completed my work on a radix-4 booth multiplier. Now I have to > > > complete its vlsi layout. Unfortunately, I have only some vhdl > > > knowledge and completely new to vlsi design. Which free or low-priced > > > vhdl design software is suitable for my needs. > > > Thanks For your case you should draw a schematic and then convert it to a layout using the automatic layout generator in Microwind. I'm not sure how the porting from one tech to another works (its been a while since I used it), but my guess is that a schematic will port to whatever tech you want it to, provided you have the required technology files. bye, PrashantArticle: 50549
hi, help.. help.. how do i have to design my state machine in vhdl code, so that a synthesis tool, like fpga express translates the state machine into the xilinx BlockRam? can anyone help me, or send me a snip of vhdl-code wbr.. millim
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