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1) Read the PCI spec Rev 2.1 Para 3.4 2) Here's an HDL file of an PCI arbiter- http://www.galileot.com/file/boardsw/gal4pa00.tdf 3) Here's an schematic for an PCI arbiter - http://developer.intel.com/design/IIO/applnots/APPNDX_C.PDF Good luck ..... Sebastien wrote: > Hi all, > > I am looking for a PCI arbiter > "core" that could be dropped in a Xilinx FPGA. Preferably a V-2 part. Would you have any idea who would have that?Article: 33401
I'll throw in my $.019999 worth and mention that a major difference between WinNT/2k and DOS (aka Win95/98/ME) is in the area of command line processing. I've seen a lot of issues with command lines working on NT and not on Win9X, amongst other things Win9X limits command lines to (I think) 256 characters. Another issue is environment space. These issues can cause scripts/batch files that work fine on NT to fail on 9X. Speaking only for meself and not Xilinx, -Dennis McCrohan Andy Rushton wrote: > "Gary Spivey" <spivey@ieee.org> writes: > > > Has anybody had any experience running ModelSim on a Windows box (currently > > Windows98) within the cygwin environment? > > Not exactly, I have win2k. I'm not exactly sure what your problem is? I just > tried vsim from cygwin's bash shell and I got the GUI okay. I also tried > running vish and got the '%' prompt and could run a few commands. I even ran > vsim from within vish and got the GUI. It all seems to work okay. So I'm not > helping you sort your problem! The only ModelSim-specific environment I have > are LM_LICENSE_FILE and PATH. > > I haven't tried ModelSim in win98 although I've had no problems with cygwin in > that environment. > > -- > Andy Rushton > LME Design Automation Limited, UKArticle: 33402
This is a tricky problem, and it is common to all BGAs not just Xilinx devices, but programmable logic may offer a solution: You want to have significant Icc, and then you want to observe whether there is a Vcc gradient on the internal supply. I would reconfigure the chip with a bunch of distributed local oscillators ( odd number of inverting CLBs feeding back in a loop), and you can then observe the relative frequency of these oscillators. If one is significantly slower than the others, it indicates a missing Vcc connection. Power consumption must be such that the chip gets hot, otherwise you may not see the effect. Just my $ 0.02 worth. Peter Alfke ( back from a 3-week vacation) ====================================== Jon wrote: > Gary Cook <gc@sonyoxford.co.uk> writes: > > > can anyone suggest a way of determining whether the > > power pins are soldered correctly. We can check the i/o pins > > Beyond measuring some supply current would it be safe to pass a larger > current (hundreds of milliamps) between power pins with everything > else isolated and floating ? > > JonArticle: 33403
Unfortunately, you will have to get a copy of Xilinx's legacy tool called XACT. We use both the Alliance and XACT toolset to support Xilinx legacy and new devices... Tran Cong So wrote: > Hi, > I have now to design on a very old FPGA XC4010 (not E or XL). > The problem is the current development softwware that I am using is Fondation ISE 3.1 and this version does not support for xc4000 family and the old software XACT Step 5.2/Sun is out of license. I tried to contact distributor to get new license but just have got the NOT SUPPORT because the software (XACTStep) is too old. > Does any one have an idea how to be able to work with XC4000 family at this time ? The device is not replacable because replacement means to destroy the PCB. > Thank you very much. > Tran Cong So.Article: 33404
Russell Shaw wrote: > > Hi all, > > I tried out Synopsys FPGA Express (free from altera for the pc) > and found the editor to be really awful. Surely they'd have syntax > highlighting in this day and age? The error messages and pdf > based help system are really not something i'd describe in a > public place<g> Forget the editor! Use Spectrum because FPGA Express sucks eggs as a synthesis tool. > I couldn't try Leonardo Spectrum until i get an old network > card with NIC. Will it work without a network connected? (using > win2k) All it uses the network card for is its MAC address, which is a unique identifier that the licensing tool uses to guarantee that your copy of the program doesn't run on other computers. Unless you remove the NIC and put it in a different computer. Which is possibly one Real Good Reason to buy a CardBus (PC Card) adapter for your PC and stick a CardBus NIC in it, and tell the licensing people the MAC address of the CardBus NIC. Hmmm...am I going to be arrested for mentioning a way of circumventing a licensing scheme? That Digital Millenium Copyright Act can reach far, far, far... And, on another note, remember all of the hoopla that arose when Intel announced that they had put a serial number in each Pentium II (or III, I don't remember)? At the time, I thought the hoopla was silly, since every NIC has a unique serial number, too, and software vendors use it for EXACTLY the same reasons people bitched at Intel for. Note that I in no way, shape or form defending Intel here (I have Athlon boxes and Macintoshes). Anyone wanna here how one can circumvent any sort of copy protection scheme that the music industry and their lackey SDMI come up with? So, yes, the tool will work without the Cat5 cable going from your computer to somewhere else. > Whats Leonardo like compared to spectrum for the editor and > help system? I never use the editor -- emacs all the way, baby. The help system is reasonable, not great, but I've noticed that online help systems always seem to omit the ONE THING you're looking for help on. -andyArticle: 33405
Russell Shaw wrote: > > Hi all, > > I tried out Synopsys FPGA Express (free from altera for the pc) > and found the editor to be really awful. Surely they'd have syntax > highlighting in this day and age? The error messages and pdf > based help system are really not something i'd describe in a > public place<g> The Altera_oem_leonardo has an editor with basic highlighting. But I would rather not tie up a network license editing text, and emacs vhdl-mode if far superior. What the leo editor is good for, is that you can right-click on a synth output schematic element and pick "trace to hdl source" to find out what you did to create that box. > I couldn't try Leonardo Spectrum until i get an old network > card with NIC. Will it work without a network connected? (using > win2k) I use it with a floating network license on my win2k box. It also runs on solaris, but the GUI is unstable on that platform. > Whats Leonardo like compared to spectrum for the editor and > help system? They just changed the name from Leonardo to LeonardoSpectrum. It's an alias, not a different thing. The other marketing alias, LeonardoInsight just means the links between schematic and code, most of which you get in the oem version. Except for for the fact that it is Altera-only, the oem version is a full-up level2 vhdl+verilog tool The exemplar spin on this is in: http://www.exemplar.com/support/faq_aboutLeoSpec.html#q4 --Mike TreselerArticle: 33406
Hello, All! I look for news about boundary scan. If any, tell me. -- Thank you. Yours, Igor KoulikovArticle: 33407
Hi all, I was wondering if anyone can confirm this: if I want to, lets say, digitally mix my bandwidth by pi/2, in other words shift the unit circle in the z plane by 90 degrees, all I need to do is multiply my incoming samples by the sequence 1,+j,-1,-j. Is this correct? I have implemented this in a schematic design, but it doesn't appear to be working as I had hoped. Any other ideas? adrianArticle: 33408
Michael, It is an EDIF file (ver 2 0 0 probably). It seems that www.edif.org is down. Here is another link I found that may be of some help: www.ecsi.org/earnest/digests/EDIF/default.htm Regards, Paul On Mon, 23 Jul 2001 11:44:45 +0200, Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote: >I am looking for an online description of the EDN netlist format. Does >anybody know such a site? >Is there free source code for the analysis of EDN-Files available? > >Michael >Article: 33409
Problem 1: Time and budget - try justifying a CPLD/FPGA design to your boss. Problem 2: Real Time and Cost of FPGA design - After your first experience with FPGA design, where are you going to work next? FPGA/CPLD vendors need to be more up front as to the time, cost and difficulty of doing a design. Don't pay anyone anything until you know for sure what you are getting into. Although Webpack is touted as free, beware of the following obstacles: (1) Free software is of no value without technical support. Xilinx does tech support (you might have to wait a day for each of your questions). (2) ModelSim XE Starter is free if you limit your code to 500 lines or less. (3) HDL Bencher is free if you do not exceed 21 I/O lines. They give you a $500 discount if you go over that limit. You could always use the TestBench or TextIO (haven't tried this yet). (4) How much does it really cost to do a design? Like any other Newsgroup, expect to be SPAM'd or Flamed. Not everyone out there is out to make a buck off your hide, however. Some people actually know what is going on and should be heard from more often. -DaveArticle: 33410
Cyber_Spook_Man "Andy Peters > > > Hmmm...am I going to be arrested for mentioning a way of circumventing a > licensing scheme? That Digital Millenium Copyright Act can reach far, > far, far... Not a problem if the lic is in the same form as everyone elesis, "One copy in use at any one time", That all they are trying to do. I think the NIC (MAC Address) is better than using the harddrive serial number, than atleast you can upgrade a machine or bin it while keeping the old network card.Article: 33411
I tried both and like Leonardo.
Easier to handle and the results are better than Synopsys (less LCs, higher
clock).
You need a network card for Leonardo.
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
"Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag
news:3B5E5419.34F185E8@iprimus.com.au...
> Hi all,
>
> I tried out Synopsys FPGA Express (free from altera for the pc)
> and found the editor to be really awful. Surely they'd have syntax
> highlighting in this day and age? The error messages and pdf
> based help system are really not something i'd describe in a
> public place<g>
>
> I couldn't try Leonardo Spectrum until i get an old network
> card with NIC. Will it work without a network connected? (using
> win2k)
>
> Whats Leonardo like compared to spectrum for the editor and
> help system?
>
> --
> ___ ___
> / /\ / /\
> / /__\ / /\/\
> /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
> \ \ / Victoria, Australia, Down-Under \ \/\/
> \__\/ \__\/
Article: 33412Austin Lesea schrieb: > > Falk, > > In the worst case, the power might be more, and more by the amount > predicted. > > I seldom get in trouble for having engineers design a power supply bigger > than the actual load, and a heat removal system more capable than what is > required. yes, but when it is oversized by the factor of 10, some question can arise. And when space and pwer is critical, every mW counts. > Good engineering practice uses safety factors of 2 or 3 or 4. Of concern > is when each person in the chain applies their X2, leading to a over > engineering of the system (X2 X2, X2 ... X8???). Hmm. > The ultimate solution is the thermal one, as watts in, will result in watts > out, as heat. Can you isolate the heat generated by the FPGA? I know, Iam getting complicated ;-) -- MFG FalkArticle: 33413
bob elkind wrote: > 1. The is and will only be *one* Peter Alfke (had to throw that one in!). > (I was on a 3-week vacation) Thanks for the friendly words, but here are some corrections: BTW, there are two more P A's in the pipeline, my son works at Apple R&D and is an exceptionally good writer, and his son is in kindergarten. So there is hope... > Peter Alfke is in one such group at Xilinx, but he has the charter to *span* > these distinct groups and act as an ombudsman to this newsgroup. > Xilinx gave Peter such a charter; without it he would have had his > keyboard-typing fingers chopped off (both of them) for crossing > marketing/sales/tech support boundaries. Not really true: Xilinx never asked me to monitor this NG, I just started on my own. I was not issued iron underwear, and I never asked for permission, nor did I have to accept any censorship ( but I routinely check for technical accuracy). And I have never EVER been reprimanded, not even by Marketing. Two reasons: 1. Seniority ( 10 years of telecom and computer design in Europe plus 30-odd years of applications engineering) plus lots of grey hair ;-) 2. Xilinx is an enlightened company. No "command-and-obey", nor "shouting-in your-face", nor "cow-towing to the King", nor other weird management practices used by some of our competitors. Silicon Valley is really just a village where we know each other very well. And Xilinx is the best place to work, because good people are respected and entrusted here. I am living proof. End of commercial. > I repeat, these postulations are nothing more or less than my own guesses. > I'm sure Peter will help clarify or correct these wild guesses I just did > I may be way off base on this, but I sure had fun writing it! Same here. PeterArticle: 33414
Peter Alfke wrote: > bob elkind wrote: > > > 1. The is and will only be *one* Peter Alfke (had to throw that one in!). > > > > (I was on a 3-week vacation) Thanks for the friendly words, but here are some > corrections: > BTW, there are two more P A's in the pipeline, my son works at Apple R&D and is an > exceptionally good writer, and his son is in kindergarten. So there is hope... > # We were all beginning to get worried - we can relax. > > > Peter Alfke is in one such group at Xilinx, but he has the charter to *span* > > these distinct groups and act as an ombudsman to this newsgroup. > > Xilinx gave Peter such a charter; without it he would have had his > > keyboard-typing fingers chopped off (both of them) for crossing > > marketing/sales/tech support boundaries. > > Not really true: > Xilinx never asked me to monitor this NG, I just started on my own. I was not > issued iron underwear, and I never asked for permission, nor did I have to accept > any censorship ( but I routinely check for technical accuracy). And I have never > EVER been reprimanded, not even by Marketing. ... and you don't get it wrong very often either. The only iron-briefs situation you've really been in is the Spartan2 saga & there you were really the only one being straightforward. If marketing didn't get at you for that one they're unlike any marketing dept. I've ever come across. > > Two reasons: > 1. > Seniority ( 10 years of telecom and computer design in Europe plus 30-odd years of > applications engineering) plus lots of grey hair ;-) > 2. > Xilinx is an enlightened company. No "command-and-obey", nor "shouting-in > your-face", nor "cow-towing to the King", nor other weird management practices > used by some of our competitors. Silicon Valley is really just a village where we > know each other very well. And Xilinx is the best place to work, because good > people are respected and entrusted here. I am living proof. End of commercial. > Sounds like a younger version of HP.Article: 33415
I have installed a licensed version of the 60 day eval version of Xilinx ISE Foundation and the 30 day Modelsim package but I am plagued with license-related problems that prevent the software from working. I don't see this situation getting any better in the future. I am now seriously considering uninstalling this software and going to Webpack (at least it's free with no time constraints). If I had a way to generate Spartan 2 and Virtex 2 FPGA configuration bit files from the output of gEDA tools and then download the configuration files to the hardware, I would switch to them immediately on the grounds that, whatever shorterm problems I might have with them, the longterm lack of licensing problems would more than compensate. "David Wright" <dwright@srtorque.com> wrote in message news:SPF77.26031$sE4.518712@news6.giganews.com... > Problem 1: Time and budget - try justifying a CPLD/FPGA design to your > boss. > > Problem 2: Real Time and Cost of FPGA design - After your first experience > with FPGA design, where are you going to work next? > > FPGA/CPLD vendors need to be more up front as to the time, cost and > difficulty of doing a design. Don't pay anyone anything until you know for > sure what you are getting into. > > Although Webpack is touted as free, beware of the following obstacles: > > (1) Free software is of no value without technical support. Xilinx does > tech support (you might have to wait a day for each of your questions). > (2) ModelSim XE Starter is free if you limit your code to 500 lines or less. > (3) HDL Bencher is free if you do not exceed 21 I/O lines. They give you a > $500 discount if you go over that limit. You could always use the TestBench > or TextIO (haven't tried this yet). > (4) How much does it really cost to do a design? > > Like any other Newsgroup, expect to be SPAM'd or Flamed. Not everyone out > there is out to make a buck off your hide, however. Some people actually > know what is going on and should be heard from more often. > > -Dave > >Article: 33416
Well everybody! Did you put jumpers on centronics connector if not do not expect you cable can work Iouri Rick Filipkiewicz wrote: > Greg Neff wrote: > > > On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe > > <nicolas.matringe@IPricot.com> wrote: > > > > We have incorporated this logic into a few of our test sets. The > > biggest problem that we found is that the 74HC125 input buffers are > > very sensitive to input noise, producing glitches on the outputs. > > Glitches on CLK are bad news. I guess those capacitors on the HC125 > > outputs are supposed to be a fix for this, but they would have been > > more effective on the inputs. > > > > We added pairs (series connected) of 74ACT14 Schmitt trigger inverters > > in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a > > 68pf cap to ground on the CLK input at the parallel cable connector. > > This circuit has worked flawlessly ever since, even with long cables. > > Interesting. Our - purely accidental - solution seems to be that we replaced > the 'HC125s with LS125s. > > Or was it accidental ? I have a feeling that our ancient ca 1996/7 > Parallel-III cable might not use the HC parts, these might have been added to > program XL devices on pure 3V3 boards - I'll check.Article: 33417
From: Jason Stratos Papadopoulos <jasonp@y.glue.umd.edu>
Subject: prospects for a tiny FPGA supercomputer?
Newsgroups: comp.arch.fpga
Organization:
Summary:
Keywords:
User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (SunOS/5.7 (sun4u))
Hello. Please pardon the following stack of ignorant questions from a
software weenie. I know a little about hardware and a little more about
computer architecture (picked up on the job).
I was amazed when I found out about these guys, who apparently built
their own little (integer only) vector processor which they intended
to use for fixed point neural net training.
http://www.icsi.berkeley.edu/real/spert/t0-intro.html
This is a chip with a simple processor core, and 16 enormous vector
registers (32 x 32-bit words each). The vector registers fed 8 words
at a time to one of two clusters of 8 pipelined functional units each,
and the chip had eight 16-bit integer multipliers. The PhD students on
this project got HP to implement it in about 750,000 gates (1995
technology), and it beat the pants off the expensive workstations of the
day at the specialized tasks the chip was designed for.
I was wondering if it would be possible to pack a 64-bit version of this
kind of vector processor into latter-day programmable logic; specifically
something with a group of 64-bit ALUs that could do adds, subtracts and
64 x 64 bit pipelined integer multiplies as fast as possible. A beast like
this would be very useful for the very large integer convolutions I
continually find myself doing, and for which conventional general-purpose
processors are way too slow for my taste.
If by some chance this is feasible, I've further deluded myself into
believing that with enough patience I can actually design such a thing in
my spare time and on a modest budget (say, a few thousand dollars), and
maybe put it onto a PCB with some fast SRAM memory. Presto, a pygmy super-
computer.
Am I completely nuts here? Are there low-cost tools that can do a
synthesis and/or place and route for what even to me sounds like a pretty
ambitious design? What about tutorials on Verilog/VHDL? Finally, are there
IP cores for little processors like an ARM7 or older MIPS that would fit
into a big FPGA? What about processor cores that have a big blob of
programmable logic on-chip and tons of I/O?
Thanks in advance for any help (or talking me out of this),
jasonp
PS: Hi Keith!
Article: 33418Hi, I am using Xilinx WebPACK and trying to add an edif file to a project (written in vhdl). May I? How? Should I be able to? (I mean, Does it make any sense?) Thank you very much in advance, Gonzalo AranaArticle: 33419
Hi,<br>
I would like to download the *.mcs file to a prom (XC18V04) with Parallel Cable III.<br><br>
Questions:<br>
1) What is the circuit for connecting the prom with cable correctly?<br>
2) Can the JTAG programmer download the *.mcs file?<br><br>
Thank you very much,<br>
Harry Chung
Article: 33420Jason Stratos Papadopoulos wrote: > Am I completely nuts here? Are there low-cost tools that can do a > synthesis and/or place and route for what even to me sounds like a pretty > ambitious design? What about tutorials on Verilog/VHDL? Finally, are there > IP cores for little processors like an ARM7 or older MIPS that would fit > into a big FPGA? What about processor cores that have a big blob of > programmable logic on-chip and tons of I/O? You are not completely nuts as long as you let your budget and resources guide your design goals. One detail you didn't ask for is simulation tools. It is a very good idea to do a simulation of the design before loading it on the hardware. It is much easier to debug a simulation than to debug hardware. 1) There are no-cost tools, simulation, synthesis and PAR from Xilinx (and others). http://www.xilinx.com/sxpresso/webpack.htm 2) There are no-cost IP cores for simple processors: a start is Jan Grey's pages: http://www.fpgacpu.org/xsoc/cc.html There is a lot to learn before you will do a good job of designing for an FPGA. Don't let that stop you from getting started. Best of luck. Don'f forget to come back and ask questions, and tell us how your projects are going. -- Phil HaysArticle: 33421
Peter Alfke wrote: > bob elkind wrote: > > > 1. The is and will only be *one* Peter Alfke (had to throw that one in!). > > > > (I was on a 3-week vacation) Thanks for the friendly words, but here are some > corrections: > BTW, there are two more P A's in the pipeline, my son works at Apple R&D and is an > exceptionally good writer, and his son is in kindergarten. So there is hope... > > > Peter Alfke is in one such group at Xilinx, but he has the charter to *span* > > these distinct groups and act as an ombudsman to this newsgroup. > > Xilinx gave Peter such a charter; without it he would have had his > > keyboard-typing fingers chopped off (both of them) for crossing > > marketing/sales/tech support boundaries. > > Not really true: > Xilinx never asked me to monitor this NG, I just started on my own. I was not > issued iron underwear, and I never asked for permission, nor did I have to accept > any censorship ( but I routinely check for technical accuracy). And I have never > EVER been reprimanded, not even by Marketing. > Two reasons: > 1. > Seniority ( 10 years of telecom and computer design in Europe plus 30-odd years of > applications engineering) plus lots of grey hair ;-) > 2. > Xilinx is an enlightened company. No "command-and-obey", nor "shouting-in > your-face", nor "cow-towing to the King", nor other weird management practices > used by some of our competitors. Silicon Valley is really just a village where we > know each other very well. And Xilinx is the best place to work, because good > people are respected and entrusted here. I am living proof. End of commercial. > > > I repeat, these postulations are nothing more or less than my own guesses. > > I'm sure Peter will help clarify or correct these wild guesses > > I just did > > > I may be way off base on this, but I sure had fun writing it! > > Same here. > > Peter Apparently I *was* way off base on my postulations, and thanks, Peter, for the corrections. Based on Peter's characterisations, Xilinx is certainly a rather unique company (certainly the *exception* rather than the *standard* sort of company). Any other FPGA companies out there would do well to take note... Peter has certainly set a standard for others to (hopefully) follow. -- Bob ElkindArticle: 33422
In article <3B5E799B.4C09ED02@IPricot.com>, nicolas.matringe@IPricot.com says... > Klaus Falser a écrit : > > > > Should it not be more correct to use HCT instead of HCs? > > Xilinx in their schematics (038057, from 10 july 1996) > > uses a HC125, but the signals levels on the printer plug > > are TTL. > > HCT work with a power supply between 4.5 & 5.5V, HC work between 2.0 & > 6.0V (and it's recommended no to apply more than Vcc on the inputs) > This is true, but does not matter. If you have a TTL signal as coming out from the computer parallel port you need HCT since the switching levels are different. I'm using only XC9500 and XC9500XLs, so I do not know the specs of the other families very well, but IMO the only correct way is to power the cable from 5V even when programming XL devices (input are 5V tolerant) AND using HCTs. -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 33423
David Wright wrote: > Problem 1: Time and budget - try justifying a CPLD/FPGA design to your > boss. > If you have to do that the first approach should probably be to get a new boss. Failing that for CPLDs you can say: o They're cheap. XC9536XL-7VQ44 = $1.20. o They decouple logic & board design to a large extent. o **No More Wire Mods**. The trick here is to throw in every signal you might possibly need into the first proto. It might mean a bigger device than the final version actually needs but that's a small price to pay. o What's the alternative ? PALs GALs ? 70's era TTL ? 80's era FCT ? 90's era widebus ? The same applies to FPGAs with the addition: o You can do a huge amount more in h/w. o The simulation tools that are an essential part of FPGA design are also incredibly useful for board level sim. > > Problem 2: Real Time and Cost of FPGA design - After your first experience > with FPGA design, where are you going to work next? > There *is* a relatively heavy learning curve esp. if you are simultaneously changing to HDL design. As usual the first one is going to cost a lot of time, effort, sweat, cursing of EDA/FPGA vendors. [and cries for HELP on this NG]. This last one can be minimised by choosing the right tools. I was lucky during my eval that I had some advice from an ASIC person. She said, for the sim tool, don't even bother to look at anything other than ModelSim. > > FPGA/CPLD vendors need to be more up front as to the time, cost and > difficulty of doing a design. Don't pay anyone anything until you know for > sure what you are getting into. > > Although Webpack is touted as free, beware of the following obstacles: > > (1) Free software is of no value without technical support. Xilinx does > tech support (you might have to wait a day for each of your questions). #1 thing you need to do in addition to loading WebPACK is to download some of the (PDF/HTML) manuals from the Xilinx Web site. This is always streets better than using Help files. The Xil manuals are really very good. The basic 2 you will need are the ``Development System Reference Giude'' and the ``Libraries Guide''. > > (2) ModelSim XE Starter is free if you limit your code to 500 lines or less. Don't bother with it. My advice is to just bite the bullet & get the full-fat PE NT version, its only ~$4.5K. Put it on a fast DDR Athlon box and you really won't regret it. > > (3) HDL Bencher is free if you do not exceed 21 I/O lines. They give you a > $500 discount if you go over that limit. You could always use the TestBench > or TextIO (haven't tried this yet). > > (4) How much does it really cost to do a design? > IMO That question needs to be asked in a relative rather than absolute way, comparing it with the costs of other approaches. As I said above - you need to be prepared to put in some "activation energy" on the first one or two designs, after that you'll wonder why you didn't go this way years ago. >Article: 33424
HI,
Jason Stratos Papadopoulos wrote:
> and the chip had eight 16-bit integer multipliers. The PhD students on
> this project got HP to implement it in about 750,000 gates (1995
> technology)
I think, thats today possible in a highend-Virtex-FPGA
> Am I completely nuts here? Are there low-cost tools that can do a
> synthesis and/or place and route for what even to me sounds like a pretty
> ambitious design?
There are low cost or freeware tools, that fit. But I know from
experience, that for designs that size you use better commercial tools
to receive best results.
What will mean, that you develop using lowcost tools until you reach
acceptable results and then search for someone, doing the final work.
> What about tutorials on Verilog/VHDL?
Its easier to learn Verilog or VHDL than to learn designing hardware
using this languages.
So you should start with small designs to learn how to build hardware
using Verilog/VHDL
> Finally, are there
> IP cores for little processors like an ARM7 or older MIPS that would fit
> into a big FPGA?
I can't believe, that there will be ever an suiable ARM-core available,
but there free cpus online. Eg Leon http://www.leoncenter.com which will
fit even in a Virtex-800 FPGA with a pack of surounding logic.
bye Thomas
--
Thomas Stanka
Bosch SatCom GmbH UC_RA/EMD4 s/UC-RA/BC
Gerberstr. 49 Tel. +49 7191 930-1690
Zi. 10/528 Fax. +49 7191 930-21690
Thomas.Stanka@de.bosch.com
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