Messages from 69200

Article: 69200
Subject: Re: turning off clock for parts of design
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 29 Apr 2004 15:38:04 -0700
Links: << >> << T >> << A >>

Tom,
Use a clock enable on your synchronous elements. When you wanna stop them,
turn off the enable. If you really must stop the clock, use a BUFGMUX.
Search the Xilinx website to find out more.
Cheers, Syms.

Article: 69201
Subject: Re: package choice, temperature and obsolesence issues with a xilinx fpga
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 29 Apr 2004 16:59:07 -0700
Links: << >> << T >> << A >>

Austin Lesea <austin@xilinx.com> writes:
> A fgXXX package (fg256) is a
> much lower inductance value package, and with all components on top,
> is not impossible at all to do a power distribution decoupling scheme
> well. You may need two more layers in the pcb stackup to do it right
> (in either case).  If you are having problems with your layout, you
> may send it into the Hotline, and someone will look at it for you, and
> advise you.  My Lab gets invovled in many pcb cases.  I would prefer
> you learn how to do it right and succeed the first time!

Is there an appnote with recommendations and/or examples?  That would
be really useful!

Article: 69202
Subject: Re: basic question, virtex 2 pro
From: ramntn@yahoo.com (ram)
Date: 29 Apr 2004 17:00:54 -0700
Links: << >> << T >> << A >>

HI 
Modelsim XE will not support there is a limitatino on the number of
lines of VHDL code.
you need Modelsim SE /PE
Ram

vananth@gmail.com (Vinod) wrote in message news:<6cd79f5.0404290531.ffccd75@posting.google.com>...
> Hi,
> I am using EDK 3.2 with ISE 5.1.3 on a WinXp machine, and targeting
> the Virtex 2 pro board. Does Modelsim XE allow me to simulate code
> running on the PowerPC along with other external blocks written in
> VHDL as one whole unit?
> I do not have a board yet, and was also wondering  whether such
> simulations would be prohibitively long.
> 
> Links to informative websites would be appreciated
> 
> Thanks
> Vinod

Article: 69203
Subject: Re: package choice, temperature and obsolesence issues with a xilinx fpga
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 29 Apr 2004 17:06:06 -0700
Links: << >> << T >> << A >>

Eric, try XAPP623. Cheers, Syms.
>
> Is there an appnote with recommendations and/or examples?  That would
> be really useful!

Article: 69204
Subject: Re: best machine setup for ISE ??
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 30 Apr 2004 01:53:35 +0000 (UTC)
Links: << >> << T >> << A >>

In article <c6s6k1$hbu$1$8302bc10@news.demon.co.uk>,
Tim <tim@rockylogic.com.nooospam.com> wrote:
>Nicholas C. Weaver wrote:
>> HT P4s are all the 400 MHz DDR bus, which is what you want.
>
>Is that 200MHz?

400 MHz DDR, IIRC.  Data transfer rate is 800 MHz.



-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 69205
Subject: Quartus II Schematic Capture
From: "Gary Pace" <xxx@yyy.com>
Date: Fri, 30 Apr 2004 02:02:58 GMT
Links: << >> << T >> << A >>

Hi,

Does anybody know how to turn off bounding box display in Quartus II
schematic capture (if it's possible at all) ?

Thanks,
Gary.

Article: 69206
Subject: Re: Quartus II Schematic Capture
From: "Subroto Datta" <sdatta@altera.com>
Date: Fri, 30 Apr 2004 02:33:01 GMT
Links: << >> << T >> << A >>

You cannot turn it off. However you can change the colors from the
Tools->Options-.Block & Symbol Editor Colors Page.

- Subroto Datta
Altera Corp.

"Gary Pace" <xxx@yyy.com> wrote in message
news:mtikc.36318$hR1.11686@fe2.texas.rr.com...
> Hi,
>
> Does anybody know how to turn off bounding box display in Quartus II
> schematic capture (if it's possible at all) ?
>
> Thanks,
> Gary.
>
>

Article: 69207
Subject: Is this a best approach- FPGA ANN
From: ramntn@yahoo.com (ram)
Date: 29 Apr 2004 20:08:39 -0700
Links: << >> << T >> << A >>

Objective : To build a neural network - lets say a trained ANN in a
FPGA
Available Resources : Xilinx Virtex-II Pro
                      
Hi all
 I have been trying to build a ANN for quite sometime. I need your
comments and criticism on the methods i followed and will be following

1. I tried to build a single neuron first ( 4 bit input ) , and i used
MAC core and LUT  for implementing activation function( a managable
1024 values in LUT )
Then i continued with building 8 bit neuron, but got stuck at
implementing the LUT ( 2^20 values becoz the output of MAC is 20 bit
number )


2. Lately I came across Xilinx System Generator - A highlevel
modelling tool targetted for DSP application integrated with MATLAB
Simulink.
Its kind of cool so far, I dont have to worry abt entering 2^20 values
into LUT, just initialize ROM with the acitivation functino expression
and implementing MAC is with a multipier and adder blocks.
In fact i made it to the extend of completing the input layer of ANN
with 5 neurons.( keep in mind, its a trained network so i knew the
weights )

3. hmm, hmm System generator is cool , but I have a more cool device
Virtex-II pro with powerpc processor, now i have the choice of
implementing few things in hardware and others in software. But not
sure how hard it would be integrate components with PPC bus.

4. Are there any xilinx cores for a neuron????????!!!

waiting on your comments
Thanks 
Ram

Article: 69208
Subject: Re: EDK 3.2
From: Matthew Ouellette <matt.ouellette@xilinx.comNOSPAM>
Date: Thu, 29 Apr 2004 21:49:53 -0700
Links: << >> << T >> << A >>

Vinod,

EDK 3.2 is compatible with 5.2 SP1 and greater only.  Check the Getting 
Started Guide for more information.

Matt

Vinod wrote:
> Hi,
> I am having problems starting up the Xilinx Platform Studio. I have
> installed EDK 3.2 with service pack 2. When I run it, I get a message
> saying
> 
> "The procedure entry point
> ?GetProjectToolBarID@Dco_PlToolBarManager@@SAIXZ could not be located
> in the dynamic link library libDco_Plugin.dll"
> 
> Im running Windows XP professional with SP1. Also have Xilinx ISE
> 5.1.3i installed. My env variables seem to be pointing to the correct
> location. I've tried reinstalling, but of no avail.
> 
> Any help will be appreciated.
> 
> Vinod

Article: 69209
Subject: Re: Data transfer for real time analysis
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 30 Apr 2004 01:06:39 -0500
Links: << >> << T >> << A >>

>I've found some boards with 32 LVDS channels. The problem is that all the 32
>channels have a common clock. I would like to connect a different sub unit
>to each pin of the 32 channels. How can I distribute the clock to all sub
>units?

What clock are you talking about?

I'm guessing that it's setup for driving 32 parallel signals and
listening to 32 parallel signals.  Are there extra clock signals?

If those are full duplex channels and you only need 12 remote boxes,
then you could do something like send 2 signals to each box, use
one for a clock and the other for data.  Now each box has a clock
synchronized to your central board.  You might want a PLL to clean
it up.

Then you can do the same thing on the return path.  The trick here
is that each clock has been delayed by some unknown time, but it
is running at the exact same frequency as your central clock.  You
need a tiny FIFO to solve that problem.  I think that takes a depth
of 4 and some tricky initialization but I can't recreate the tricks
on the fly.

You could also use a crystal on each remote box and use Manchester
encoding.  If your local clock is 10x or 16x the bit rate, you can build
a small FSM to parse Manchester encoding.  10x 25 megabits is 250 MHz,
or only 125 if you process it 2 bits at a time.  If you have a clean
signal you can probably do it with fewer samples per bit.  (You can
work out the FSM with pencil and graph paper.)  If you have 32
recv channels and only need 12 remote boxes you could use 2 channels
per box and run at half speed.

Note that a signal clock for all 32 channels is OK.  That's the 10x
oversample clock, not the bit rate clock.  You still have to figure
out what to do when the data arrives at slightly different rates and/or
at different times.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

Article: 69210
Subject: Re: Post-Place & Route Simulation with ISE
From: arkagaz@yahoo.com (arkaitz)
Date: 29 Apr 2004 23:27:49 -0700
Links: << >> << T >> << A >>

Hi,

Thanks both for the reply.

That's good to receive other people experiences.

I'll try with both tricks.

Regards,

Arkaitz.

Article: 69211
Subject: Not enough sites to place MULT18X18?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Fri, 30 Apr 2004 14:46:55 +0800
Links: << >> << T >> << A >>

Hi, there:

I am implementing a partial chip for virtex-2-6000. My module has 116
multipliers, the module is allocated an area group with 120 multipliers.
Later I got 9 multipliers not placed, while the PAR
informs there are 13 available sites for placing them...However, the
placement failed...

How may I handle such a situation?
    Replace some smaller * with rtl implementation? How many slices can I
implement an 8X8 muldipler?
    Repartitioning to put some * signs in somebody else's modules? Possible
but troublesome...

Best Regards,
Kelvin






Phase 6.9
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_wkq_calc_mul_inst_
m
   ult_11 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_wkq_calc_mul_inst
_mul
t_11".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_wkq_calc_mul_inst_
mult
_11 will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_q0_b_mul_inst_mu
l
   t_2 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_q0_b_mul_inst_m
ult_
2".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_q0_b_mul_inst_mu
lt_2
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_multipath_top/i_multipath_wk_calc/Mmult__n0009_inst_mu
l
   t_3 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_multipath_top/i_multipath_wk_calc/Mmult__n0009_inst_m
ult_
3".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_multipath_top/i_multipath_wk_calc/Mmult__n0009_inst_mu
lt_3
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_dataii_mul_inst_mu
l
   t_1 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_dataii_mul_inst_m
ult_
1".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_dataii_mul_inst_mu
lt_1
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_i0_a_mul_inst_mu
l
   t_2 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_i0_a_mul_inst_m
ult_
2".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_i0_a_mul_inst_mu
lt_2
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_multipath_top/i_multipath_wk_calc/Mmult__n0010_inst_mu
l
   t_3 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_multipath_top/i_multipath_wk_calc/Mmult__n0010_inst_m
ult_
3".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_multipath_top/i_multipath_wk_calc/Mmult__n0010_inst_mu
lt_3
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_dataqq_mul_inst_mu
l
   t_1 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_dataqq_mul_inst_m
ult_
1".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_dataqq_mul_inst_mu
lt_1
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_wki_calc_mul_inst_
m
   ult_11 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_wki_calc_mul_inst
_mul
t_11".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_wk_calc/Mmult_wki_calc_mul_inst_
mult
_11 will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
WARNING:Place:119 - Unable to find location.  MULT component

i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_i0_b_mul_inst_mu
l
   t_2 not placed.
   MULT18X18
"i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_i0_b_mul_inst_m
ult_
2".
      COMPGRP "RX.MULT18X18" LOCATE = SITE "MULT18X18_X1Y23:MULT18X18_X5Y0"
LEVEL 4 ;
Only the one associated with MULT18X18
i_ofdm_rx/i_wrx_top/i_channel_top/i_channel_calc/Mmult_data_i0_b_mul_inst_mu
lt_2
will be looked at.
The AREA group contains 120 possible sites for this component.   13 of these
sites were available to place this component into.
===============================================================
List of 13 available sites in area are:
   Site MULT18X18_X1Y3
   Site MULT18X18_X1Y5
   Site MULT18X18_X1Y12
   Site MULT18X18_X1Y15
   Site MULT18X18_X1Y19
   Site MULT18X18_X2Y4
   Site MULT18X18_X2Y6
   Site MULT18X18_X2Y8
   Site MULT18X18_X2Y12
   Site MULT18X18_X2Y16
   Site MULT18X18_X2Y19
   Site MULT18X18_X2Y20
   Site MULT18X18_X2Y22
===============================================================
List of comps in area without same LOC are:
===============================================================
ERROR:Place:120 - There were not enough sites to place all selected
components
Phase 6.9 (Checksum:39386fa) REAL time: 27 mins 46 secs

Total REAL time to Placer completion: 27 mins 47 secs

Article: 69212
Subject: Ethernet & FPGA
From: Stefan Kopetsch <bibelwerfer@web.de>
Date: Fri, 30 Apr 2004 09:27:23 +0200
Links: << >> << T >> << A >>

Hi...

i'll write my bachelor thesis about the implementation of ethernet and 
possible tcp/ip layers in an fpga. does someone have experience doing 
it? especially using open source ip cores like the ethernet MAC core 
from opencores.org? would be nice if someone could share their 
experience. another point is the implementation of tcp/ip. does it make 
sense to do it all in hardware or is it simpler to run a processor core 
on the fpga and then implement the tcp/ip layers using a highlevel 
language like C? i gotta stress that the aim is initially to build an 
runnable ethernet core and then implement the data transfer step by step

TIA

Stefan

Article: 69213
Subject: Can assign same area group to multiple modules?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Fri, 30 Apr 2004 15:56:31 +0800
Links: << >> << T >> << A >>

May I assign same area_group to multiple modules? e.g.

INST "fft_top"   AREA_GROUP = "TX";
INST "wtx_top"   AREA_GROUP = "TX";

Kelvin

Article: 69214
Subject: Re: Ethernet & FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 30 Apr 2004 03:05:22 -0500
Links: << >> << T >> << A >>


>i'll write my bachelor thesis about the implementation of ethernet and 
>possible tcp/ip layers in an fpga. does someone have experience doing 
>it? especially using open source ip cores like the ethernet MAC core 
>from opencores.org? would be nice if someone could share their 
>experience. another point is the implementation of tcp/ip. does it make 
>sense to do it all in hardware or is it simpler to run a processor core 
>on the fpga and then implement the tcp/ip layers using a highlevel 
>language like C? i gotta stress that the aim is initially to build an 
>runnable ethernet core and then implement the data transfer step by step

You can do very simple protocols without much software, but it's
still simpler to think of it as software.

Consider something like a data recording setup.  You send it a UDP packet
and it returns the answer.  You don't need a routing layer since you
send it back where it came from - just swap a few header fields.
(But watch out for the broadcase case.)

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

Article: 69215
Subject: Re: Can assign same area group to multiple modules?
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 30 Apr 2004 18:09:17 +1000
Links: << >> << T >> << A >>

On Fri, 30 Apr 2004 15:56:31 +0800, "Kelvin @ SG"
<kelvin8157@hotmail.com> wrote:

>May I assign same area_group to multiple modules? e.g.
>
>INST "fft_top"   AREA_GROUP = "TX";
>INST "wtx_top"   AREA_GROUP = "TX";
>
>Kelvin

Yes.

Allan.

Article: 69216
Subject: Xilinx ISE 6.2 on Debian
From: "Gerrit VdV" <gvd@denayer.wenk.be>
Date: Fri, 30 Apr 2004 01:09:33 -0700
Links: << >> << T >> << A >>

Has anyone succesfully installed the ISE software on a Debian 3.0 system ? 
I receive errors like: 
Wind/U Error (294): Unable to install Wind/U ini file (/cdrom/data/WindU). 
See the Wind/U manual for more details on the ".WindU" file and the "WINDU" 
environment variable. 
Wind/U X-toolkit Error: wuDisplay: Can't open display 

Any help will be appreciated ! 
Regards, 
Gerrit VdV

Article: 69217
Subject: Re: Not enough sites to place MULT18X18?
From: "Ken Morrow" <junk@not_morro.co.uk>
Date: Fri, 30 Apr 2004 13:26:08 +0100
Links: << >> << T >> << A >>

Kelvin,

You will probably find that some of the multiplier sites are blocked from
being used due to
some block RAMs having widths of > 18 bits. If so, try to change some of the
RAMs to
have smaller widths.

I have a design which now uses all 144 of the V2-6000 multipliers, and most
of the RAMs
without prob. I had to reduce the width of all of the RAMs to 18 bits or
less for the multipliers
to be available for use.

(I was impressed that Mentor Precision automatically used multipliers built
with LUTs, once it had
used up all the available multipiers).

Good Luck,

Ken,
Morrow Electronics Limited, UK
Currently specialising in FPGA design for 3G.
www.morro.co.uk

Article: 69218
Subject: Re: package choice, temperature and obsolesence issues with a xilinx
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 30 Apr 2004 07:48:37 -0700
Links: << >> << T >> << A >>

Eric,

The SI webpage on support.xilinx.com lists all of the collateral 
material that we can provide (and there is a lot).  There are a couple 
of app notes that cover this topic.

Austin

Eric Smith wrote:
> Austin Lesea <austin@xilinx.com> writes:
> 
>>A fgXXX package (fg256) is a
>>much lower inductance value package, and with all components on top,
>>is not impossible at all to do a power distribution decoupling scheme
>>well. You may need two more layers in the pcb stackup to do it right
>>(in either case).  If you are having problems with your layout, you
>>may send it into the Hotline, and someone will look at it for you, and
>>advise you.  My Lab gets invovled in many pcb cases.  I would prefer
>>you learn how to do it right and succeed the first time!
> 
> 
> Is there an appnote with recommendations and/or examples?  That would
> be really useful!

Article: 69219
Subject: Re: Xilinx ISE 6.2 on Debian
From: fmadlener@gmx.de (Felix Madlener)
Date: Fri, 30 Apr 2004 15:04:15 +0000 (UTC)
Links: << >> << T >> << A >>

Gerrit VdV <gvd@denayer.wenk.be> wrote:
> Has anyone succesfully installed the ISE software on a Debian 3.0 system ?

Wind/U tries to open a display using TCP ports. However Debian
disables TCP connections to your Xserver by default. Search for an
entry like ":0 local /usr/X11R6/bin/X vt7 -dpi 100 -nolisten tcp" in
/etc/X11/kdm/Xserver or whereever you start X and remove "-nolisten
tcp". After the installation you can disbable tcp connections again.

Regards
Felix

-- 
"Let's face it.  The FPGA companies are really software 
companies that happen to have very expensive dongles"

Ray Andraka in comp.arch.fpga

Article: 69220
Subject: Re: Fast Carry Chains in Xilinx SpartanII FPGA's
From: abeaujean@gillam-fei.be (A Beaujean)
Date: 30 Apr 2004 08:19:28 -0700
Links: << >> << T >> << A >>

"John_H" <johnhandwork@mail.com> wrote in message news:<yzEcc.7$mx3.84@news-west.eli.net>...
> Another thought:  If you're instantiating the MUXCY primitives, you may need
> to add an XORCY between the MUXCY and the register.  Take a look at the
> slice configuration - the Virtex functional data sheet illustration is more
> detailed than that found in the Spartan-II's - and you'll see that the MUXCY
> output from one "stage" of your carry chain feeds the XORCY of the register
> one half slice above.
> 
> Also, rather than instantiating 12 MUXCY and XORCY primitives, try using the
> 13-bit result from 13'h1fff+In where you may need to add some directives to
> keep a smart synthesizer from reducing your equation to an equivalent 1-bit
> result.  Use the top 12 of the 13 bits for your "deterministic" delay and
> you're there.  It may be cleaner and easier to implement in the end.
> 
> 
> "A Beaujean" <abeaujean@gillam-fei.be> wrote in message
> news:8211d046.0404060730.5e01e294@posting.google.com...
> > I want to be able to use the fastest possible paths within a SpartanII
> >  FPGA to create internal signals which are simple copies of each other
> > linked in a chain. Delay between each should be in the order of a few
> > tens to hundreds of picoseconds.
> > All of the created signals should however be usable by other internal
> > logic (in fact on D inputs of a chain of flip-flops clocked all the
> > same)
> > My first idea was to define a chain of BUF "components", and see what
> > happens.
> > As feared, the (Foundation) development tool just merged all the
> > signals (No BUF generated).
> > Forcing a KEEP attribute on all the signals just did not help.
> > I tried with LUT1's. This works but is much too slow for the
> > application.
> > Looking at the FPGA Editor gave me the idea of using the MUXCY,
> > MUXCY_L or MUXCY_D components of the SpartanII library. Some sort of a
> > miracle happened then: the dedicated carry chain was selected, running
> >  thru the expected number of CLB's, and speed was excellent. But to my
> > great surprise, only one flip-flop out of two hooked onto the outputs
> > of the MUXCY components was selected as being part of the same cell.
> > The second FF was placed in a totally different CLB. This is not
> > exactly  what I expected, since the application requires a very close
> > matching of delays.
> > Any idea why this happens ?  Possible corrections ? Thank you
> > beforehand.


OK: I had a bit more time working again on this idea.
Your idea to define the result of say "111111" + ("00000"&Input) and
register it is the most staightforward choice. Works fine.
All FF's are now perfectly facing the corresponding carry logic. Time
is now pratically deterministic.

Thanks.

Article: 69221
Subject: programming the mach231
From: nate <nathan_wilson@tepidmail.com>
Date: 30 Apr 2004 10:45:21 -0500
Links: << >> << T >> << A >>

I have a bunch of free mach231 chips but I can't find any information about 
how to program them. I have gathered from the web that they are not JTAG. 
The datasheet does not explain how to program the chip. I am planning on 
constructing a programmer but there is not a lot of information about how 
to do this. The closest thing I have found is some information and 
schematics showing how to build the expro-60. Any ideas or information 
would be appreciated. 

Nathan

change tepid to hot to reach me by e-mail

Article: 69222
Subject: Re: transport applications
From: nnadal@terra.es (Narc?s Nadal)
Date: 30 Apr 2004 09:14:21 -0700
Links: << >> << T >> << A >>

"paris" <273986malaka@email.it> wrote in message news:<c6kb9a$1te6$1@avanie.enst.fr>...
> "Narcis Nadal" <nnadal@terra.es> escribió en el mensaje
> news:unLic.4700406$uj6.16108118@telenews.teleline.es...
> > Yes, we have recently designed and produced here in Catalonia some 192x64
> > LED displays with 16 gray levels EN 50155 compliant for the TGV
> > Barcelona-Madrid. Those displays have a Xilinx XCS05 industrial grade as a
> > coprocessor.
> >
> 
> did you mean "intensity" levels?
> 

Yes, in the first step each bitmap is changed in format for easy
serialisation 1 bmp at a time, and the second step is showing it as
bmp 0 lasting 1T, bmp 1 lasting 2T, and so on showing the entire
gray-scale graphic in 1/64 sec and an animation at 64 frames/sec. The
CPU works just a little and I put a H3003 at only 16MHz because I
thought hard work for passing EMC but it was funny.

> wasnt TGV a French train?
> i thought in Spain you had AVE or something
> 

Yes, the official name is AVE but in Catalonia (we speech catalan) the
acronim TGV sounds better :-)

Regards

Narcis Nadal

> 
> 
> > Regards
> >
> > Narcis Nadal
> > "Jacek Mocki" <jacekmocki@poczta.onet.pl> escribió en el mensaje
> > news:c6anq7$7r$1@news.onet.pl...
> > Does anyone know some examples of using CPLD or FPGA devices in railways
> > equipment?
> >
> > Regards
> >
> > Jacek
> >
> >

Article: 69223
Subject: Re: transport applications
From: nnadal@terra.es (Narc?s Nadal)
Date: 30 Apr 2004 10:36:37 -0700
Links: << >> << T >> << A >>

"Jacek Mocki" <jacekmocki@poczta.onet.pl> wrote in message news:<c6o7st$23l$1@news.onet.pl>...
> Narcis,
> 
> I hope to use FPGA or CPLD to control of train movement (signalling).
> 
> I prepared some state machines for a small station and it seems to be
> working. Just think about a conception of the adaptation my solution to a
> real line in Poland.
> I would like to implement signalling functions to probably CPLD but there
> still will be required a software in control center. There are 18 small
> stations. There are 6 people on each station. Using automatic equipment some
> people can be moved to other jobs. It is very useful for national railway
> companies from East Europe block to improve single lines.
> 
> Regards
> 
> Jacek Mocki
> 

I work in advertising and I just took contact with one project in
signaling, it was a semaphoric control and I'm sure there are out
there a lot of people with more experience than me but I want advise
you: in logic don't forget the forbidden states, take some robust
external logic (PLD or glue) for supervising the outputs (final
lights) and another one for the entire system (WD is a complement but
it don't suffit). Another thing very useful is testing the system
remotelly changing the inputs in test mode looking for Murphy's
combinations, and when you had a system entirelly verifiable, take
another one with his own power supply as a backup.
In an European railway network you must be EN 50155 and EN 50121
compliant, it means your equippement will be tested in isolation, EMC,
surges, fast transients, overvoltages, voltage variations, temperature
and usually in vibrations. I have done that in 3 projects (7
equipements) ranging from 3 to 9 months each one. Ah! don't begin the
production before you had passed all the tests in a prototype, is
usual to put the last minute's capacitor or ferrite.

Regards.

Narcis Nadal

Article: 69224
Subject: SpyGlass Software
From: ijazag@yahoo.com (Ijaz Ahmad)
Date: 30 Apr 2004 10:47:16 -0700
Links: << >> << T >> << A >>

HellO!
 
 Can anyone send me Evaluation version of SpyGlass Software.

 Thank you

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