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Thank you, Steen Qijun. "Steen Larsen" <steen@tech-forge.com> wrote in message news:3e8d96d6.0210091036.4f9c6c25@posting.google.com... > Xu Qijun, your question seems pretty broad and may not be applicable > to comp.arch.fpga. MP3 decoding (as far as I understand) is pretty > complex, and you would be hard put to compete in the high volume > end-consumer market where there exist low cost MP3 decoder ASICs. > Take a look at www.pjrc.com for a public domain design of a hard drive > based MP3 player. I think Paul shares the Xilinx code that interfaces > between hard drive, SIMM buffer, 8051 controller, and MP3 decoder. > > Regards, > -Steen > "Karl" <Far@East.Design> wrote in message news:<3da385c5@news.starhub.net.sg>... > > Hi, > > > > I have come across a low-end portable MP3 player, which uses a parallel > > cable to load > > songs into the SmartMedia cards and the player's internal memory. Can > > anybody tell what > > are the steps involved in designing this MP3 player? What core expertise do > > I need to > > design this toy? > > > > -- > > Xu QijunArticle: 48026
www.fpgaarcade.com update. Now include Space Invaders & Galaxian piccy links Cheers, MikeJArticle: 48027
On a serious note at a professional (!) designer. I used maxplus2 extensively in the past, but was forced to move onto devices Xilinx when they introduced the 4000xl chips as I really needed to use the distributed rams. (However, since Virtex have never look back) This forced a move from AHDL to VHDL, and lots of pain. I had to move from the nice 'cosy' gui to a set of tools that were not so polished. However, whereas simulating a single chip was a pain in maxplus, I now simulate whole cards, indeed systems. I can take data, for example a picture, run it through the simulator using complex test benches and produce a real output (perhaps another image). My point is that I spend most of my time in simulation. When I come to build a chip I run (under win2k) a batch file that runs the sythesis tool, then the xilinx place and route tools. I am not really interested in the xilinx sw - they produce me a bit file for the device, a timing report file telling me how much extra time I have to spend over the weekend meeting constraints, and perhaps a list of errors. The point is I type 'build_chip' (perhaps on a seperate machine) and carry on with the simulation / coding. Xilinx tools are not interesting, they don't need to be. Many designers never even run up the gui. The simulator is where the action is. Cheers, MikeJ b.t.w. never, ever, ever phone xilinx tech support. just my gripe for the day.Article: 48028
Have you seen this problem with Gnome or KDE that ships with Red Hat 7.1? Another possibility would be is to set the following environment variable MWWM with a value allwm to see if it makes a difference. - DS "Petter Gustad" <newsmailcomp3@gustad.com> wrote in message news:m3elazvra1.fsf@scimul.dolphinics.no... > kevinbraceusenet@hotmail.com (Kevin Brace) writes: > One big plus: Quartus II runs under Linux in native mode! > > > The Quartus II Linux edition GUI behaves rather odd (at least under > fvwm2). It will always stay on top of all other windows. There is no > way to raise other windows like xterms on top of Quartus. Even when > minimized it punches through all other windows on the desktop. Have > anybody else experienced this behavior? > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48029
Petter Gustad wrote: > > Russell <rjshaw@iprimus.com.au> writes: > > > Look for something like a ~/.quartus2rc or > > /usr/X11R6/lib/X11/app-defaults/quartus2 file. > > There is no such thing... Haven't used it, so i guessed.Article: 48030
MikeJ wrote: > > On a serious note at a professional (!) designer. > > I used maxplus2 extensively in the past, but was forced to move onto devices > Xilinx when they introduced the 4000xl chips as I really needed to use the > distributed rams. > (However, since Virtex have never look back) > > This forced a move from AHDL to VHDL, and lots of pain. > I had to move from the nice 'cosy' gui to a set of tools that were not so > polished. > > However, whereas simulating a single chip was a pain in maxplus, I now > simulate whole cards, indeed systems. > I can take data, for example a picture, run it through the simulator using > complex test benches and produce a real output (perhaps another image). > > My point is that I spend most of my time in simulation. When I come to build > a chip I run (under win2k) a batch file that runs the sythesis tool, then > the xilinx place and route tools. I am not really interested in the xilinx > sw - they produce me a bit file for the device, a timing report file telling > me how much extra time I have to spend over the weekend meeting constraints, > and perhaps a list of errors. The point is I type 'build_chip' (perhaps on a > seperate machine) and carry on with the simulation / coding. > > Xilinx tools are not interesting, they don't need to be. Many designers > never even run up the gui. The simulator is where the action is. How do you floor-plan without a gui?Article: 48031
Does anyone know if Intel intends to make XScale family cores available as "IP" that can be embedded in an ASIC (and/or FPGA) designs for the System-on-chip (SOC) market? Warren PostmaArticle: 48032
Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How
do you floorplan with the broken floorplanner GUI in 4.2i?
Russell wrote:
>
> How do you floor-plan without a gui?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48033
In this age of multigigabit networks TCP/IP processing with
software will cause perfomance degradation .What are the possiblities of an
TCP/IP hardware which will do all the TCP/IP processing and store the
packets in a buffer so that the application can use it.Is any similar system
is available
"Nicholas C. Weaver"
<nweaver@ribbit.CS.Berkeley.EDU> wrote in message
news:ann7uo$1oa9$1@agate.berkeley.edu...
> In article <3D9F21D0.12AAC8B@attbi.com>,
> Phil Hays <SpamPostmaster@attbi.com> wrote:
>
> >> Well, it's interesting if you can jam all the TCP logic in a sub
> >> 1000 k gates , do all the checksumming in one clock cycle, match
> >> IP's in a CAM, etc...
>
> >The key phrase is "wire speed".
>
> However, until you are doing 1Gb+ packet processing, EL Cheapo
> Embedded PC (EG, the Via EPIA system, very cute) has enough horespower
> to keep up with TCP and have a fair amount left over.
>
> Gb+ is another kettle of fish. I WANT, WANT, WANT, a PCI card with a
> V2Pro and quad Gb ethernet.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
Article: 48034Whatta pain that their website has no email address for feedback/suggestions/questions. Prick of misery. Unless you know the xscale manager there personally, you probably shouldn't hold your breath for an answer. "Warren Postma" <warren.postma@sympatico.ca> wrote in message news:qH5p9.18129$ZO1.898354@news20.bellglobal.com... > Does anyone know if Intel intends to make XScale family cores available as > "IP" that can be embedded in an ASIC (and/or FPGA) designs for the > System-on-chip (SOC) market? > > Warren Postma > >Article: 48035
I gave up on doing any fpga design after wasting weeks on discovering how broken floor planning with RPMs in 4.2i was, and there's no way i can do without manual floorplanning. Altera had even less options and the devices had no SRL16 equivalent. If 5.1i is no good, i'll start investigating the cyclone devices. It would be good having a tool that runs on linux too (wonder if i still need that leonardo with the crappy gui bugs?). I was hoping 5.1i would fix everything, but i haven't tried it yet. Ray Andraka wrote: > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > do you floorplan with the broken floorplanner GUI in 4.2i? > > Russell wrote: > > > > > How do you floor-plan without a gui?Article: 48036
Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my
previous post. I haven't tried the floorplanner in 5.1 yet.
4.2i's floorplanner has a workaround if your design will go through PAR without a
floorplan, you can then go into the floorplanner do a constrain from placement on your
RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it
does no good if your design won't make it through PAR without a floorplan, and it
doesn't leave much room to move things around if youve got a dense device.
I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of
floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds
me too much of the days before the introduction of the floorplanner in XACT.
Russell wrote:
> I gave up on doing any fpga design after wasting weeks on discovering
> how broken floor planning with RPMs in 4.2i was, and there's no way i
> can do without manual floorplanning. Altera had even less options and
> the devices had no SRL16 equivalent. If 5.1i is no good, i'll start
> investigating the cyclone devices. It would be good having a tool
> that runs on linux too (wonder if i still need that leonardo with
> the crappy gui bugs?). I was hoping 5.1i would fix everything, but
> i haven't tried it yet.
>
> Ray Andraka wrote:
> >
> > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How
> > do you floorplan with the broken floorplanner GUI in 4.2i?
> >
> > Russell wrote:
> >
> > >
> > > How do you floor-plan without a gui?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48037
Some qualification to my rants here:
The Xilinx silicon is still good stuff, very capable. I have some beefs with the software
and its spiralling quality. The fact of the matter though is that many users will not
encounter the problems I have with the software, simply because we typically are pushing
the corners of the tools where most users never stray. For example, if you are not
floorplanning, you won't hit about 90% of the show stopper bugs we've run into. My
frustration is that for these designs where we are pushing the limits, the tools have
steadily lost capability from version to version, to the point the 4.2 has enough problems
that it is leaving us very little options for work arounds on a couple of designs.
Ray Andraka wrote:
> Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my
> previous post. I haven't tried the floorplanner in 5.1 yet.
>
> 4.2i's floorplanner has a workaround if your design will go through PAR without a
> floorplan, you can then go into the floorplanner do a constrain from placement on your
> RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it
> does no good if your design won't make it through PAR without a floorplan, and it
> doesn't leave much room to move things around if youve got a dense device.
>
> I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of
> floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds
> me too much of the days before the introduction of the floorplanner in XACT.
>
> Russell wrote:
>
> > I gave up on doing any fpga design after wasting weeks on discovering
> > how broken floor planning with RPMs in 4.2i was, and there's no way i
> > can do without manual floorplanning. Altera had even less options and
> > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start
> > investigating the cyclone devices. It would be good having a tool
> > that runs on linux too (wonder if i still need that leonardo with
> > the crappy gui bugs?). I was hoping 5.1i would fix everything, but
> > i haven't tried it yet.
> >
> > Ray Andraka wrote:
> > >
> > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How
> > > do you floorplan with the broken floorplanner GUI in 4.2i?
> > >
> > > Russell wrote:
> > >
> > > >
> > > > How do you floor-plan without a gui?
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48038My designs just use cascades of fairly repetitive filter and delay blocks which is well suited to macro methods, and they're controlled with some state-machine random logic. It should fit in the larger spartan devices. I heard that 4.2i fpga editor had bugs where vcc-gnd shorts happened. Is the 5.1i fpga editor much better? Are hard macros relatively bug-free to generate and use in 5.1i? Ray Andraka wrote: > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > previous post. I haven't tried the floorplanner in 5.1 yet. > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > floorplan, you can then go into the floorplanner do a constrain from placement on your > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > does no good if your design won't make it through PAR without a floorplan, and it > doesn't leave much room to move things around if youve got a dense device. > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > me too much of the days before the introduction of the floorplanner in XACT. > > Russell wrote: > > > I gave up on doing any fpga design after wasting weeks on discovering > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > can do without manual floorplanning. Altera had even less options and > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > investigating the cyclone devices. It would be good having a tool > > that runs on linux too (wonder if i still need that leonardo with > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > i haven't tried it yet. > > > > Ray Andraka wrote: > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > Russell wrote: > > > > > > > > > > > How do you floor-plan without a gui?Article: 48039
I think the fpga world would benefit greatly if the fpga vendors would just write an api library for each device to control all the low level logic primitives, and let open-source on linux take care of building state of the art routing and layout tools and decent hdl languages and compilers. It would improve the industry no end. How excellent would it be to be able to locate and fix a router bug your self, or get it fixed in less than a week? Ray Andraka wrote: > > Some qualification to my rants here: > > The Xilinx silicon is still good stuff, very capable. I have some beefs with the software > and its spiralling quality. The fact of the matter though is that many users will not > encounter the problems I have with the software, simply because we typically are pushing > the corners of the tools where most users never stray. For example, if you are not > floorplanning, you won't hit about 90% of the show stopper bugs we've run into. My > frustration is that for these designs where we are pushing the limits, the tools have > steadily lost capability from version to version, to the point the 4.2 has enough problems > that it is leaving us very little options for work arounds on a couple of designs. > > Ray Andraka wrote: > > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > > previous post. I haven't tried the floorplanner in 5.1 yet...Article: 48040
In article <qH5p9.18129$ZO1.898354@news20.bellglobal.com>, Warren Postma <warren.postma@sympatico.ca> wrote: >Does anyone know if Intel intends to make XScale family cores available as >"IP" that can be embedded in an ASIC (and/or FPGA) designs for the >System-on-chip (SOC) market? I doubt they would do X-scale as an FPGA, simply because all its strenghts really come from the implementation as custom logic (after all, it is really StrongARM v 1.1). Similarly, Intel has never been much of an IP vendor, and I bet the design is fairly fab specific... There are, however, plenty of other Arm designs out there. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48041
Petter Gustad wrote: > > Russell <rjshaw@iprimus.com.au> writes: > > > Look for something like a ~/.quartus2rc or > > /usr/X11R6/lib/X11/app-defaults/quartus2 file. > > There is no such thing. Quartus installs itself in a separate > directory tree and does not install anything under X11 or in your home > directory. > > Everything related to the Quartus windows layer appears to be located > in the directory called mw. Quartus does not seem to behave like a > typical X11 application in this sense. There's also a: /etc/X11/app-defaults/ area on debian.Article: 48042
Russell <rjshaw@iprimus.com.au> writes: > Petter Gustad wrote: > > > > Russell <rjshaw@iprimus.com.au> writes: > > > > > Look for something like a ~/.quartus2rc or > > > /usr/X11R6/lib/X11/app-defaults/quartus2 file. > > > > There is no such thing... > > Haven't used it, so i guessed. I see. Thank you for trying to help anyway. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48043
Russell wrote: > > I think the fpga world would benefit greatly if the fpga vendors > would just write an api library for each device to control all > the low level logic primitives, and let open-source on linux > take care of building state of the art routing and layout tools > and decent hdl languages and compilers. It would improve the > industry no end. How excellent would it be to be able to locate > and fix a router bug your self, or get it fixed in less than > a week? That may sound great in theory, but the software is vitally important to an FPGA vendor. An FPGA vendor can't depend on outside factors to control their destiny. An FPGA company can literally be made or broken on the tools. So you will never see them abandon their in house tools for open source tools. In fact, because the user community is so small, they can't afford to develop the tools without the finance support of the user base. If even just 50% of them go to open source tools the FPGA vendor will lose tons of money. They can't raise the price of the silcon to make up for it since the price of silicon is set by competitive pressures. It would be a very tough sell to show that it would provide a superior market position to have open source tools. Of course when I say they "can't afford" to self fund the tools, that is a relative term. The point is that the tools cost a lot of money to maintain and update. The economics are not there to allow open source tools to compete. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 48044
That Babelfish translation is heinous. Kind of humorous though. "MikeJ" <pacman@fpgaarcade.com> wrote in message news:1034206876.91304.0@dyke.uk.clara.net... > www.fpgaarcade.com update. > > Now include Space Invaders & Galaxian piccy links > > Cheers, > MikeJ > >Article: 48045
Ray Andraka wrote: > > Some qualification to my rants here: > > The Xilinx silicon is still good stuff, very capable. I have some beefs with the software > and its spiralling quality. The fact of the matter though is that many users will not > encounter the problems I have with the software, simply because we typically are pushing > the corners of the tools where most users never stray. For example, if you are not > floorplanning, you won't hit about 90% of the show stopper bugs we've run into. My > frustration is that for these designs where we are pushing the limits, the tools have > steadily lost capability from version to version, to the point the 4.2 has enough problems > that it is leaving us very little options for work arounds on a couple of designs. I think more users may be affected than you realise. The cynical amongst us could say they have a vested interest in NOT fixing the software, if the effect is to simply bump users up a FPGA size. We routinely push CPLD right to the corners, and the critical metric for tools here, is quality of reports, esp the fitters. ( and the ability to control / floor plan ) Tools where you cannot guide, nor analyse the results, are not tools at all. -jgArticle: 48046
Russell <rjshaw@iprimus.com.au> writes: > Petter Gustad wrote: > > > > Russell <rjshaw@iprimus.com.au> writes: > > > > > Look for something like a ~/.quartus2rc or > > > /usr/X11R6/lib/X11/app-defaults/quartus2 file. > > > > There is no such thing. Quartus installs itself in a separate > > directory tree and does not install anything under X11 or in your home > > directory. > > > > Everything related to the Quartus windows layer appears to be located > > in the directory called mw. Quartus does not seem to behave like a > > typical X11 application in this sense. > > There's also a: > /etc/X11/app-defaults/ area on debian. Your guesses are good and would be very reasonable if Quartus was a typical X11 application. However, Quartus is more of a Windows application in this sense... Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48047
"ds" <nospam@cwix.com> writes: > Have you seen this problem with Gnome or KDE that ships with Red Hat 7.1? I haven't tried yet. I have quite a bit of context stored on my desktop (the downside of using an OS which never crashes) so I don't want to restart my window manager at the moment. I'll try later. > Another possibility would be is to set the following environment variable > > MWWM with a value allwm > > to see if it makes a difference. Unfortunately it didn't: scimul:jtag $echo $MWWM allwm scimul:jtag $/net/sciraid2/raid2/home/local-linux-x86/bin/quartus& The behavior was the same. I'll check some other window managers later. I would assume that the one that Altera used for Qualification will behave better. I like fvwm2 because it's fast and easy to configure to select windows using the keyboard only. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48048
"Warren Postma" <warren.postma@sympatico.ca> writes: > Does anyone know if Intel intends to make XScale family cores available as > "IP" that can be embedded in an ASIC (and/or FPGA) designs for the > System-on-chip (SOC) market? I don't know, but I would guess no. However, you can get the ARM core used¹ in the XScale from ARM (www.arm.com). Altera provides an FPGA with an embedded ARM core, namely the Excalibur. Petter ¹) Intel has put a lot of supporting devices around the core and enhanced the architecture, but the ISA is the same. -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48049
Atmel has some microcontroller chip with both USB and JTAG Masters in H/W. Some of the controllers have decent size flash memories as well (8 Mbit). I think these ships could be really useful for programming FPGAs. Unfortunately there is no interest for prototyping adapters, only for them to be used in production. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden. "Jens Niemann" <Jensniemann@gmx.de> skrev i meddelandet news:anus53$hkp3q$1@ID-92522.news.dfncis.de... > Hello, > is there somewhere a reference design or some information about booting a > SRAM-based FPGA via a USB interface? > I am thinking to use one of Cypress's USB interfaces to programm a Spartan > 2 via JTAG. This would be a very convenient solution for further programm > updates. > Any suggestions ? > > Regards, > Jens Niemann > >
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