Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thomas Pollischansky <polly@rz.fh-augsburg.de> wrote: > Has anyone got experiance in using Nios 1.1 together with Quartus II > 2.11. I never used it in this combination, but I never had your problems. (I used NIOS1.1 with Quartus 1.1, then upgraded to NIOS 2.0, and recently I upgraded to Quartus 2.1) > My Nios processor designs are not completely compiled. Half of the > NIOS processor is missing on the FPGA (no internal memory..). > Has anyone had problems like that or know what might be the reason > (forgotten Options in Quartus...)? Thanks for any answers! There are no options in Quartus, which I would be aware about. I suppose there are no relevant compiler messages/ errors regarding this problem. Which device are you using? How can you be sure that is there actually is no internal memory? ( and not just e.g. on the wrong address) RomanArticle: 49276
> DesignManager has disappear but 'Project Navigator' is useful too. (I > don't know how to answer to your question). Which reminds me: here's a request which reflects a very-long-standing, trivial, yet significant usability problem in both DM (RIP) and PN. To illustrate the problem: 1. make any trivial design 2. right-click Implement Design >> Rerun All. The various FPGA implementation tools run, and their output scrolls through the Console tab in the Transcript window. Say you need to check something (e.g.the Design Summary) while the tools are running. The problem is the Thumb (vertical scrollbar control) seems subordinate to the window scrolling logic such that EVEN IF the mouse is held down on the thumb (so as to review some earlier bit of the Console output), each time a new line of output is written to the Console, the Console output jumps down to the bottom of the log. Then to return to the earlier log output, you must then "jiggle" the mouse. In effect, you "fight" with the thumb to try in vain to read the output you wish to see in the midst of all this jumping back to the last line of the log. It would suffice that that repositioning the Console window does not occur while the thumb is held down. (Still this is not a trivial problem because the thumb logic needs to move and resize the thumb to reflect the growing Console window output buffer, even when the thumb is held such that the current contents of the window do not move. Even the simple expedient of freezing the output buffer while the thumb is held would be better than the current regime.) ..... Perhaps this kind of too trivial to report, yet annoying little problem that never gets fixed (and that moves forward even as earlier tools like DM retire) reveals to what extent ones' tools builders "eat their own dogfood" (<< not a pejorative). I encourage all tools developers of every bent, and their management, to make sure you take some time every year to work on a "real project" (several days' long, not a 10 minute quickie) using your own tools. This does wonders for rounding-off-the-rough-corners-of-usability. (Usability Labs studies are essential, but in my experience eating your own dogfood is more immediate and motivating.) ..... Here's another one in this series of too-trivial-to-report annoyances. After you've been "in flow" (Csikszentmihalyi) for a while, running PARs and floorplanners and timing analyzers and such, and you have lots of apps and lots of MDI windows open, many timing analyses, etc., and you want to close each of these apps, you would like to quickly ALT-TAB around the windows and ALT+F4 to close each one down. But no, first you have to dismiss a sea of "Save Changes?" dialogs. I often wish there were some sticky preference or "don't ask me again" or some heuristic (if the timing analysis took less than 10 seconds or was a default kind of timing analysis there is no need to prompt to save it) to preclude this. Respectful of the "can't please everybody" nature of tools development, Jan Gray, Gray Research LLC -- once and future tools developerArticle: 49277
"Hal Murray" <hmurray@suespammers.org> a écrit dans le message news: usk1vc50nb8dff@corp.supernews.com... > > The trick you want is to use a rough analog filter, say one that kills > everything above 40 MHz, sample fast enough to get everything that > gets through the filter (80 megasamples/sec in this example), and > then implement a good filter in the digital side. After that filter > you don't have any signal (or noise) above 20 MHz so you can decimate > your data stream down to 40 megasamples/sec. > Thank you very much. I want to know where I can get a reference design in FPGA about my problem. FPGA venders have such library? Of course, I have to get the analog antialiase filter specification in order to design the digital low pass filter. Are there any such filter designs in FPGA? About the decimating filter, if I select the sample clock rate at integer times of input data rate, I can simply discard some bits regularly? If not, I can digitally interpolate value and decimate data? I have no practical experience about these. What book or website can give me some reference, especially applications on FPGA? ThanksArticle: 49278
The answer is negative: Adding one bit to a 24 bit value is effectively a 24-bit incrementer or counter ( flip-flops are free). That has always taken 24 LUTs. Peter Alfke ========================= Sanjay Patil wrote: > Hi, > We are using Virtex-2 device for one of the applications and We have > observed that the LUT utilization for a 16 + 16 bit adder is 16LUTs and also > 16 + 1bit adder is also 16LUTs. The above is because the Carry chains are > routed through LUTs. Is there any possibility of reducing the LUTs in case > where unequal number of bits are added to less than the Max number of input > vector. i.e. if say 24bits are added with 1bit, then can the logic can be > such that it utilizes less than 24 LUTs > > Can anyne help me. > Regards, > SanjayArticle: 49279
I remember, for I was there :-) Here is what I found today on google: "Mick and Brick". >Back in the "good old days" ... > >AMD had a multipart app note called "Build a microcomputer" which showed >the design for a computer based on the 2901 bit slice parts. This was >later released as a hard cover book. Does anyone remember what this book >was called? I think the authors were "Mick and Brick" (No joke, just >fact). > It's called BIT-SLICE Microprocessor Design by Mick and Brick published by McGraw Hill , ISBN 0-07-041781-4 in 1980 also you might want to look at Bit Slice Design:Controllers and ALU's by Donnamaie E. White ISBN 0-8240-7103-4 ( known as the white book ! ) Both books were written by AMD staff members. Henry Davis wrote: > AMD put out a series of applications notes 20 years ago that made up a > pretty good review of developing ISAs using microprogramming and bbit slice > techniques. > > HenryArticle: 49280
Thanks for the answer - I'm using the apex20ke200 on the nios evaluation board - but the problem is in the compiling stage. When I'm compiling a NIOS design (with nothing but a processor) the compiler reports, that it has used about 1800 LEs but 0 RAM bits. ThomasArticle: 49281
remove extension cable between byteblaster and PC!!!Article: 49282
Peter Alfke wrote: > It's called BIT-SLICE Microprocessor Design by Mick and Brick > published by McGraw Hill , ISBN 0-07-041781-4 in 1980 > > also you might want to look at Bit Slice Design:Controllers and ALU's > by Donnamaie E. White ISBN 0-8240-7103-4 ( known as the white book ! ) And if you really don't have it in your bookshelf, at least the second one is online. Just google around for Donnamaies webpage. cheersArticle: 49283
"Peter Alfke" <peter@xilinx.com> wrote in message news:3DCA9786.5E3BABFB@xilinx.com... > I remember, for I was there :-) > Here is what I found today on google: "Mick and Brick". > > >Back in the "good old days" ... > > > >AMD had a multipart app note called "Build a microcomputer" which showed > >the design for a computer based on the 2901 bit slice parts. This was > >later released as a hard cover book. Does anyone remember what this book > >was called? I think the authors were "Mick and Brick" (No joke, just > >fact). I think I've seen synthesisable implementations of these parts somewhere. Ogle and Gogel wrote a paper on visual perception some years ago. 8-) Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 49284
Peter Wallace wrote: > On Tue, 05 Nov 2002 05:35:54 -0800, Petter Gustad wrote: > > > "Jan Pech" <j.pech@noSPAMieee.org> writes: > > > >> I can't install the Service Pack 2 for my WebPACK. When I run the file > > > > Does anybody know if 5.1 is shipped to all Xilinx customers by now? I > > haven't received mine yet... > > > > Petter > > I got mine a couple of weeks ago. It sits idle on my desk since I am > still running NT4 sp6a and have vowed to let no more Redmond Devils Spawn thru > our portals... > > PCW Ahhh, someone else who understands the joys of a stable O/S. I think I'll just wait till Xilinx go Linux native.Article: 49285
Many thanks Tullio for the answer could you please highlight one of this functionalities. was it used for routing or reconfiguration, and why FPGA? thanks Tullio Grassi <tullio@physics.umd.edu> wrote in message news:<3DC9AF0E.508F0411@physics.umd.edu>... > hristo wrote: > > > > hello, > > i often go through this expression, but never see what it means > > any explanations > > thanks > > More or less it's a jargon to indicate a device that does not perform > any central function, but simply is a bridge to interface between more > powerful subsystems (CPU, DSP, ASIC, etc). > In the old days this was one of the main use of FPGAs. > > -- > > Tullio Grassi > > ====================================== > Univ. of Maryland - Dept. of Physics > College Park, MD 20742 - US > Tel +1 301 405 5970 > Fax +1 301 699 9195 > ======================================Article: 49286
Klaus Vestergaard Kragelund <KlausKVIK@hotmail.com> wrote: : On a side note - could/would you recommend Wine? I'm using Linux - but : haven't dared using Wine yet :-( Look in the Wine Changelog. I play with wine since 1994, so I have a perhaps biased view. Standard Wine is not yet for the faint hearted. Configuration and getting things going may take some time. Often things don't work because of small things, which need to be fixed. File system permissions are one example, But then a lot of things work acceptable, compared with a reboot. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49288
Hi there - can anyone tell me if you get the IP Core generator program included with the ISE web pack? If so does it contain the constant coefficient multiplier cores? Thanks BobArticle: 49289
There are several companies/individuals who have 2901 class products. One commercial company is Cast. Cast, Inc tel: 201-391-8300 f ax: 201-391-8694 11 Stonewall Court Woodcliff Lake, NJ 07677 info@cast-inc.com Henry DavisArticle: 49290
Hello bigg guys,
I got in big troubles and hope you will be so kind to help me.
After discussing with the Xilinx representatives in France, i decided
to implement a board on a Spartan II Xc2s50 -6. They said I can
successfully use the free webpack.. I downloaded it and installed one
week ago about.
Now after turning around few days trying to introduce some schematics
and Verilog module to build our project I am stagged by a very strange
phenomenon which seems like a discrepancy between the datasheet of
Spartan II and the timings spec's implemented by the ISE5.1.02i.
The Datasheet says that for the version -6, the clkdll support up to
100MHz on it clock entry while and for the version -5 only 90MHz.
Based on the Xapp132 we tested separately this idea and have seen
that the ISE sets through the generated sdf file the same time limits
for both version and this limit correspond exactly with 90MHz.. More
specifically the concerning line is:
(PERIOD (posedge CLKIN) (11111:11111:11111))
or the whole definition block for the clkdll results as follows:
(CELL (CELLTYPE "X_CLKDLL")
(INSTANCE dll)
(DELAY
(ABSOLUTE
(PORT RST (1647:1647:1647)(1647:1647:1647))
(PORT CLKFB (1047:1047:1047)(1047:1047:1047))
(PORT CLKIN (6:6:6)(6:6:6))
(IOPATH CLKIN LOCKED (1177:1177:1177)(1177:1177:1177))
)
)
(TIMINGCHECK
(WIDTH (posedge RST) (3000:3000:3000))
(WIDTH (posedge CLKIN) (3000:3000:3000))
(WIDTH (negedge CLKIN) (3000:3000:3000))
(PERIOD (posedge CLKIN) (11111:11111:11111))
)
)
I need to run a piece of logic at 200MHz starting from the 100MHz
crystal. Would you like, please, to explain me how to proceed with ISE
to get the right sdf file or, better, could you send me a full (
simulation included) frequency multiplier example generating 200MHz on
Spartan II -6 ? I am really trapped with the webpack now...
Hoping help :((
Article: 49291Ralph Mason wrote in message ... >Does anyone know of any documents that talk about processor microcode - (an >instruction set that implements an instruction set) > >Thanks for any links >Ralph Take a look at some AMD applications notes that Al Kossow has on his site: http://www.spies.com/~aek/pdf/amd/Article: 49292
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:aq95sd$q1h$1@news.tu-darmstadt.de... > Peter Wallace <pcw@karpy.com> wrote: > : On Tue, 05 Nov 2002 05:35:54 -0800, Petter Gustad wrote: > > :> "Jan Pech" <j.pech@noSPAMieee.org> writes: > :> > :>> I can't install the Service Pack 2 for my WebPACK. When I run the file > :> > :> Does anybody know if 5.1 is shipped to all Xilinx customers by now? I > :> haven't received mine yet... > :> > :> Petter > : > : I got mine a couple of weeks ago. It sits idle on my desk since I am > : still running NT4 sp6a and have vowed to let no more Redmond Devils Spawn > : thru our portals... > > I run webpack through wine on linux... > However impact dosen't work for principal reasons. > Hi Uwe On a side note - could/would you recommend Wine? I'm using Linux - but haven't dared using Wine yet :-( Cheers KlausArticle: 49293
Hi anyone, I'm trying to do a LU-decomposition with xilinx FPGA. It's inside matlab but it's not in the xilinx blockset which mean i cannot implement it using sysgen, any idea?Article: 49294
> Hi anyone, > > I'm trying to do a LU-decomposition with xilinx FPGA. > It's inside matlab but it's not in the xilinx blockset > which mean i cannot implement it using sysgen, any idea? Is the "decomposition" the one related to logic theory? Is it an academic research? Would you please more specific? UtkuArticle: 49295
Dear all,
I have a quiestion about Virtex-II BUFT
(which may be applicable to other Xilinx FPGAs).
I have two BUFTs connected to a common bus,
which are configured below(in VHDL).
-- BUFT instance 1
tbuf_inst1 : BUFT port map(
O => buft_out1, I => '0', T => ctrl1
);
-- BUFT instance 2
tbuf_inst2 : BUFT port map(
O => buft_out2, I => '1', T => ctrl2
);
-- connect buft_out1 and buft_out2 to common line data_bus
data_bus <= buft_out1;
data_bus <= buft_out2;
At first, I have already assigned '0' and '1' to ctrl1 and ctrl2
respectively. This results in data_bus to be driven to '0' and
the circuit retains that state.
Next, aftre re-assigning '1' and '0' to ctrl1 and ctrl2 simutaneously,
the circuit transition may also start simutaneously.
At this time, does bus contention occur on data_bus and hence
any damages to device?
Thanks for any suggestions.
Hiro
Article: 49296Hi, Glue logic means non-regular logic, normally a group of gates working asynchronous in statitc decisions. Regular logic like memory cells is not called "glue". Glue logic consists of simple gates forming logical decisions. The gates can als be used as rs-ffs or dffs. This sort of logic is implemented in CPLDs, FPGAs or Gate Arrays. In earlier times only about 1000 gates were called "glue logic". It is normally supporting higher integrated devices with additional functions (data transfer, buffering, reading sensors etc.): Regards, Roland hristo schrieb in Nachricht ... >hello, >i often go through this expression, but never see what it means >any explanations >thanksArticle: 49297
Friends, Getting my feet wet today patching in a consultants breadboard with an FPGA and their associated Vector board. I am looking for an online reference that has a quick lookup of the pinouts of many of the most popular interfacing chips. This design includes opto-couplers to isolate signal inputs to high energy strobes. The chip in question is the Phillips 74HCT245N, a non-inverting buffer. Seems the designed schematic does not aggree with the wired hardware. Has not been powered for that reason. Thanks, Regards Charles Reply to charlie days@acushnetgolf.comArticle: 49298
Bob -
Webpack doesn't include the Core Gen program (I think by "program"
you mean the GUI that's used to instantiate Core Gen components). Not
100% sure, but you may be able to snag the libraries and still use the
Core Gen components in your designs, although without using the GUI to
instantiate them for your specific needs.
But if Xilinx charges extra for Core Gen, then what I said doesn't
make (financial) sense. I'm going to give it a try....
BT
Bob wrote:
>
> Hi there - can anyone tell me if you get the IP Core generator program
> included with the ISE web pack? If so does it contain the constant
> coefficient multiplier cores?
> Thanks
> Bob
Article: 49299Hello, I have recently installed Version 5.1 of Project Manager and two service packs. I am now about to start a big design. It has been split into blocks. It is a team work that we are aiming at. The idea here is to use Modular design. All I could from the Xilinx website is documents for Modular Design 4.2, which only works by typing command lines. Is there any GUI version of Modular Design for 5.1i ? That would be great really ! Anybody can help me ? Thanks in advance. Philippe.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z