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Thanks for your clarification Ray.
It is now clear to me that Floorplan RPM is completely useless
in my particular case. I want to apply different synthesis goals
to each part (area for the RPM, speed for the rest) and I see
no way to achieve this into a single, flat design.
I already knew i could RLOC the source directly,
but I was reluctant as I'm not comfortable designing at such low level.
I'll try to use the post-translate VHDL equivalent to figure out
how to "synthesize" my original design into RLOCable VHDL.
I would also to try the FPGA Editor way, but before this
I would like to hear more comments about timing analysis
and simulation difficulties that can arise.
Reading the tool manual, it clearly states that
the hard macro saves place info, not routing (timing is not guaranteed).
So I _assume_ routing is still generated and analyzed every time PAR is run.
Am i right here?
Regards
Francisco
"Ray Andraka" <ray@andraka.com> escribió en el mensaje
news:3DB0679F.79D00326@andraka.com...
> If it was created in the floorplanner, you are restricted to using it in
> that design, at least as of v4.2i. You can export it as a UCF file, which
> essentially puts LOCs on all the pieces, so you could bring it into
> another design only if the device is the same size and the hierarchical
> names are unchanged. Not all that useful, I know. The problem with the
> floorplanner (well, one of many problems actually) is that it is not
> hierarchical: it works on a flat representation of your design, so you
> wind up having to floorplan each copy of multiple identical instances
> instead of doing it once unless you do the floorplanning in your source.
> You can also create hard macros using the FPGA editor and bring them in as
> black boxes into your source. I don't like doing that because it makes
> simulation and timing analysis difficult.
>
> We put RLOCs directly into our VHDL so that we end up with placed RPMs
> that can be used in any design without having to go through floorplanning
> every time. In that case, you just instantiate the RPM as a component in
> the HDL code (and stick an RLOC on that component if it is forming a
> larger RPM). Of course, Xilinx says they've never heard of people making
> big RPMs out of smaller ones like this, and the 5.1 tools barf on big
> RPMs...but that is beside the point.
>
> Francisco Rodriguez wrote:
>
> > Hello all
> >
> > I'm working with Xilinx ISE 4.1 tools. I have a small design manually
> > floorplanned and have created an RPM with all the logic, but
> > without IOBs or BUFGs.
> >
> > Now I want to use this RPM as a design black block in a larger design.
> > How do I instantiate it into my VHDL model?
> >
> > Or am I completely wrong on the use of RPMs?
> >
> > Regards
> > Francisco
> > ====================================================
> > Francisco Rodriguez Ballester (prodrig@disca.upv.es)
> > Dept. DISCA, EUI - Univ. Politecnica de Valencia
> > c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
> > tlf: +(34) 96 387 75 77 - fax: +(34) 96 387 75 79
> > ====================================================
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
>
>
Article: 48576Ray Andraka wrote: > > If it was created in the floorplanner, you are restricted to using it in > that design, at least as of v4.2i. You can export it as a UCF file, which > essentially puts LOCs on all the pieces, so you could bring it into > another design only if the device is the same size and the hierarchical > names are unchanged. Not all that useful, I know. The problem with the > floorplanner (well, one of many problems actually) is that it is not > hierarchical: it works on a flat representation of your design, so you > wind up having to floorplan each copy of multiple identical instances > instead of doing it once unless you do the floorplanning in your source. > You can also create hard macros using the FPGA editor and bring them in as > black boxes into your source. I don't like doing that because it makes > simulation and timing analysis difficult. > > We put RLOCs directly into our VHDL so that we end up with placed RPMs > that can be used in any design without having to go through floorplanning > every time. In that case, you just instantiate the RPM as a component in > the HDL code (and stick an RLOC on that component if it is forming a > larger RPM)... Hi, When you make an RPM by putting the constraints in the VHDL source, can you position the RPM on the floorplanner with the mouse, or do you need to rerun the tools a few times and iteratively change the position of that RPM by changing a constraint in the source in order to position various RPM blocks together?Article: 48577
First, I'll admit that I haven't upgraded to 7.2 yet, We're using 7.03 until we
get these few projects out the door because we know it is stable and we know the
quirks in it. 7.1 broke a bunch of our things, and with the schedule we didn't
have too much time to mess with it. Now the schedule is tighter, and I don't
have the slack time to learn the quirks in another tool (got enough tool debug
going on with the recent Xilinx releases...uh, 'escapes' as it is).
For the SRL16's, We generally try to put the last clock of delay into a FF
because of the relatively long clock->Q of the SRL16. I can't have that
flip-flop getting sucked into the SRL16, even if such modification is controlled
by the clock period. We generally turn the clock to 0 in synplify to keep it
from duplicating stuff that is RLOC'd in aggressive designs. That works fine as
long as the logic between registers is reasonably simple (eg., single level of
logic), but it also means that I don't want ff's I intend to follow an SRL16
getting absorbed into the SRL16. I also don't want the SRL16 inference
automatically putting a flip-flop at the end if the SRL16 address is dynamic.
For static SRL16 address, automatic inference of a flip-flop after *EACH* SRL16,
even when there are several SRL16's in a chain is a nice feature. I believe 7.03
does that just for the last SRL16 in a chain.
Allan Herriman wrote:
> On Mon, 21 Oct 2002 05:49:16 GMT,
> allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote:
>
> >On Sun, 20 Oct 2002 13:52:38 +0100, Rick Filipkiewicz
> ><rick@algor.co.uk> wrote:
> >
> >>
> >>
> >>Allan Herriman wrote:
> >>
> >>> On Sat, 19 Oct 2002 16:15:01 GMT, Ken McElvain <ken@synplicity.com>
> >>> wrote:
> >>>
> >>> >Thanks! Actually there are several of the hotline folks that read the
> >>> >newsgroup, but we limit the number of posters.
> >>>
> >>> Ah, good. I'd like to know what you are doing about the SRL16
> >>> inference rule change between 7.0 and 7.1. We have a number of
> >>> designs here that break in 7.1 and 7.2 because Synplify Pro is
> >>> inappropriately changing FF into SRL16E.
> >>>
> >>> Problem 1 (fixed in 7.2 beta) Some FF with 350MHz clock get converted
> >>> to SRL16E. SRL16E don't work at 350MHz (in Virtex2).
> >>>
> >>> Problem 2 (still outstanding) Some FF with async reset get converted
> >>> to SRL16E. SRL16E don't have an async reset input, so this is a
> >>> functional change.
> >>> (It's that old problem of Synplify trying to be too clever about the
> >>> meaning of GSR when the startup block is present. If an FPGA has an
> >>> external reset input (connected to the startup block) then it is *not*
> >>> correct to assume that GSR is only active during configuration.)
> >>>
> >>> Problem 3 (still outstanding) Some FF that were in IOBs get converted
> >>> to SRL16E. This breaks the I/O timing on the part.
> >>>
> >>> Problem 3 is actually the worst one for us, since most of the designs
> >>> infer I/O FF.
> >>>
> >>
> >>Does `syn_useiobffs' stop it inferring SRL16Es ? If not this is a killer
> >>bug and mucho thanks for the warning as I was just about to make the move
> >>from 7.0.2 -> 7.2.
> >
> >Haven't tried that one. This is legacy code that doesn't have many
> >tool specific attributes.
> >In general, I don't like littering my code with attributes just to get
> >reasonable behaviour from the synthesiser, particularly when earlier
> >versions of the same synthesiser did the right thing.
> >But I guess it all hinges on the meaning of "reasonable" ...
> >
> >As we saw with the tristate buffer push through bug, tool vendors can
> >have a rather odd view of what customers want from their tools.
> >
> >>>
> >>> I rather liked the 6.x rule that only allowed an RTL FF to be
> >>> converted to SRL16E when the FF was coded without an async reset or
> >>> set.
> >>>
> >>
> >>In fact I can't see how Synplify can legally infer an SRL16(+/-E) for an FF
> >>with any sort of set/reset sync or async since the Xilinx primitive doesn't
> >>have a reset pin!. IIRC this was actually broken in 6.0beta and I had a I2C
> >>module shift reg with sync. clear inferred as an SRL16. Got fixed in 6.1 I
> >>think.
> >
> >Well, it seems to be broken again.
>
> Minor clarification: If the GSR net is connected to a ROC block, then
> the synthesiser can know that GSR is only active during configuration,
> and therefore it is safe to convert a FF (with async set or reset)
> into an SRL16(E).
>
> But the problem I was seeing had to do with an async reset net that
> had an external connection, therefore no conversion is possible.
>
> Regards,
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48578
Well, you are supposed to be able to pick up the RPM from the hierarchy browser
and place it with the floorplanner, but the floorplanner is broken in 4.x. In
order to place RPMs, you need to run through automatic place and route, then
open the floorplanner, constrain the RPMs from placement, unbind and rebind each
RPM, then you can move it around. It is a very awkward and time consuming
workaround that does not work for densely populated designs with large RPMs. Do
us all a favor and complain to XIlinx about the broken floorplanner. There is a
general attitude there that floorplanning is only used by a few experts, and so
it is the neglected stepchild. The fact of the matter is that floorplanning is
crucial to any form of modular design capability, and until they recognize it
they probably will not get a reasonable modular design flow. With the size of
current devices, modular design is the only way to achieve reasonable design
times. Right now, big hierarchical design with big rpms is the easiest way to
achieve a semblance of modular design in the tools. I have not tried out the
floorplanner in the 5.1 software yet because of the long map times associated
with big RPMs. I understand that a patch is forthcoming for that bug if if
bites you.
Russell wrote:
> RHi,
> When you make an RPM by putting the constraints in the VHDL source,
> can you position the RPM on the floorplanner with the mouse, or do
> you need to rerun the tools a few times and iteratively change the
> position of that RPM by changing a constraint in the source in order
> to position various RPM blocks together?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48579
The edif netlists are hierarchical, and have been since day 1. The problem is Xilinx views
the world as flat, so it flattens everything. Until thier tools view the designs as
hierarchical rather than flattened, I think they will continue to have problems with large
designs and RPMs, and will probably not be able to achieve a reasonable modular flow. We
currently work around the shortcomings of the flat world society in EDA land by building RPMs
hierarchically in the source, which leads to big placed RPMs, which in turn broke the 5.1
Xilinx tools as mentioned earlier in this thread.
Russell wrote:
> I'll be doing designs with multiple large RPMs too. Are the netlists
> hierarchial in 5.1?
>
> Efficient handling of hand-routed RPMs in a hierarchial netlist
> is what i consider to be *the* most important feature. It should
> be easy to build low-level RPMs and link them together to make
> larger RPMs, until you've done the whole project from the bottom
> up.
>
> In the end, your whole project is an RPM, which you could re-use
> as a library component. It's not hard to see that anyone could
> be building mega-chip designs from these components in just a
> few minutes. It's this sort of capability i'd aim for in an
> open source tool.
>
> lass wrote:
> >
> > Ray,
> >
> > This is planned to be fixed in our 5.2i release. We might be able to create a tactical
> > patch for you before that, but it sounds like you are not using 5.1i and since no other
> > customers have run into this problem, the current plan is to wait until 5.2i (Feb).
> >
> > Steve
> >
> > Ray Andraka wrote:
> >
> > > I wish that were the case. This is something that broke in 5.1 that causes map
> > > to take 25+ hours to complete where it completed in less than 2 hours on a
> > > machine with half the speed and memory (and paging like crazy on that machine)
> > > using 4.2...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48580"Murali K Warier" <muralikwarier@yahoo.com> wrote in message news:f7eeeb58.0210202233.15eb8b76@posting.google.com... > Hi All, > > I tried to download the free Webpack software from Xilinx website. > Whatever I did, I could not download the single file (170 MB) beyond > 26%. I tried two download managers, GetRight and Gozilla, to no avail. > The server is always busy with something else. Is there a way around? > I do have a fast connection to the net. Thanks for any suggestions. I downloaded it, but it wouldn't install properly. I complained to Xilinx support (UK) and they posted me a copy on CD-ROM. 8-) Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48581
Hi all, As anybody tried to use Nios dev. tools and quartus on a Linux workstation ? What are the cons and pros ? Are the tools easy to use ? Are there special things to take care off ? Is the use of the RedHat 7.1 mandatory or is it possible to use those EDA soft with other linux distributions such as Mandrake (9.0 for instance) or Suse or whatever ? Thanks very much for your comments. StephaneArticle: 48582
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3DAF3240.C6961041@yahoo.com>... > Bert Wibble wrote: > > > > Interesting point about the Altera pricing. My company has > > traditionally always used Xilinx parts - and we have no complaints. > > Recently we spoke with Altera, and their pricing was far better than > > what Xilinx would offer for an equivalent part. But, typically, we > > have no time to invest in changing to an Altera part - so we end up > > staying with Xilinx because we know the parts - and pay more for them. > > I feel that maybe Xilinx trade on this point of view - and this allows > > them to keep their prices high. Thoughts ? As a small-company engineer, I am convinced that there is a huge elasticity in pricing, and if they think they've got you, you will pay more, while if they think the other guy has got you, well there can be some deals to be had. > Last year I worked with a company who made a point of competing both > vendors on every design they started. It actually hurt them a little It is gratifying to hear that other people think this way. I have always believed that cost is determined (and can be influenced) early in the design process (for example while selecting components), yet I have come across numerous engineers who believe that parts cost what they cost and that getting the price down is the job of purchasing. How can purchasing possibly do this effectively after the part is designed in... where is the negotiating leverage ? My sense is that boards these days have a significantly higher proportion of cost tied up in sole-source components, compared to say 10-15 years ago, and that a mindset that worked well then may be less appropriate today. > technically since they could not make use of special features on the > chips, but they felt in the long run it was a better way to go because > it made the chips cheaper. I'm not sure I agree with this Rick, because I believe that the special features get factored in to the comparative decision. For example last year I had a board where the logical choice would have been A. parts (we were using them already), but X. parts fitted much better because I could get more block RAM (which that design needed) at a lower price. Same thing this year, I've got a design underway in a 2V250, but with the hoopla attending the Cyclone family I ran the numbers to see how much I would save if I could wait a little and go that route. Well guess what... the design would require a bump-up in size because of the memory requirements -- wasting a ton of logic elements, and there's no significant cost saving to be had. On the other hand, if a design has to be built so that it can freely migrate between families, then that's a different story -- and I absolutely agree that the design would suffer for it. Best, -rajeev-Article: 48583
Murali K Warier wrote: > Hi All, > > I tried to download the free Webpack software from Xilinx website. > Whatever I did, I could not download the single file (170 MB) beyond > 26%. I tried two download managers, GetRight and Gozilla, to no avail. > The server is always busy with something else. Is there a way around? > I do have a fast connection to the net. Thanks for any suggestions. I had the same problem, i could not download it with mozilla or galeon. With wget it worked, but i could see that it needed 3 or 4 retries to get the whole file. So give wget a try , that should work. - Erwin > > Thanks and regards, > Murali.Article: 48584
Blackie Beard <BlackBeard@FearlessImmortalWretch.com> wrote: > One of the stupidest things about Altera Quartus S/W (at least the > first versions, I don't know about later ones) was that hidden about > 4 submenus down, was the setting for what to do with unused pins, > the default choice; "As Outputs Driving Ground". What if you have > the board made first, with the I/O in place, and want to add the > various interface blocks of the design in incrementally? You can > get some real hot chips. You must know about this setting, and > find it and change it to "As Tri-State Inputs", and remember to do > so with any design revisions, or your prototype is toast. I tried to > tell Altera, but to no avail. oh, so I am not the only one who learned this about feature the hard way...Article: 48585
Your task can vary from really easy to really hard depending on how many of the FPGA vendor's specific features are being using (as opposed to generic VHDL). Altera doesn't use the "Slice" concept, ignore that part of the report for your comparison. A Slice register, is just a register. And a LUT is just a LUT. The most likely issue you're going to run into is how to handle rams. Depending on your front end tool suite, you may have to change RTL to make up for the difference in how Altera and Xilinx handle RAMs in an HDL flow. If your sister firm was enlightened, and was able to use inferred ram through your systhesis tool (like Synplify), then it just may be automatic. The fact that you see 342 LUTs used up for RAM in the Xilinx part is probably not a problem. You'd have to tell me what those 32x1's are being used to build up to. Altera's Stratix line has a whole heirarchy of ram sizes that consume no LUTs. If it ends up that you're dealing with a large number of little rams, then this would be a good family to target. Regards "Sven T" <hw_engineer@NOSPAMgmx.net> wrote in message news:<ap0bk3$cjq$1@vistranem1.vi.vector.int>... > Hi there, > I have the following problem. > A partner firm has a design implemented on a XILINX Virtex XCV800. > The design is in VHDL and I want to check if this design can be ported to an > ALTERA. > > Could anyone explain me the following terms that I get in the report of the > XILINX Dev-Tool and give me the correspondig term for an ALTERA device ? > > - Slices > - Slice reigster > - LUT > > I think the LUTs are comparable to the ALTERA LUT aren´t they ? > > On epoint is that 342 LUTs are used as 32x1 RAM. > If I interpret the ALTERA datasheet correctly I cannot implement ram in that > small portions. > Is there a way to implement RAM in LUTs ? > > Thanks in advance > SvenArticle: 48586
You will find that the number of chips is not so interesting, it is the level of business people are interested in. If the volume is low, the price needs to go up. I think you need to look at total business of $100 k for people to be interested in ASIC. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden. "dave garnett" <dave.garnett@metapurple.co.uk> skrev i meddelandet news:3db2cff0$0$9445$cc9e4d1f@news.dial.pipex.com... > I've delivered a prototype based on large cpld's (xc95288xl), and now the > customer is asking about the costs of a production version. I suspect that a > relatively modest fpga would also work well for this application - think > 85MHz clocks, multiple 32 bit wide data paths, interface to a modest frame > store. > > So the question is, at what sort of production volume should I be asking > about ASIC's ? > > The last time I investigated this, nobody seemed to think that it was worth > considering for less than 10k+ units/per annum, plus the fact that it would > take 6 - 9 months to get working silicon. Since then, the impression I have > gained is that fpga's are even more competitive, together with the usual > advantages of being 'soft' - but what do you find in practise ? > > Any info or pointers welcome > regards, > Dave > > >Article: 48587
Ray Andraka wrote: > Well, you are supposed to be able to pick up the RPM from the hierarchy browser > and place it with the floorplanner, but the floorplanner is broken in 4.x. In > order to place RPMs, you need to run through automatic place and route, then > open the floorplanner, constrain the RPMs from placement, unbind and rebind each > RPM, then you can move it around. It is a very awkward and time consuming > workaround that does not work for densely populated designs with large RPMs. Do > us all a favor and complain to XIlinx about the broken floorplanner. There is a > general attitude there that floorplanning is only used by a few experts, and so > it is the neglected stepchild. The fact of the matter is that floorplanning is > crucial to any form of modular design capability, and until they recognize it > they probably will not get a reasonable modular design flow. With the size of > current devices, modular design is the only way to achieve reasonable design > times. Right now, big hierarchical design with big rpms is the easiest way to Actually, if you use the new MultiPoint features in Synplify Pro 7.2 feeding into the area group based P&R incremental flow, you get very good iteration times for large designs. The whole flow becomes incremental to the level of the area groups. Synplify Pro automatically detects differences in the source code (not file dates, that is too crude - especially for VHDL package file changes) that affect each area group and only recompiles as needed. - Ken > achieve a semblance of modular design in the tools. I have not tried out the > floorplanner in the 5.1 software yet because of the long map times associated > with big RPMs. I understand that a patch is forthcoming for that bug if if > bites you. > > Russell wrote: > > >>RHi, >>When you make an RPM by putting the constraints in the VHDL source, >>can you position the RPM on the floorplanner with the mouse, or do >>you need to rerun the tools a few times and iteratively change the >>position of that RPM by changing a constraint in the source in order >>to position various RPM blocks together? >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 48588
"Matthias Dyer" <dyer@tik.ee.ethz.ch> skrev i meddelandet news:3daad887@pfaff.ethz.ch... > In our lab we'd like to add an reconfigurable module to a mobile > Bluetooth-Node (BT & uC). Issues as low-power, flexibility and performance > are important for us. > > I first thought about a CoolRunner II implementation but I think we are too > limited with CPLDs. We also want to enable partial and dynamic > reconfiguration where I believe that the Virtex family is leading. > > Has anyone used Virtex FPGAs in an low power embedded design? > What system-level power saving possibilities do I have (not in the FPGA > design)? > > Or do you have other suggestions for other components? > > Thanks for any help > > Matthias Dyer > What is your microcontroller? The FPSLIC implements AVR uC + FPGA. It will be low power since the connections are internal. The AVR is limited to 32 kB of code/4 kB of data so you cannot run a very big system. The FPGA portion is 5k/10k or 40 k gates and supports partial reconfiguration. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden. > > -- > ------------------------------------------------------------- > Matthias Dyer phone: +41-1-6327061 > Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 > CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch > > Computer Engineering and Networks Lab (TIK) > Swiss Federal Institute of Technology (ETH) Zuerich > -------------------------------------------------------------Article: 48589
It is always changing. Start a new and try to set the device. You should get to some screen that lets you pick all the parts the version supports. Steve "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1035193081.979262@turtle.ru.ac.za... > Does Foundation 4.2i support Spartan IIE???? > > Adrian > > >Article: 48590
Hi, I have created through quartus .mif files for a lpm_rom(altera devices). While simulating it in modelsim I am getting error as "Not a proper intel hex file". Any clue why is not taking .mif file? When I gave .hex file as initialization file, the simulation is correct. But I want to create a hex file of 10kb. So it is very difficult to write all the data in hex file editor of quartus one by one.. Any body can give me solution how to create a .hex file with my own hex data ?Article: 48591
I hope that somebody out there can help me with this installation issue: For a lab course I need ISE 5.1i to run on a student accessible PC. Everything works fine if one is loged into an administrator account. But when I try to start Modelsim from a restricted account I get a message: "Your evaluation license is no longer valid. If this has happened in error, please contact Model Technology Customer Support for assistance. Evaluation Error Code : 104" The licensing wizard tells me: "Your evaluation license has been invalidated because a text file necessary for licensing cannot be written. In order to continue with the evaluation of Modelsim you will need to correct the error, re-install the evaluation copy and re-request an evaluation license from Model Technology." Which is strange, because I do not use an evaluation license. I checked that the LM_LICENSE_FILE variable for the user points to the same license file that the administrator uses. Of course I contacted modeltech support. They pointed me to the Xilinx US support who forward my request to the german support team who just don't have a clue. (I had to point out some related answers from their database before they agreed that apparently ISE is supposed to work for restricted users) So, anybody know which file permissions need to be changed to get this working? Thanks in advance, Kolja SulimmaArticle: 48592
Stevenson wrote: >Hi, >I'm developing an application using Xilinx FPGA (XC4005) and the ISE >foundation software from Xilinx. >I've got a little question: it exists a way to delay some signal (just a few >nanosec) using the schematic editor??? >I tried to use a little "chain" of inverters, but this work only before >implementation! (because it performs a logic minimization...). > > I do this on some Xilinx CPLDs. I had to use external delays because there is no (system) clock in the CPLD designs. What I did was feed the signal out a pin, through a resistor, and back in another pin. This, of course, eats up 2 pins. The capacitance of the input pin is the C for the RC delay. I used a 5100 Ohm resistor for a pretty long delay for cable deskew. Maybe 50 to 100 Ohms, or even zero Ohms would do it in your case. Just the delay of the output and input pads would probably give you your "few NS". It is also possible to make the intermediate signal go to an unbonded I/O pad, with an obuf and ibuf. This won't be optimized away, and it doesn't eat up a pad. (I'm not sure how to command ISE to allow you to use an unbonded pad, but I think you have to select it by physical location (row, column). JonArticle: 48593
Hi Kolja, It has been seen that if you do the following then you may be able to run Modelsim without Admin privileges: 1. Delete .mti_enc and .mti_enc2 in the WINDOWS directory, and delete the mti_em file in the C:\Modeltech_xe\win32xoem directory. Note that these files may be hidden in your system. 2. Set the license file permissions to enable the use by the user and the system. Note that the location of the license file should also be specified in the LM_LICENSE_File environment variable. Regards, Martin Kolja Sulimma wrote: > I hope that somebody out there can help me with this installation > issue: > > For a lab course I need ISE 5.1i to run on a student accessible PC. > Everything works fine if one is loged into an administrator account. > But when I try to start Modelsim from a restricted account I get a > message: > "Your evaluation license is no longer valid. If this has happened in > error, please contact Model Technology Customer Support for > assistance. > Evaluation Error Code : 104" > > The licensing wizard tells me: > "Your evaluation license has been invalidated because > a text file necessary for licensing cannot be written. > In order to continue with the evaluation of Modelsim you will need to > correct the error, re-install the evaluation copy and re-request > an evaluation license from Model Technology." > > Which is strange, because I do not use an evaluation license. > > I checked that the LM_LICENSE_FILE variable for the user points to > the same license file that the administrator uses. > > Of course I contacted modeltech support. They pointed me to the Xilinx > US support who forward my request to the german support team who just > don't have > a clue. (I had to point out some related answers from their database > before they agreed that apparently ISE is supposed to work for > restricted users) > > So, anybody know which file permissions need to be changed to get this > working? > > Thanks in advance, > > Kolja SulimmaArticle: 48594
Adrian, ISE refers generally to the Design Tool. There are four configurations of this tool that you may use, and Foundation is one of them. The other configurations include Alliance, BaseX, and WebPACK. You can check here for more info: http://support.xilinx.com/ise/devsys_feature_guide.pdf I hope this helps. Regards, KamalArticle: 48595
I have been trying to learn verilog with the aim of designing a cpu I have
an idea of. I have been using the Very good document by Jan Gray on his
system on chip design.
I have a couple of queries, an odd mix of them.
1. As a learning process I have copped his adder, he says that it turns
into 17 LUT's although mine ends up at 52 - Is there some optimizations I am
missing here? are there any pragmas you can use in these situations to say
what you want? Can you get right down to the actual LUT level and connect
them up yourself? Using the free Xilinx tools can you actually see the way
it has connected the actual LUTs?
module addsub(clk, fn, carry_in,carry_out,x,a,b,sum);
input clk, fn,carry_in;
input [15:0] a,b;
output [15:0] sum;
output x,carry_out ;
assign {carry_out,sum,x} = fn ? {a,carry_in} - { b,1'b1 }
:{a,carry_in} + { b,1'b1 } ;
endmodule
2. Floorplaning - Is there any info on this, it seems that you don't need
to do it because the tools do it automatically, I am guessing sometimes you
can do it better yourself to give a faster device? It looks like a
laborious process - is it?
3. General - The CPU I want to design is a RISC / CISC design where a pre
processor reads CISC instructions from ram and places RISC instructions (or
jumps to RISC subs) to do the same them in an internal pipeline for a RISC
internal cpu ( or perhaps many instances of the same RISC cpu and a single
pre processor to provide a kind of hardware multithreading) - Is there any
notes on existing designs like this that one could read.
Thanks for any help / suggestions / ideas
Ralph
Article: 48596I found out that the multilinx drivers didn't install correctly. I have windowsXP, but i tried the software and the hardware on win98 everything worked OK. It would still be nice to make iMPACT to work with XP. I have webpack 4.1, are newer versions without this mistake? Is there anyway to get rid of this problem? thanks "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:aoutlh$q7img$1@ID-84877.news.dfncis.de... > "Klemen" <nec4b@email.si> schrieb im Newsbeitrag > news:aou0m4$6fq$1@planja.arnes.si... > > Recently i got the insight spartan II demo board and xilinx webpack, but i > > can't get the board to work. Xilinx iMPACT doesn't recognize it. The board > > is connected with the computer through jtag cable. I tried all sorts of > > combinations with the jumpers on the board, but no matter what i do it > just > > doesn't work. I'm a beginner with fpga and i'm getting very frustrated > with > > not finding the mistake, please help. > > Check the voltage on the board. There are two regulators, als well as two > testpins for 3.3 and 2.5V. > Check the connection from the JTAG cable to the board. DO you connect to the > right pins? Nothing mixed up? > The cable comes with two flying leads connectors, make sure you use the > right on and hav connected to the right pins on the cable (usually you can > mix it up, unless you use brute force) > Have you installed the software propperly? Sometimes something goes wrong > with the multilinx parallel port driver installation. > > -- > MfG > Falk > > > >Article: 48597
"Steve Casselman" <sc@vcc.com> writes:
> There are 8 frames in the beginning that only have the main clock buffers
> and the DLLs in the frames the middle portion is 0's.
Those 8 frames are only GCLKs in the "top" and "bottom" rows (same
positions as the north/south IOBs are relative to CLBs), no DLLs.
The DLLs are in the same "top" and "bottom" sections of the BRAM control
frames (27 per BRAM column). That is why there are 4 DLLs, 2 each per
BRAM column. The "top" and "bottom of the 2*64 BRAM data frames seem to
be empty, dito those of the 2*54 west/east IOB frames.
Also the "middle" (same position as CLBs) of the GCLK frames has some
stuff in the 8th frame:
1st to 7th frame (on XCV300, null300.bit) are all like this (slight variation):
00
0000220 12 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000260 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000300 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000320 00 00 00 00 00 00 00 00 00 40 04 80 00 00 00 00
0000340 00 00 00
but the 8th frame has "middle" stuff:
ff 12 00 0a 00
0001340 02 80 00 a0 00 28 00 0a 00 02 80 00 a0 00 28 00
0001360 0a 00 02 80 00 a0 00 28 00 0a 00 02 80 00 a0 00
0001400 28 00 0a 00 02 80 00 a0 00 28 00 0a 00 02 80 00
0001420 a0 00 28 00 0a 00 02 80 00 a0 00 28 00 0a 00 02
0001440 80 00 a0 00 28 3f c4 00 00 00 00 00 00 00 00
only then comes the first CLB frame:
c0
0001460 07 fc 00 ff 00 3f c0 0f f0 03 fc 00 ff 00 3f c0
0001500 0f f0 03 fc 00 ff 00 3f c0 0f f0 03 fc 00 ff 00
0001520 3f c0 0f f0 03 fc 00 ff 00 3f c0 0f f0 03 fc 00
0001540 ff 00 3f c0 0f f0 03 fc 00 ff 00 3f c0 0f f0 03
0001560 fc 00 ff 00 3f c0 0f f0 03 f0 00 f0 00 00 00 00
0001600 00 00 00
> the V1 devices have lots of ones and zeros.
Yes. and in an funny "banded" pattern.
> If you look at a bit file in a
> binary editor you'll see this.
I use "od". That is what the above are cut&paste from.
Sorry, "vd" does not yet list non CLB stuff, so no nice formatted
output from it here. That is in the next milestone of its development.
> I just ran my software for the V2 and those
> devices do have 0's for a blank configuration.
Interesting. So LUTs are not stored inverted? Or do they default them
to output-ones in the null files?
> Also they have all the
> configuration bits for a look up table in the same frame.
Vertical LUTs? Sensible. Was one of the weaknesses in V1, slow on
read-out.
Hmmm. I knew they have an 80(vert)x22(hor) format.
--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer
- hardware runs the world, software controls the hardware
code generates the software, have you coded today?
Article: 48598Well, I'm asking because I am about to install either Foundation 4.2 or ISE 4.2 for use with a Spartan IIE. Finding out before I install Foundation will save quite a bit of time. Adrian > It is always changing. Start a new and try to set the device. You should get > to some screen that lets you pick all the parts the version supports. > > Steve > > "Noddy" <g9731642@campus.ru.ac.za> wrote in message > news:1035193081.979262@turtle.ru.ac.za... > > Does Foundation 4.2i support Spartan IIE???? > > > > Adrian > > > > > > > >Article: 48599
Hi, Probably should have worded question a bit better. Thanks for the reply, but I am still a bit confused. I have a 4.2 upgrade pack which consists of a set of CDs for installing Foundation 4.2, and another set for installing ISE 4.2. How is ISE different to Foundation?? I want to design for a Spartan IIE, so which should I install? I checked the datasource CD to check which device families are supported, and it said ISE Foundation supports Spartan IIE. Perhaps ISE is used in a different context here? Adrian > Adrian, > > ISE refers generally to the Design Tool. There are four configurations of this tool that you may use, and Foundation is one of them. The other configurations include Alliance, BaseX, and WebPACK. > > You can check here for more info: > http://support.xilinx.com/ise/devsys_feature_guide.pdf > > I hope this helps. > > Regards, > Kamal
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