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Matthew John Duane wrote: > > Does anyone have any suggestions/examples for creating an interface > between a Xilinx FPGA and NAND flash? I am working for the University of > Michigan on the FEGI project, and we are experiencing difficulty > communicating between our Spartan IIE FPGA board and the Samsung 128 MB > NAND Flash we are using for data storage. We already looked at the Xilinx > website and downloaded their one "schematic," but it was not detailed > enough for us to make much sense out of it. If anyone here has any quick > tips/advice, or an example bit of code that they have written, it would be > greatly appreciated if you could send it to us. Thanks.--Matt > > Matthew John Duane > University of Michigan-College of Engineering > Computer Engineering > Phone Number-School > 734-663-9219 > mduane@engin.umich.edu I am working on a design that will be using a NAND flash chip. From what I have read in the data sheet it is not complex. The documentation is a bit obtuse however. I was reading the Toshiba docs, but I expect they are very similar to the Samsung parts. I will be working on the flash interface design in about a month or so. But if you want to give me a few details of your problem I would be happy to swap ideas. We can do this either here or by email. See below. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57451
"Nicholas C. Weaver" wrote: > > In article <3eff173f$1_3@newsfeed>, DK <dknews@ueidaq.com> wrote: > >Hi, All > > > >for the new multichannel filter design I have a choice - > >Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) > > > >Xilinx part has a embedded MAC units. > > Spartan 3 does not have embedded Serdeses, IIRC. Only the > V2Pro/V2Pro-X have the serdeses. > > >Does any one has experience with Xilinx support? And is it possible to > >obtain a free tools from Xilinx or they charge for the software? > > Xilinx Webpack currently doesn't support the big Spartan-3 chips, so > you would have to pay for Foundation. > > Spartan 3 is very low voltage, which may be a problem for some designs > but not for others. It may add an additional voltage you would not > otherwise have, but the Cyclones already pretty low. > > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu That is a good point about the tools. I forget that the XC3S is only supported in webpack in the XC3S50 now and I think only up to the XC3S400 in the next release. I honestly don't get the idea of selling very low cost chips and not adding them to the free tools. I don't expect the OP will find a large difference in the support of the two vendors. Both have phone support answered by novices and will have to get back to you with answers to the tougher questions. As to the voltage, depending on the other chips on the board, the XC3S parts may be the perfect fit. On my board the DSP core voltage is 1.26 which matches the 1.2 of the XC3S pretty well. But good luck getting a price on the XC3S1000 at this point. The XC3S1000 parts have been pushed back due to design problems and will not be out until Q1 or perhaps later. The XC3S400 and one of the larger parts will be out in 4Q03 according to their schedule. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57452
Steve Casselman wrote: > > What you should really do is count the number of times someone from Xilinx > has answered questions on the NG and the number of times you see someone > from Altera (or other vendors) answer any questions. I think you will see it > is about 100 to 1. A question about Xilinx will almost always be answered > where as a question about Altera will only be answered by some other user. > So basically you see more Xilinx questions because users know they will get > an answer by someone who knows what they are talking about. You can't say > that about Altera. Except that I often am contacted by Altera directly rather than here in public. I can understand why they would do that. I think you will also find that very recently there are a lot more posts here from Altera. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57453
Luiz Carlos wrote: > > > > You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, > > > RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", > > > not half of the ditributed memory! > > > > Unless I am missing something, I still don't see the issue. My point is > > that it is a rare design indeed that needs even close to half the LUTs > > used as distributed RAM or SRs. Most designs use a small number of SRs > > and RAMs and the rest of the chip is used as logic. > > Rick, I donīt know about other applications, but this kind of dual > ported memory helps me a lot. I use it primary as memory for filters, > and the fact that I can have a write and a read separate ports, save > me a lot of logic and let me run the filters at double speed (or half > clock rate). The block RAM is not usable because the throughput: I > have a lot of filters running in parallel. So these wider memories let > me implement bigger filters at high speed without to much > complication. Of course I can, and have to live without them in > Spartan3, but if Iīm not alone, maybe in Spartan4... Again, I don't think you are reading what I am posting. In the XC3S400 there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs capable of being RAMs and SRs. How many do you really need??? That is 56,000 bits of distributed RAM, almost a quarter as much as the block rams! Don't you need some LUTs to use as logic??? I am sure that nearly any design that will run in a VirtexII will also run in a Spartan 3 with as many CLBs (Ray Andraka aside). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57454
In article <3F00FF90.FB2A0E20@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Again, I don't think you are reading what I am posting. In the XC3S400 >there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs >capable of being RAMs and SRs. How many do you really need??? That is >56,000 bits of distributed RAM, almost a quarter as much as the block >rams! Don't you need some LUTs to use as logic??? The wider address rams will require external muxing/control to implement with only 4 LUTs/CLB usable as ram rather than 8. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57455
Followup to: <vfv8tlhpgtpk57@corp.supernews.com> By author: "Jerry" <nospam@nowhere.com> In newsgroup: comp.arch.fpga > > > > I come from the ASIC side, and I have > > > something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get an > > > error saying the divisor must be a power of 2. Looking around, it > > > seems that this cannot be implemented into HW?? > > > > The limitation is with your synthesis tool, not the capabilities of FPGA. > > > > > Any advice is appreciated. > > > > Buy a good book on computer arithmetic and implement the operation > yourself > > (or alternatively search a bit hardware around the web and you're bound to > > find some example code). Don't expect the resultant hardware to be small. > > > > Cheers, > > JonB > > > > > To expand on what JonB said, there is a trade off between gate count and > number of clock cycles required to perform the operation. > To further expand... Something that reads in Verilog like what you have above is all-combinatorial logic, meaning no loops and no latches. Not even microprocessors usually have combinatorial dividers, because of the sheer amount of area required; you may want to see if you can't use a clocked design instead. Common designs are 1, 2 or 4 bits per clock. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57456
I am now designing a FPGA based video processing board for my own use. The board has standard NTSC/PAL, HD and DVI input., a VirtexII FPGA, 64 bit DDR-SDAM interface, DVI/RGB/YPbPr output, I2C and UART communication port. Recently, I heard some interests from others saying that they might want to verify their video processing cores (video scaling, de-interlacing, OSD, motion compensation etc.) on my video board before they are implemented in ASICs. So I wonder if there is any similar interests from this news group and I really like to get some feedback from those video guys. Maybe I can modify my design and make a video evaluation board which is capable of general purpose video processing verificarion. It won't take me much extra efforts to modify the board, but it is real beneficial to those who like have their ASIC design verified in FPGA but don't want to design their own FPGA boards. JunArticle: 57457
Hello, Pls see xapp354 'Using Xilinx CPLDs to Interface to a NAND Flash Memory Device' Sandeep "Matthew John Duane" <mduane@engin.umich.edu> wrote in message news:Pine.SOL.4.44.0306301043500.11458-100000@blue.engin.umich.edu... > Does anyone have any suggestions/examples for creating an interface > between a Xilinx FPGA and NAND flash? I am working for the University of > Michigan on the FEGI project, and we are experiencing difficulty > communicating between our Spartan IIE FPGA board and the Samsung 128 MB > NAND Flash we are using for data storage. We already looked at the Xilinx > website and downloaded their one "schematic," but it was not detailed > enough for us to make much sense out of it. If anyone here has any quick > tips/advice, or an example bit of code that they have written, it would be > greatly appreciated if you could send it to us. Thanks.--Matt > > Matthew John Duane > University of Michigan-College of Engineering > Computer Engineering > Phone Number-School > 734-663-9219 > mduane@engin.umich.edu > > "Just imagine if your name was Anonymous. You'd get credit for everything > no one wanted credit for." >Article: 57458
Hi, I am designing a DDR SDRAM controller in a Virtex-II 1500 -5 FFA896. It should operate at 166 MHz towrads the DDR SDRAM. I have used XAPP266 as reference regarding the timing analysis towards the DDR SDRAM. In XAPP266 one of the "results" is: 0.503ns<tDQS-tDQ<1.025 (midpoint at 0.76ns). This delay is introduced by routing? If the PCB delay is 180ps pr. inch. it would require a DQS net that is 4.2 inches? Is this correct??? regrads Jon Terje HauglandArticle: 57459
When is Quartus version 3 coming out? fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0306300026.7c3b3c8@posting.google.com>... > Hi Ben, > It is possible at the moment to build a Nios for FLEX10KE family with > the SOPC builder. But since you talking about 70kgate FLEX I am > guessing you are looking at FLEX10K (5.0V) family. This family is not > at the moment supported in Quartus hence not supported for Nios. But > the new release of Quartus version 3 will have support for 5.0 familys > such as flex10k and max7000s (way to go Altera) according to the > Altera web page. So my guess is that there will be support for FLEX10K > and Nios in the next release. There is no limites on the number of ram > needed with Nios, as long as you have more than 2000LE's you should be > able to build a decent Nios system in any non CPLD family from Altera. > Cheers > Fredrik > benn686@hotmail.com (Ben Nguyen) wrote in message news:<e604be8.0306281332.23e027a8@posting.google.com>... > > Since Altera only sells Stratix, Cyclon, and APEX kits for their Nios, > > can Quartus II synthesize the Nios on a small (70k gates) FLEX device? > > > > Is this possible or does it require too many internal ram blocks/multipliers > > that the Flex simply doesnt have? > > > > Thanks!Article: 57460
hi: i am new to fpga.Now i have a simple question. It is said that if the data delay is less than the skew, a race condition exits.Could sb.explain it to me clearly why ?Your comment will be appreciated. BR. Black HuangArticle: 57461
I get the following warning: WARNING:NgdBuild:477 - clock net 'resetlogic_local_reset' has non-clock connections. These problematic connections include: pin clr on block resetlogic_resettimer_3 with type FDCE, pin pre on block resetlogic_resettimer_0 with type FDPE, pin pre on block resetlogic_logicreset with type FDPE, pin pre on block resetlogic_resettimer_1 with type FDPE, pin pre on block resetlogic_cpureset with type FDPE, pin pre on block resetlogic_resettimer0_1 with type FDPE, pin pre on block resetlogic_resettimer0_0 with type FDPE, pin pre on block resetlogic_resettimer_2 with type FDPE, pin pre on block resetlogic_resettimer_4 with type FDPE ... that signal is a reset signal that stays low for a few clocks then goes high. What does this message mean? the xilinx doc, is (once again | as usual | as expected ) useless at describing what it is.Article: 57462
"black" <mini_monkey@163.net> wrote in message
news:bdrg80$1007cl$1@ID-199450.news.dfncis.de...
> i am new to fpga.
This isn't an FPGA problem, it's a general digital
electronics problem.
> It is said that if the data delay is less than the skew,
> a race condition exists.
It is said truthfully.
> Could sb.explain it to me clearly why ?
Consider two D-type flipflops connected to form a simple
shift register.
(Please view in monospaced font, e.g. Courier)
>DELAY>
.---. .---.
--|D Q|-------|D Q|--
+---|> | +-|> |
| | | | | |
| '---' | '---'
| FF1 | FF2
| |
-----+--->SKEW>----+
(Schematic drawn using the completely brilliant AACircuit
program from www.tech-chat.de/AAcircuit.html )
DELAY represents the clock-to-output delay of the first
flip-flop, FF1. SKEW represents some delay in the clock
line to the second flip-flop, FF2. Now, at some clock edge,
new data will appear at the output of FF1. If SKEW is
larger than DELAY, then the clock to FF2 will happen AFTER
FF1's output has changed. So FF2 will pick up the new value
on FF1, which is wrong - it should pick up the old value
of FF1.
Of course there are some complications related to the setup
and hold time of FF2, and other detailed timing. But
that's the basic idea.
Note that this problem is related to what happens at a single
clock edge, and therefore it is unrelated to the clock
frequency. You can't fix it by running the clock slower.
This is why it's so important to use the FPGA's dedicated
clock distribution resources.
HTH
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 57463Thanks a lot for your reply,i think i am much clear now! "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:bdril6$s9v$1$8300dec7@news.demon.co.uk... > "black" <mini_monkey@163.net> wrote in message > news:bdrg80$1007cl$1@ID-199450.news.dfncis.de... > > > i am new to fpga. > > This isn't an FPGA problem, it's a general digital > electronics problem. > > > It is said that if the data delay is less than the skew, > > a race condition exists. > > It is said truthfully. > > > Could sb.explain it to me clearly why ? > > Consider two D-type flipflops connected to form a simple > shift register. > (Please view in monospaced font, e.g. Courier) > > >DELAY> > .---. .---. > --|D Q|-------|D Q|-- > +---|> | +-|> | > | | | | | | > | '---' | '---' > | FF1 | FF2 > | | > -----+--->SKEW>----+ > > (Schematic drawn using the completely brilliant AACircuit > program from www.tech-chat.de/AAcircuit.html ) > > DELAY represents the clock-to-output delay of the first > flip-flop, FF1. SKEW represents some delay in the clock > line to the second flip-flop, FF2. Now, at some clock edge, > new data will appear at the output of FF1. If SKEW is > larger than DELAY, then the clock to FF2 will happen AFTER > FF1's output has changed. So FF2 will pick up the new value > on FF1, which is wrong - it should pick up the old value > of FF1. > > Of course there are some complications related to the setup > and hold time of FF2, and other detailed timing. But > that's the basic idea. > > Note that this problem is related to what happens at a single > clock edge, and therefore it is unrelated to the clock > frequency. You can't fix it by running the clock slower. > > This is why it's so important to use the FPGA's dedicated > clock distribution resources. > > HTH > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 57464
I have an input signal that I use to clock some events in the fpga. when doing the mapping, I get this error: ERROR:MapLib:93 - Illegal LOC on symbol "pin_cpuphase2" (pad signal=pin_cpuphase2) or BUFGP symbol "pin_cpuphase2_bufgp" (output signal=pin_cpuphase2_bufgp), IPAD-IBUFG should only be LOCed to GCLKIOB site. so, apparently it wants that signal to be on a GCLKIOB; what would be the workaround to use this input as a clock without going through one of the gclkiob pin?Article: 57465
Dear All, Apologies if this is slightly off-topic but I hope there may be someone reading who has faced a similar problem. I have a prototype 33/32 PCI peripheral. The PCI bus interface is implemented in a Spartan-IIE device, which is not +5V tolerant. Design verification of the hardware is underway on this new design. I would like to make progress on software development while we wait for the hardware to be finished. To that end, I am looking for a PC-architecture motherboard into which I can plug our prototype card without blowing the Spartan-IIE device. I tried searching for suitable commodity motherboards. There are plently of boards but none of them specified that their PCI bus interfaces were 3.3V only. If anyone can suggest a suitable board I would be most grateful. Regards, Colin.Article: 57466
hi Jonathan Bromley: The reason for using FPGA's dedicated clock distribution resources is that there is no clock skew in these resources,is that right? "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:bdril6$s9v$1$8300dec7@news.demon.co.uk... > "black" <mini_monkey@163.net> wrote in message > news:bdrg80$1007cl$1@ID-199450.news.dfncis.de... > > > i am new to fpga. > > This isn't an FPGA problem, it's a general digital > electronics problem. > > > It is said that if the data delay is less than the skew, > > a race condition exists. > > It is said truthfully. > > > Could sb.explain it to me clearly why ? > > Consider two D-type flipflops connected to form a simple > shift register. > (Please view in monospaced font, e.g. Courier) > > >DELAY> > .---. .---. > --|D Q|-------|D Q|-- > +---|> | +-|> | > | | | | | | > | '---' | '---' > | FF1 | FF2 > | | > -----+--->SKEW>----+ > > (Schematic drawn using the completely brilliant AACircuit > program from www.tech-chat.de/AAcircuit.html ) > > DELAY represents the clock-to-output delay of the first > flip-flop, FF1. SKEW represents some delay in the clock > line to the second flip-flop, FF2. Now, at some clock edge, > new data will appear at the output of FF1. If SKEW is > larger than DELAY, then the clock to FF2 will happen AFTER > FF1's output has changed. So FF2 will pick up the new value > on FF1, which is wrong - it should pick up the old value > of FF1. > > Of course there are some complications related to the setup > and hold time of FF2, and other detailed timing. But > that's the basic idea. > > Note that this problem is related to what happens at a single > clock edge, and therefore it is unrelated to the clock > frequency. You can't fix it by running the clock slower. > > This is why it's so important to use the FPGA's dedicated > clock distribution resources. > > HTH > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 57467
<Marlboro> schrieb im Newsbeitrag news:ee7e56e.2@WebX.sUN8CHnE... Hi Petter, The speed is very slow, data is updated every 33 ms or so but the clock is 50 mhz, I think there would be no problem... In this case you should consider using a serial adder. Uses much less ressources. -- Regards FalkArticle: 57468
> >Again, I don't think you are reading what I am posting. In the XC3S400 > >there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs > >capable of being RAMs and SRs. How many do you really need??? That is > >56,000 bits of distributed RAM, almost a quarter as much as the block > >rams! Don't you need some LUTs to use as logic??? > > The wider address rams will require external muxing/control to > implement with only 4 LUTs/CLB usable as ram rather than 8. That is my poit of view. I donīt care (not much) of having just half of the LUTs confurable as memory (Iīve read what you wrote, Rick), but I didnīt like loosing those dual ported bigger blocks (you didnīt read carefully what I wrote). To have the same function I'll need a lot of additional logic and/or a clock two times faster. So, my DSP designs need a lot of more CLBs in Spartan3 than in Virtex2, and I'm not Ray. Luiz Carlos Oenning Martins KHOMP SolutionsArticle: 57469
DK <dknews@ueidaq.com> wrote: : Hi, All : for the new multichannel filter design I have a choice - : Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) : Xilinx part has a embedded MAC units. : I've used in a past Altera chips and they have a good tech support and free : tools. : Does any one has experience with Xilinx support? And is it possible to : obtain a free tools from Xilinx or they charge for the software? : Any other hidden issues? Don't expect the Spartan III out in the wild any soon... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57470
Thomas <tom3@protectedfromreality.com> wrote: > ERROR:MapLib:93 - Illegal LOC on symbol "pin_cpuphase2" (pad > signal=pin_cpuphase2) or BUFGP symbol "pin_cpuphase2_bufgp" (output > signal=pin_cpuphase2_bufgp), IPAD-IBUFG should only be LOCed to GCLKIOB > site. > > so, apparently it wants that signal to be on a GCLKIOB; what would be the > workaround to use this input as a clock without going through one of the > gclkiob pin? You need to use a simple IBUF instead of an IBUFG. Your synthesis tool is probably trying to be helpful. You may have to instantiate the IBUF. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57471
Peter Alfke <peter@xilinx.com> wrote in message news:3F00A341.650BCCA4@xilinx.com... > My approach would be to generate a synchronous CE (clock disable) signal > and distribute it. Now I have a synchronous signal distribution problem > that I can analyze the conventional way. If the prop delay is less than > a clock period, there is no problem. Otherwise I can resort to pipelining... > That means, you are in charge and not at the mercy of some loosely > specified asynchronous delay Peter, do you recommend using these synchronised resets with the asynch reset input of your flip-flops, or do they then become part of the synchronous inputs? Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 57472
sdatta@altera.com (Subroto Datta) wrote in message news:<ca4d800d.0306301212.1cd9be9c@posting.google.com>... > already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0306300619.58b3f8a5@posting.google.com>... > > Following PLL was generated with MegaWizard Plug In Manager and > > compiled (for Stratix) under Quartus 2.2: > > Input Frequency: 36MHz > > Dynamic reconfiguration is in use. > > c0 Clock Multiplication Factor = 158 > > c0 Clock Division Factor = 36 > > Other counters are not in use. > > The compilation report shows: > > M value = 79 > > N value = 3 > > VCO frequency = 948MHz !!!! > > It looks like Quartus design team is not aware of limitations of the > > Stratix PLL as listed in the respective datasheet (300 to 800MHz for > > -5 and -6 grades, 300 to 600MHz for -7 grade). They live under > > impression that everything up to 1000MHz is o.k. :( > The Stratix Fast PLL can go up to 1GHz for certain speedgrades, which > is why the Megawizard allows this (only the Enhanced PLL is limited to > 800Mhz). A design that needs a VCO at 1GHz will work in Stratix. The > PLL will then be placed on the Fast PLL and be used as a general > purpose PLL. However a Fast PLL cannot be used for dynamic > reconfiguration, and this should have been reported during fitting. > > For Quartus II version 3.0, the Megawizard has been enhanced to > recognize that only an Enhanced PLL can be used when dynamic > reconfiguration is selected, and as a result it will ensure that the > VCO is valid for an Enhanced PLL in the Megawizard itself. The > Megawizard will become speedgrade aware in a future release of > Quartus. In the meantime all calculations are based on the fastest > speedgrade. > > - Subroto Datta > Altera Corp. > > I don't have Quartus II version 3.0 (BTW, is it already available ?) so can't comment about it. What I do know - Quartus II version 2.2 Megawizard doesn't emit "enhanced" set of PLL parameters, so the Megawizard has no direct control of the VCO frequency. Unless it was changed in the 3.0, I can't see how improvements in the Megawizard would fix the problem. IMHO, the bug is in the compiler and it's where it should be fixed. In the mean time, the only reliable solution I can think of is: 1. Don't use the Megawizard. 2. Manually set enhanced parameters for the altpll(). It would work, of coarse, but it's a PITA... Regards, MichaelArticle: 57473
Hello,
I have written a program to run on the Celoxica RC100 board and compiled
it to edif file. When i use the Xilinx Design Manager to convert it to a bit
file,
it always fail during the mapping stage saying it cannot fit into the
device.
I have tried many optimzation method in the DK1 suite and nothing works.
Tried using its technology mapper (take very long to compiler) also cannot
work.
And it always exceed the maximum slices and 4 i/p look-up table (both exceed
by 50%). I have tried the -r option in the mapping and it still exceed.
I'm using the following software,
Celoxica DK1 Design Suite 1.1 Service Pack 1, compiler version 3.1.2676
Xilinx Design Manager Revlease version 3.3.08i, application version D.27
Thanks you
from Triax
Article: 57474"black" <mini_monkey@163.net> writes: > hi Jonathan Bromley: > The reason for using FPGA's dedicated clock distribution resources is > that there is no clock skew in these resources,is that right? There is skew even in dedicated clock lines. Because clock nets are dedicated for just for clock signals skew is much smaller and can (more easily) be accounted for in place and route. Most FPGA tools warn about gated clocks because then your skew is no longer well known parameter of global clock net but depends heavily on your design. -- Keijo Länsikunnas
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