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In article <354652A0.EDC111E@eng.sun.com>, tom karabinas <tom.karabinas@eng.sun.com> writes: > Anyone have luck doing a 150MHz design using an FPGA?? We have run Xilinx 3090-3s at 155 MHz. It wasn't a clean design but it works well enough in the lab. I think there are two areas to keep in mind - the outside/IO and the core/logic. You should be able to get most of what you need to know about the IO area from the data sheets. If you are going to be pushing that area hard, I'd suggest building a prototype board and/or playing with a demo board. The core speed depends a lot upon the nature of your problem and how much you are willing to taylor your design to match what the part can do. You can run a simple data path, say a shift register, a lot faster than a big state machine with lots of random logic that drives the router up the wall. A human may be able to taylor a state machine so that it matches what the hardware can do. The closer you get to the hardware limits the harder you will have to work to adapt your design to be nice to the hardware and/or the more hand layout and routing you will have to do. [We do all our layout by hand anyway.] You also have to pay attention to heat. -- These are my opinions, not necessarily my employers.Article: 10151
The first question that I need to ask is "What do you need to do at 150 MHz?" Most of the modern FPGAs can do _some_ things at 150 MHz using the fastest speed grade and a little human guidance. Some people, with effort, are even operating at 250 MHz and beyond. The folks at Rapid Prototypes have done DSP designs up to about 300 MHz using Xilinx XC3100A FPGAs (http://www.fpga.com/papers.htm). Peter Alfke at Xilinx claims 400 MHz operation using the fastest speed grade in an XC4002XL FPGA (http://www.xilinx.com/xcell/xl28/xl28_33.pdf). Nearly all vendors claim "we have the fastest device" but as the car companies say, "your mileage may vary." A lot depends on your application. Some--but probably not all--of the "claimed" faster devices out there include the following. You can find these companies' web sites at http://www.optimagic.com/companies.html. Xilinx (XC4000XL, XC3100A) Altera (FLEX 8000A, FLEX 10KE) Actel (SX) Lucent (ORCA 3) Vantis (VF1) QuickLogic (pASIC 3) DynaChip (DL5000, has ECL I/O that help out in I/O performance) Some other ideas on the subject: 150 MHz performance requires more work. If possible, simplify. For example, if you're working with 150 MHz serial data, bring it in and convert it to parallel data that you can manipulate at a significantly lower frequency. It will may your life easier and you'll use less logic. If your design can tolerate latency, pipeline it. In most FPGAs, the pipelining flip-flops are already inside each block. I've built pipelined adders in XC3100A devices that operate above 250 MHz, with one clock per bit latency. If you need a big wide function at 150 MHz, also consider the smaller CPLD devices. You can get 7.5 ns pin-to-pin performance and a reasonable amount of logic. There are also 5 ns devices out there from a few vendors. Watch out for the I/O characteristics. On XC3100A, the outputs start looking like sine waves when you get beyond 150 MHz. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- tom karabinas wrote in message <354652A0.EDC111E@eng.sun.com>... >Anyone have luck doing a 150MHz design using an FPGA?? > >Any suggestions on which FPGA might do the job? > >QuickLogic seems to have fast parts. Any comments on these parts? > >Thanks for your input, > >Tom > >--------------------------------------- >Tom Karabinas >ASIC Design Manager >Sun Microsystems Computer Corporation >email: tom.karabinas@eng.sun.comArticle: 10152
I'm having a bit of trouble getting the G1 step clock going on a Hotworks 6216 board. Has anybody had more success? Is there something tricky I should know about? -- Reid Porter Space Centre for Satellite Navigation Queensland University of Technology 2 George St / GPO Box 2434 Brisbane Qld 4001 Australia Email: r.porter@student.qut.edu.au Phone: +61-7-3864-2458 Fax: +61-7-3864-1361Article: 10153
Hi all,
Before purchasing XILINX FOUNDATION software I would
like to hear some user's experience on it.
1) Is SC-FND-BAS-PC protected by a hardware key, or is it
tied to particular computer via ETHERNET card number?
2) Is it useable on WindowsNT?
3) What kind of schematic entry is in Foundation?
Does it look like ORCAD? Like Viewlogic?
Is it possible to import Viewlogic schematics into FOUNDATION?
4) Are FOUNDATION schematic files binary, or text files?
(Viewlogic uses text format for schematics files).
Thanks in advance for sharing experience.
Alex Sherstuk
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/ Now offering spam-free web-based newsreading
Article: 10154I'm currently designing an ISA board for the PC. I'm using a Lattice ispLSI1016-110 for the address decode for a couple of '245 and '574 devices. Everything works fine if I hardwire the addresses of the decoded signals in the device. If however I try to get the base address from four I/O pins (so I can move the board in the PC memory map) then the chip goes silent on me - no output signals at all. I've put the output of my base address decoder onto a spare pin and it's working fine so I'm assuming that the chip is too slow. Has anyone used this chip to do something similar and if so could they provide an example. Alternatively any advice as to how to decode variable address would be appreciated (I've tried both schematic and ABEL decoders without success) JohnArticle: 10155
Scott, Well, OK, VHDL is not perfect, and the synthesis tools are probably the weak link, but they are a lot better than they used to be. I do miss the control over some critical low-level signals, (clock-enables come to mind). However, I believe that the VAST MAJORITY of errors in designs can be traced to either poor system architecture, or silly logic errors that aren't caught during verification. This is where VHDL really shines, in my opinion. The ability to simulate at the behavioural level is absolutely addictive, and I will never go back. To be able to make a change in the source code, re-compile, and see the effects in LESS THAN ONE MINUTE, even for large designs, is unbeatable for wringing out errors, and trying out different approaches, especially when coupled with a decent testbench. Granted, Altera has a functional simulation capability built into MAX PLUS, but I haven't had very good luck with it for designs of any complexity (the dreaded "nil period oscillation at 3.12 ns" message, etc.). And don't even get me started about how many nights I've spent waiting for Altera's "Linked simulation" to compile and re-compile even modest sized designs with a few test bench style components attached Being able to simulate the entire top-level behavioural description of the design in a realistic stimulus/response environment is worth dealing with the synthesis tool's idionsyncracies. I feel that the bottom line is management of complexity, and the VHDL designs that we have been creating, I think, have fewer errors, because the source code is cleaner and easier to maintain and test. Besides, the synthesis tools usually do a decent job, at least in my limited experience. We did some benchmarks on a medium size design, and found that the synthesized results compared very favorably to those obtained with schematics and AHDL. It is only now, that we are adding more stuff into our design, and getting really serious, that we are seeing the limitations (yes, the honeymoon is definitely over). To their credit, Synplicity and Exemplar are both very receptive to user feedback, and I think that by working with them, we will, as a design community, eventually, have the best of both worlds. Call me a dreamer... Tom Meagher tomm@icshou.com staylor@dspsystems.com wrote in message <6i7r75$cku$1@nnrp1.dejanews.com>... >In article <6i7cbr$68q$1@supernews.com>#1/1, > "Tom Meagher" <tomm@icshou.com> wrote: >> >> Scott, >> 100MHz makes me both jealous and depressed! I would be happy to get my >> protocol parser and TDMA dual ported RAM's to work at 25MHz (sigh). >> Individual sub-components seem to be OK, but when everything goes together >> into a 10K70 device that is much over 65% full, then look out, stuff never >> seems to fly as fast as one thinks it should... >> > >Tom, > >My off the cuff response would be that is because you are writing high level >syntax and expecting the compiler and fitter to know the difference between >critical and non-critical signals. If you have 10 inputs and only 2 are >critical, how is the compiler/fitter to know which ones are critical. > >I don't know how true it still is, but Altera used to use alphabetical >ordering. Try placing A-Z on the front of critical signal names to see if that >helps. Since symbolic names are lost early in partitioned projects, I suspect >the same is true of VHDL. In that case the names will have little or no >effect. > >VHDL to me is an improvement in the wrong direction. People want portability, >and they want performance too. I think VHDL is a long way from being able to >offer both. Pick your vendor, even if it is on a project by project basis and >write the code to fit the architecture. You will get higher performance and >more logic in a smaller lower speed grade device. Since I commonly run as fast >as the fastest speed grade will allow, I rarely have that option. While larger >devices can usually be gotten in the same speed grades, routing delays, >especially when soft buffers are inserted, make them appear slower. > >Scott Taylor - DSP Fibre Channel Systems > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10156
We have recently launched www.computalaw.com which is designed to offer ONLINE: computer contracts, support and advice to the legal and computer/IT industries worldwide. This is new type of service and we are looking for people to help us perfect it's delivery. For your help, as part of the cost of the contract, we will perform a 1 hour review of your contract or license and make amendments and advise you as appropriate. We would like anyone who is interested to contact us through our website. Michele Rennie -- Computer contracts for worldwide use with On-line contract advice and support. http://www.computalaw.comArticle: 10157
Thanks for taking time to read this. I am looking at converting to CPLD with ISP from standard individual gates. What I would like to know is, has anyone out there had any success with using a net list from PADS software to generate the JEDEC file? I have an older version of PADS and I am not sure if it is in any standard that the newer CPLD software would be able to recognize. If you know of any shareware/freeware programs that are schematic entry and will produce the desired output could you please post this information? Perhaps there are some intermediate steps that I do not know about and I would welcome that information as well. A pointer to any FAQ for this group would be most helpful. Many thanks in advance, Chip Remove the ~ from my e-mail address to reply ThanksArticle: 10158
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End of listing.
Article: 10159Hi, you can try the Actel new 54SX family, which has 16000 gate-count device available now. It features 1.4 ns EXTERNAL input data setup time and 4 ns EXTERNAL clock to output delay, without having to instantiate special I/Os, like registers in I/O. It has 3 global clock networks, one of which is hardwired and extremely high in performance, the others are for medium clock rate and are routed by place/route software automatically. please visit www.actel.com Felix K.C. CHEN Dave Hawkins wrote: > > I have an application where I want to operate on either > a 62.5MHz or 125MHz clock rate sample stream. > > I am concerned that although FPGA manufacturers quote > internal operation of counters etc at 166MHz, that packaging > parasitics may limit the I/O data rates. >Article: 10160
--------------1E07928DCB764AD7BA5F2DA2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit It probably would not be fair to share my experiences with Foundation since I work for Xilinx but since I can answer all of your questions below, so I thought I would chime in with answers to them: > 1) Is SC-FND-BAS-PC protected by a hardware key, or is it > tied to particular computer via ETHERNET card number? The schematic entry and simulation portion of the software is unlicensed. The place and route software is licensed via FLEXLM and can be "tied" to your C: drive serial number, ethernet host id, or IP Address. The synthesis portion (FPGA Express) is also licensed by FLEXLM in the same manner. > 2) Is it useable on WindowsNT? Yes. The software is tested and fully supported on Windows NT 4.0 as well as Windows 95. > 3) What kind of schematic entry is in Foundation? > Does it look like ORCAD? Like Viewlogic? > Is it possible to import Viewlogic schematics into FOUNDATION? Foundation software is actually created by Aldec and if you have seen or used Aldec's Active-CAD 3 then you have seen what Foundation looks and feels like. It is unique in respect to Viewlogic and OrCAD so it is difficult to make comparisons with those vendors software, especially about such qualitative aspects like look and feel. The best advice I have for you is to try it out. If you don't know anyone that already has the software (which I assume you don't hence the question) contact your local Xilinx or Xilinx distributor FAE and I am sure he/she will be glad to show it to you. Yes. It is possible to import existing Viewlogic Schematics. > 4) Are FOUNDATION schematic files binary, or text files? > (Viewlogic uses text format for schematics files). The actual schematic files are binary. The project initialization files and a few other files are ASCII but if you are planning to try to read or parse the actual schematic file then that would be much more difficult than the ASCII text based Viewlogic schematic, symbol and wire files. Hope this helps you out. -- Brian -- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 ------------------------------------------------------------------- --------------1E07928DCB764AD7BA5F2DA2 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <P>It probably would not be fair to share my experiences with Foundation since I work for Xilinx but since I can answer all of your questions below, so I thought I would chime in with answers to them: <BR> <BLOCKQUOTE TYPE=CITE>1) Is SC-FND-BAS-PC protected by a hardware key, or is it <BR> tied to particular computer via ETHERNET card number?</BLOCKQUOTE> The schematic entry and simulation portion of the software is unlicensed. The place and route software is licensed via FLEXLM and can be "tied" to your C: drive serial number, ethernet host id, or IP Address. The synthesis portion (FPGA Express) is also licensed by FLEXLM in the same manner. <BR> <BLOCKQUOTE TYPE=CITE>2) Is it useable on WindowsNT?</BLOCKQUOTE> Yes. The software is tested and fully supported on Windows NT 4.0 as well as Windows 95. <BR> <BLOCKQUOTE TYPE=CITE>3) What kind of schematic entry is in Foundation? <BR> Does it look like ORCAD? Like Viewlogic? <BR> Is it possible to import Viewlogic schematics into FOUNDATION?</BLOCKQUOTE> Foundation software is actually created by Aldec and if you have seen or used Aldec's Active-CAD 3 then you have seen what Foundation looks and feels like. It is unique in respect to Viewlogic and OrCAD so it is difficult to make comparisons with those vendors software, especially about such qualitative aspects like look and feel. The best advice I have for you is to try it out. If you don't know anyone that already has the software (which I assume you don't hence the question) contact your local Xilinx or Xilinx distributor FAE and I am sure he/she will be glad to show it to you. <P>Yes. It is possible to import existing Viewlogic Schematics. <BR> <BLOCKQUOTE TYPE=CITE>4) Are FOUNDATION schematic files binary, or text files? <BR> (Viewlogic uses text format for schematics files).</BLOCKQUOTE> The actual schematic files are binary. The project initialization files and a few other files are ASCII but if you are planning to try to read or parse the actual schematic file then that would be much more difficult than the ASCII text based Viewlogic schematic, symbol and wire files. <BR> <P>Hope this helps you out. <P>-- Brian <BR> <PRE>-- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -------------------------------------------------------------------</PRE> </HTML> --------------1E07928DCB764AD7BA5F2DA2--Article: 10161
Tom, Have you tried placing cliques around the critical sections of the design in the Altera MaxPlusII software? This assumes that you have a VHDL hierarchy that seperates the 25MHz clock sections from the 12.5MHz sections. Using MaxPluIIs place cliques around the sections that contain the 25MHz clock. This places a constraint during placement to hold together all logic within the clique. This can significantly improve performance by minimizing routing and programmable switching delays. A well placed design can give very high performance. A poorly placed design can NEVER give good performance. I would caution you not to use cliques on large sections of code, atleast if you ever want to see MaxPlusII finish! I place cliques on the smallest sections of code. Use cliques sparingly and wisely. Another performance "improvement" is controlling synthesis algorithms. Leonardo, for example, has several optimize passes available. Try both the standard set and the exhaustive set. Find the best synthesis pass for each section of a design. The estimated delay, area, and processing time can greatly vary using these different synthesis algorithms. A script file, defining the idea synthesis pass for each module, will significantly speed up the compile time for larger designs. Good Luck, Tom Palermo CEArticle: 10162
This is simple, safe, and it really works! For $6 (U.S), 6 stamps, and
about an hour of your time, you could earn a year's salary in a month.
Sounds to good to be true, but just imagine. WHAT IF?
A little while back, I was browsing these newsgroups, just like you are
now, and came across an article similar to this that said you could make
thousands of dollars within weeks with only an initial investment of
$6.00! So I thought, "Yeah, right, this must be a scam!" but like most
of us, I was curious. Like most of us, I kept reading. Anyway, it said
that if you send $1.00 to each of the 6 names and addresses stated in
the
article, you could make thousands in a very short period of time. You
then place your own name and address at the bottom of the list at #6,
and post the article to at least 200 newsgroups. (There are about
22,000.) or e-mail them to friends, or e-mailing lists...
No catch, that was it.
Even though the investment was a measly $6, I had three questions that
needed to be answered before I could get involved in this sort of thing.
1. IS THIS REALLY LEGAL?
I called a lawyer first. The lawyer was a little skeptical that I would
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I told him it sounded a lot like a chain letter but the details of the
system (SEE BELOW) actually made it a legitimate legal business.
2. Would the Post Office be ok with this...?
I called them: 1-800-725-2161 and they confirmed THIS IS ABSOLUTELY
LEGAL! (See Title 18,h sections 1302 NS 1341 of Postal Lottery Laws).
This clarifies the program of collecting names and addresses for a
mailing list.
3. Is this moral?
Well, everyone who sends me a buck has a good chance of getting A LOT of
money ... a much better chance than buying a lottery ticket!
So, having these questions answered, I invested EXACTLY $7.92 ... six
$1.00 bills and six 32 cent postage stamps ... and boy am I glad I did!
Within 7 days, I started getting money in the mail! I was shocked! I
still figured it would end soon, and didn't give it another thought. But
the money just continued coming in. In my first week, I made about
$20.00 to $30.00 dollars. By the end of the second week I had made a
total of $1,000.00! In the third week I had over $10,000.00 and it was
still growing. This is now my fourth week and I have made a total of
just over $42,000.00 and it's still coming in.....
It's certainly worth $6.00 and 6 stamps!
So now I'm reposting this so I can make even more money! The *ONLY*
thing stopping *ANYONE* from enriching their own bank account is pure
laziness!
It took me all of 5 MINUTES to print this out, follow the directions,
and begin posting to newsgroups. It took me a mere 45 minutes to post
to over 200 newsgroups. And for this GRAND TOTAL investment of $ 7.92
(US) and under ONE HOUR of my time, I have reaped an incredible amount
of money -- like nothing I've ever even heard of anywhere before!
'Nuff said!
Let me tell you how this works, and most importantly, why it works.
Also, make sure you print a copy of this article now, so you can get the
information off of it when you need it. The process is very simple and
consists of THREE easy steps.
============
HOW IT WORKS
============
STEP 1:
------
Get 6 separate pieces of paper and write the following on each piece of
paper:
PLEASE ADD ME TO YOUR MAILING LIST.
$1 US DOLLAR PROCESSING FEE IS ENCLOSED.
(THIS IS KEY AS THIS IS WHAT MAKES IT LEGAL SINCE YOU ARE PAYING FOR AND
LATER OFFERING A SERVICE).
Now get 6 $1.00 bills and place ONE inside EACH of the 6 pieces of paper
so the bill will not be seen through the envelope to prevent
theft/robbery.
Then, place one paper in each of the 6 envelopes and seal them. You
should now have 6 sealed envelopes, each with a piece of paper stating
the above phrase and an U.S. $1.00 bill.
Mail the 6 envelopes to the following addresses:
#1 - Ron Cooper
177 Cochrane Cres.
Ft. McMurray, Alta
T9K 1H1
Canada
#2 - Bruce Pelletier
P.O. Box 359
Gray, ME 04039
USA
#3 - Tim Chiles
P.O. Box 3003
Kodiak AK 99615
USA
#4 - Matthew Combs
12 Indiana Ave.
Blackwood, NJ, 08012
USA
#5 - Yazid Hashim
No. 47, Jalan Taman Sri Duyung,
75460 Melaka, Malaysia.
#6 –RF Sutton
27 Thames Dr.
Whitby,Ontario,
Canada L1R-2M2
STEP 2: Now take the #1 name off the list that you see above, move the
other names up (6 becomes 5, 5 becomes 4, etc.) and add YOUR Name as
number 6 on the list. (If you want to remain anonymous put a nickname,
but the address MUST be correct. It, of course, MUST contain your
country, state/district/area, zip code, etc! You wouldn't want your
money to fly away, wouldn't you?).
STEP 3: Now post your amended article to at least 200 newsgroups.
Remember that 200 postings are just a guideline. The more you post, the
more money you make!
Don't know HOW to post in the news groups? Well do exactly the
following:
------------------------------------------------------------------------
HOW TO POST TO NEWSGROUPS FAST WITH YOUR WEB BROWSER:
The fastest way to post a newsletter: Highlight and COPY (Ctrl-C) the
text of this posted message and PASTE (Ctrl-V) it into a plain text
editor (as Wordpad) and save it. After you have made the necessary
changes that are stated above, simply COPY (Ctrl-C) and PASTE (Ctrl-V)
the text into the message composition window, after selecting a
newsgroup, and post it! (Or you can attach the file, without writing
anything to the message window.)
----------------------------------------------------------------------------
--------------------
If you have Netscape Navigator 3.0 do the following:
1. Click on any newsgroup like normal, then click on 'TO NEWS'. This
will bring up a box to type a message in.
2. Leave the newsgroup box like it is, change the subject box to
something flashy, something to catch the eye, as "$$$ NEED CASH $$$?
READ HERE! $! $! $" Or "$$$! MAKE FAST CASH, YOU CAN'T LOSE! $$$". Or
you can use my subject title.
3. Now click on 'ATTACHMENTS'. Then click on 'ATTACH FILE'. Find your
file on your Hard Disk (the one you saved from the text editor). Once
you find it, click on it and then click 'OPEN' and 'OK'. You should now
see your file name in the attachments box.
4. Now click on 'SEND'/'POST'. You see? Now you just have 199 to go!
(Don't worry, it's easy and quick once you get used to it.) NOTE: All
the versions of Netscape Navigator's are similar to each other, so
you'll have no problem to do this if you don't have Netscape Navigator
3.0.
------------------------------------------------------------------------
! QUICK TIP!
(For Netscape Navigator 3.x and above)
You can post this message to many newsgroups at a time, by simply
selecting a newsgroup near the top of the screen, hold down the SHIFT,
and then select a newsgroup near the bottom of the screen. All of the
newsgroups in/between will be selected. After that, you follow/do the
basic steps, stated below at this letter, except of step #1. You can go
to the page stated below in this letter and click on a newsgroup to open
up the newsgroups window. Once you've done this, in the same window go
to 'OPTIONS', and then mark 'SHOW ALL NEWSGROUPS' and 'SHOW ALL
MESSAGES'. Now you can see all the newsgroups and you can apply easier
the above tip.
------------------------------------------------------------------------
If you have MS Internet Explorer do the following:
1. Go to the newsgroups and press 'POST AN ARTICLE'. To the new window
type your headline in the subject area and then click in the large
window below. There either PASTE your letter (which it's been copied
from the text editor), or attach the file which contains it.
2. Then click on 'SEND' or 'OK'. NOTE: All versions of MS Internet
Explorer are similar to each other, so you won't have any problem doing
this.
GENERAL NOTES ON POSTING: A nice page where you'll find all the
newsgroups if you want help is http://www.liszt.com/ (When you go to the
home page, click on the link 'Newsgroup Directory'). But I don't think
you'll have any problem posting because it's very easy once you've found
the newsgroups. All these web browsers are similar. It doesn't matter
which one you have. (But it makes it very easy if you have Netscape
Navigator 3.0 or later. You may download it from the Internet if you
don't have it.) You just have to remember the basic steps, stated below.
BASIC STEPS FOR POSTING:
1. Find a newsgroup and you click on it.
2. You click on 'POST AN/NEW ARTICLE' or 'TO NEWS' or anything else
similar to these.
3. You type your flashy headline in the subject box.
4. Now, either you attach the file containing your amended letter, or
you PASTE the letter. (You have to COPY it from the text editor, of
course, from before.)
5. Finally, you click on 'SEND' or 'POST' or 'OK', whatever is there.
------------------------------------------------------------------------
**REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU WILL
MAKE! BUT YOU HAVE TO POST A MINIMUM OF 200**
That's it! You will begin receiving money from around the world within
days! You may eventually want to rent a P.O.Box due to the large amount
of mail you receive. If you wish to stay anonymous, you can invent a
name to use, as long as the postman will deliver it.
**JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT. **
-------------------------------------------------------------------------
=================
Now the WHY part:
=================
Out of 200 postings; say I receive only 5 replies (a very low example).
So then I made $5.00 with my name at #6 on the letter. Now, each of the
5 persons who just sent me $1.00 make the MINIMUM 200 postings, each
with my name at #5 and only 5 persons respond to each of the original 5,
that is another $25.00 for me, now those 25 each make 200 MINIMUM posts
with my name at #4 and only 5 replies each, I will bring in an
additional $125.00! Now, those 125 persons turn around and post the
MINIMUM 200 with my name at #3 and only receive 5 replies each, I will
make an additional $626.00! OK, now here is the fun part, each of those
625 persons post a MINIMUM 200 letters with my name at #2 and they each
only receive 5 replies, that just made me $3,125.00! Those 3,125 persons
will all deliver this message to 200 newsgroups with my name at #1 and
if still 5 persons per 200 newsgroups react I will receive $15,625,00!
With an original investment of only $6.00! AMAZING! And as I said 5
responses is actually VERY LOW! Average are probable 20 to 30! So lets
put those figures at just 15 responses per person. Here is what you will
make:
at #6 $15.00
at #5 $225.00
at #4 $3,375.00
at #3 $50,625.00
at #2 $759,375.00
at #1 $11,390,625.00
When your name is no longer on the list, you just take the latest
posting in the newsgroups, and send out another $6.00 to names on the
list, putting your name at number 6 again. And start posting again. The
thing to remember is, do you realize that thousands of people all over
the world are joining the internet and reading these articles everyday,
JUST LIKE YOU are now!
So can you afford $6.00 and see if it really works? I think so...People
have said, "what if the plan is played out and no one sends you the
money? So what! What are the chances of that happening when there are
tons of new honest users and new honest people who are joining the
internet and newsgroups everyday and are willing to give it a try?
Estimates are at 20,000 to 50,000 new users, every day, with thousands
of those joining the actual Internet. Remember, play FAIRLY and HONESTLY
and this will work. You just have to be honest.
By the way, if you try to deceive people by posting the messages with
your name in the list and not sending the money to the rest of the
people already on the list, you will NOT get as much. Someone I talked
to knew someone who did that and he only made about $150.00, and that's
after seven or eight weeks! Then he sent the 6 $1.00 bills, people added
him to their lists, and in 4-5 weeks he had over $10k. This is the
fairest and most honest way I have ever seen to share the wealth of the
world without costing anything but our time! You also may want to buy
mailing and e-mail lists for future dollars. Make sure you print this
article out RIGHT NOW, also. Try to keep a list of everyone that sends
you money And always keep an eye on the newsgroups to make sure everyone
is playing fairly. Remember that HONESTY IS THE BEST POLICY. You don't
need to cheat the basic idea to make the money!
GOOD LUCK to all and please play fairly and reap the huge rewards from
this, which is tons of extra CASH. Please remember to declare your extra
income. Thanks once again...
=====================================================================
LEGAL? ? ? (Comments from Bob Novak who started this new version.)
"People have asked me if this is really legal. Well, it is! You are
using the Internet to advertise you business. What is that business? You
are assembling a mailing list of people who are interested in home based
computer and online business and methods of generating income at home.
Remember that people send you a small fee to be added to your mailing
list. It is legal. What will you do with your list of thousands of
names?
Compile all of them into a database and sell them as "Mailing Lists" on
the internet in a similar manner, if you wish, and make more money. How
do you think you get all the junk mail that you do? Credit card
companies, mail order, Utilities, anyone you deal with through the mail
can sell your name and address on a mailing list, unless you ask them
not to, in addition to there regular business, So, why not do the same
with the list you collect. You can find more info about "Mailing Lists"
on the internet using any search engine.
." So, build your mailing list, keep good accounts, declare the income
and pay your taxes. By doing this you prove your business intentions.
Keep an eye on the newsgroups and when the cash has stopped coming (that
means your name is no longer on the list), you just take the latest
posting at the newsgroups, send another $6.00 to the names stated on the
list, make your corrections (put your name at #6) and start posting
again.
===========================================================
NOTES:
*1. In some countries, the export of the country's exchange is illegal.
But you can get the license to do this from the post office, Explaining
the above statements (that you have an online business, etc. You may
have to pay an extra tax, but that's OK, the amount of the incoming
money is HUGE! And as I said, a few countries have that restriction.
*2. You may want to buy mailing and e-mail lists for future dollars. (Or
Database or Spreadsheet software.)
*3. If you're really not sure or still think this can't be for real,
please print a copy of this article and pass it along to someone who
really needs the money, and see what happens.
*4. You should start getting responses within 1-2 weeks.
Article: 10163In article <6i89dj$sgi$1@supernews.com>#1/1, "Tom Meagher" <tomm@icshou.com> wrote: > > However, I believe that the VAST MAJORITY of errors in designs can be traced > to either poor system architecture, or silly logic errors that aren't caught > during verification. This is where VHDL really shines, in my opinion. The > ability to simulate at the behavioural level is absolutely addictive, and I > will never go back. Tom, It is a choice. I apparently get 4x the performance with AHDL you can get with VHDL. Why not write in AHDL and simulate in VHDL? I am told it is possible. I have wanted to try it, but haven't had the need yet. I just realized this morning that my replies are also showing up in comp.vhdl. I am replying in comp.fpga. I got Steve's message via e-mail (Steve is Tom's FAE). I think Steve used to be with the inside tech support team and we worked on a few issues at one time or another. Altera seems to be very reluctant to participate in on-line discussions. Their compuserve forum had maybe 100 messages a year. Steve did point out something that I wasn't aware of, as the databook doesn't show it, that the clock enables for logic elements can be driven by one of the 4 global signals. The diagrams also give no indication of this capability. The 1998 databook on page 36 reads "The clock, clear and preset control signals on the flipflop can be driven by global signals, general purpose I/O pins, or any internal logic.". The clock enable is not included. I will have to try myself to be sure. I have my doubts. Even if the clock enable can be driven by the global signals, there are only 4 signals. I typically have a clock, output enable and reset. Those will take three. If more than one clock enable is required the reset won't be global. Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10164
In article <6i89dj$sgi$1@supernews.com>#1/1,
"Tom Meagher" <tomm@icshou.com> wrote:
>
Tom,
My previous reply has not posted yet, so I will reply to you again. I did a
test to verify what Steve Kliman said regarding using a global signal to drive
the clock enable of a logic element. Here is the original code and report
file results. I have found errors in thre report file before, but unless this
is one, don't count on being able to drive the clock enable from a global
signal. A further point against being able to drive the clock enable with
global signals is that under "ASSIGN - GLOBAL LOGIC Synthesis" The automatic
global box shows clock, clear, preset, output enable and all, but not clock
enable. I stand by my comments regarding the variable routing delays
associated with using a clock enable in a 10k series device. The 7K series is
another matter entirely. I use them there all the time. Never used a 6k or 9k
device.
Title "Global clock enable test in 10k" ;
SUBDESIGN dffe
(
ClockIn, ClockEna, A, B, C
: INPUT ;
R, S
: OUTPUT ;
)
VARIABLE
P : dffe ;
Q : dffe ;
BEGIN
P.clk = GLOBAL(ClockIn) ;
P.ena = ClockEna ;
P = A & B & C ;
R = P ;
Q.clk = GLOBAL(ClockIn) ;
Q.ena = GLOBAL(ClockEna) ;
Q = A & B & C ;
S = Q ;
END ;
-- Node name is 'P' from file "dffe.tdf" line 12, column 5
-- Equation name is 'P', location is LC1_A1, type is buried.
P = DFFE( _EQ001, GLOBAL( ClockIn), VCC, VCC, ClockEna);
_EQ001 = A & B & C;
-- Node name is 'Q' from file "dffe.tdf" line 13, column 5
-- Equation name is 'Q', location is LC3_A1, type is buried.
Q = DFFE( _EQ002, GLOBAL( ClockIn), VCC, VCC, ClockEna);
_EQ002 = A & B & C;
-- Node name is 'R' from file "dffe.tdf" line 19, column 5
-- Equation name is 'R', type is output
R = P;
-- Node name is 'S' from file "dffe.tdf" line 24, column 5
-- Equation name is 'S', type is output
S = Q;
Scott Taylor - DSP Fibre Channel Systems
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/ Now offering spam-free web-based newsreading
Article: 10165I'm new to FPGAs. I'm developing a design which should take roughly 10k gates, plus about 1500 registers. I'm considering the Xilinx 6200 for the part, but find the literature concerning the capacity of the different parts very confusing. Here's what the part data for the XC6216 says: 'Cell count:' 4096 'Typical Gate Count Range:' 16000 - 24000 From this, it looks like you can get 4-6 gates/cell. Looking at the design spec, it appears that each cell can contain only one gate, and/or a register. Is the 'typical gate count' simply marketing hype? Am I missing something obvious? The XC6264 (which as 16384 sites) is a lot more expensive than I care to use. thanks, Peter Trei ptrei@securitydynamics.com -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10166
sherstuk@amsd.com wrote: > > Hi all, > > Before purchasing XILINX FOUNDATION software I would > like to hear some user's experience on it. > > 1) Is SC-FND-BAS-PC protected by a hardware key, or is it > tied to particular computer via ETHERNET card number? > 2) Is it useable on WindowsNT? > 3) What kind of schematic entry is in Foundation? > Does it look like ORCAD? Like Viewlogic? > Is it possible to import Viewlogic schematics into FOUNDATION? > 4) Are FOUNDATION schematic files binary, or text files? > (Viewlogic uses text format for schematics files). > > Thanks in advance for sharing experience. > > Alex Sherstuk > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/ Now offering spam-free web-based newsreading Alex, 1)SC stands for support contract. The part number is DS-FND-BAS-PC. There is no hardware key with the new M1.4. It is tied to either your harddrive serial number or ethernet address. 2)It does work under Windows NT.Article: 10167
I have tried their software. In the main I like it but the schematic capture is very cluncky - workable but not nearly as easy to use as Orcad. However the price is right. And though no speed demon it is adequate for the smaller parts (on a Pentium 90). The Xilinx support is just great. Peter A. who you see here from time to time is just great at answering smart AND dumb questions. Other than the schematic capture it is a great value for the price. Simon sherstuk@amsd.com wrote: >Hi all, > > Before purchasing XILINX FOUNDATION software I would >like to hear some user's experience on it. > >1) Is SC-FND-BAS-PC protected by a hardware key, or is it > tied to particular computer via ETHERNET card number? >2) Is it useable on WindowsNT? >3) What kind of schematic entry is in Foundation? > Does it look like ORCAD? Like Viewlogic? > Is it possible to import Viewlogic schematics into FOUNDATION? >4) Are FOUNDATION schematic files binary, or text files? > (Viewlogic uses text format for schematics files). > > Thanks in advance for sharing experience. > > Alex Sherstuk > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/ Now offering spam-free web-based newsreading Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 10168
staylor@dspsystems.com wrote in message <6iag1l$87q$1@nnrp1.dejanews.com>... >In article <6i89dj$sgi$1@supernews.com>#1/1, > "Tom Meagher" <tomm@icshou.com> wrote: >> >> However, I believe that the VAST MAJORITY of errors in designs can be traced >> to either poor system architecture, or silly logic errors that aren't caught >> during verification. This is where VHDL really shines, in my opinion. The >> ability to simulate at the behavioural level is absolutely addictive, and I >> will never go back. > >Tom, > >It is a choice. I apparently get 4x the performance with AHDL you can get with >VHDL. Why not write in AHDL and simulate in VHDL? I am told it is possible. I >have wanted to try it, but haven't had the need yet. Oh come on now, Scott. Let's not do apples to oranges. The fact is, I've done several large Altera 9560 designs in AHDL/schematic mix, as well as some 10K50 designs in AHDL/schematic mix. The fact is, that the structure of the design is more important than the description medium. The following table is based on some evaluation work that we did last fall, compiling small design sub-components separately into an Altera 10K50-3. The VHDL was a direct functional translation from the original schematic/AHDL description. component | Schematics/AHDL | VHDL(Altera 8.0) | VHDL(Synplify 3.0a) ================================================================= LNK_LAYR | 243 LCs/22.02 MHz | 286 LCs/?? MHz | 206 LCs/34.36 MHz TRANSMIT | 115 LCs/113.6 MHz | 146 LCs/78.4 MHz | 125 LCs/76.33 MHz PHY_LAY3 | 313 LCs/61.34 MHz | 352 LCs/48.1 MHz | 346 LCs/49.26 MHz RECEIVE | 395 LCs/65.32 MHz | 486 LCs/35.1 MHz | 388 LCs/54.64 MHz As you can see, you don't necessarily sacrifice speed and area when you design in VHDL. Indeed, our "LNK_LAYR" component, got faster and smaller when synthesized in Synplify (Altera's VHDL compiler didn't fare so well). These comparison numbers are about as apples to apples as you can get. If you are filling up a 10K50 to the 90% level, and are able to achieve 100MHz register-to-register performance, then you probably don't have a highly interconnected architecture. Our stuff requires lots of deeply nested state machines, counters, muxes, random logic and decoding, dual ported registers and RAM's, etc. I think it is pushing the interconnect capability of the device. It is this, more than the source level description medium that is defining the bandwidth constraints. The synthesis tools comport themselves quite well, and the penalty is nowhere near 4:1. In fact, in the same way that a good optimizing C compiler can sometimes outstrip a human assembly language programmer, that can happen in VHDL too, and will increasingly do so. To return to the original point of the discussion, if only I could enforce the clock enable connections, then the performance would be quite acceptable. Synplicity and Exemplar are both looking at this issue, even as we speak, and I think that one or both of them will solve it, as they seem to be taking the issue quite seriously. In fact, the attention from this newsgroup is an incentive for them. As to your other point, I have done a lot of VHDL simulation of ".vho" files from schematic/AHDL designs, and yes, it is an immense improvement over the alternatives. In fact, I am now resurrecting a testbench composed of about 20 large EPLD's and FPGA's all in structural .vho format, and all written in schematic/VHDL source. That is where we are coming from. Pure VHDL/Verilog description is where we are headed (and there was much rejoicing). Get used to it.Article: 10169
Tom Palermo wrote in message <354bb753.702181103@news.supernews.com>... >Tom, > >Have you tried placing cliques around the critical sections of the >design in the Altera MaxPlusII software? This assumes that you have >a VHDL hierarchy that seperates the 25MHz clock sections from the >12.5MHz sections. Using MaxPluIIs place cliques around the sections >that contain the 25MHz clock. This places a constraint during >placement to hold together all logic within the clique. This can >significantly improve performance by minimizing routing and >programmable switching delays. Trying to find the nodes to clique in the EDIF file is the problem. What is the saying? "To control a demon, you must first learn his name..." Besides, Exemplar 4.2.2 places cliques into the ACF file directly by itself, and does produce pretty fast output. > > A well placed design can give very high performance. A poorly placed >design can NEVER give good performance. > >I would caution you not to use cliques on large sections of code, >atleast if you ever want to see MaxPlusII finish! I place cliques on >the smallest sections of code. Use cliques sparingly and wisely. > >Another performance "improvement" is controlling synthesis algorithms. >Leonardo, for example, has several optimize passes available. Try >both the standard set and the exhaustive set. Find the best synthesis >pass for each section of a design. The estimated delay, area, and >processing time can greatly vary using these different synthesis >algorithms. A script file, defining the idea synthesis pass for each >module, will significantly speed up the compile time for larger >designs. Yes, I think this is the key, but the cursed synthesizers still pervert the clock enables. > >Good Luck, >Tom Palermo >CEArticle: 10170
I keep my tools on a removable hard drive. Simon Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 10171
Hi All: I have heard rumours that at FCCM Xilinx mentioned it was "reducing" its support (which appeared extensive) for RC. Is this true? What does this entail? What is the future of the 6200 familiy? Why the pull back? Etc. Thanks much, BruceArticle: 10172
Isabelle Gonthier wrote: > sherstuk@amsd.com wrote: > > 1) Is SC-FND-BAS-PC protected by a hardware key, or is it > > tied to particular computer via ETHERNET card number? > 1)SC stands for support contract. The part number is > DS-FND-BAS-PC. There is no hardware key with the new M1.4. > It is > tied to either your harddrive serial number or ethernet > address. If I install the software on Machine X and later I want to move to Machine Y, do I just move the Ethernet card to Y and reload the software on Y? ThanksArticle: 10173
In article <3544B806.AF21C41B@gel.ulaval.ca>, Antoine Lecerf <lecerf00@gel.ulaval.ca> writes: > The setup time for the adress and data (on the SRAM) is 0 ns. I just need a > stable adress before I put my write enable. No, you also have to meet the address hold time at the other end of the write pulse. ----- Making delays in a Xilinx is hard if you want numbers in nanoseconds. Basically, they won't give you any data on the min delays. If it isn't in the databook, their reasoning behind that philosophy has been posted here several times - they want to be able to ship faster parts that still meet all the specs. You can get useful data on min delays though. It's just specified relative to other delays rather than in nanoseconds. There is lots of good info in their databook. Expect to read it several times. It helps if you have smart friends/co-workers to discuss it with. It's tricky to get your head used to thinking that way. Another problem with making delays is that things can easily change when you run the router again. ----- The initial question was how to make a write pulse for an SRAM. The super clean way is to use 3 cycles - setup, write, and hold. You can trim that to 2 if you can make the write pulse with the other edge of the clock - 1/2 setup, write, 1/2 hold. Or you can turn that sideways and make the write pulse on the main clock edge and change the addresses during the middle of the previous and next cycles. (That still uses two cycles to do a write.) Sometimes the second cycle can be free. Suppose, for example, that you are reading the same location before you write it. Then you can clock the address in a row of CLBs next to the IOBs and clock the write pulse in an IOB. That isn't super clean - you are now depending upon the clk-out of the IOB to be less than clk-out of a CLB plus prop time through an IOB less some slop for clock skew and fab tolerances. You can probably convince yourself this will work if you read all the fine print in the data book. The interesting case is to do a write to an arbitrary address in one clock cycle. There are two obvious approaches. You can make the write pulse during the first half of the cycle or during the second half. If you make it in the first half, you have to make sure it gets delayed long enough to meet the setup time. That is usually easy if you do something like clock the address bits in the IOBs and generate the write pulse in a CLB next to an IOB by ANDing the clock with the write-enable signal from a FF. That's a bit ugly in a 3000 part since the clock that goes to the FFs isn't easily available as a logic intput to the CLBs. [You probably want to place the critical CLB near the clock input IOB and/or manually route that signal.] You also have to make sure that the max delay on the write pulse doesn't exceed 1/2 cycle or the tail of the write pulse may still be active when the address bits are changing. One problem with that approach is that the data has to be setup early in the cycle. But that may be easy if it is also coming from the same Xilinx and can be registered with the same timing as the address info. The second approach of making the write pulse during the second half of the cycle gives (most of) another 1/2 cycle to get the write data ready. Generating a write pulse during the second half of the clock cycle requires a negative delay if you want some address hold time. That may be easy if the system architect cooperates. It's really a system or board level problem. The traditional way in old TTL chip designs was to have a preClock signal that was one gate earlier than the main clock. It would typically run through a NAND gate to get extra drive and/or to make qualified clocks. The write pulse would be made with similar logic. It would end at the same time as the main clocks ticked. The (min) clock-out time on the register holding the address turned into hold time. (Round down for clock skew and such.) You can implement a similar circuit in a Xilinx. Run the preClock signal on a long line (in 3000 terms - whatever gets low skew) next to several CLBs along an edge. Route preClock through a CLB+IOB to make the main clock. There is no logic in the CLB. It is just there to balance the timing on the write pulse. Connect the clock from that IOB over to the main clock input pin via an external trace on the PCB. You can make several copies of the clock this way by using more CLB+IOB pairs. (Don't forget to match the length of the clock traces.) Make sure the router doesn't do anything silly. You want all the interconnections to be short and have the same routing pattern. (For 3000 parts, you should be able to do (almost?) all the routing with direct connections.) To make the write pulse, use another CLB+IOB pair. Again, make sure the routing matches what the clocks are using. This time you can put a gate in the CLB to turn a write-enable signal (from a FF) into a write pulse by AND/OR-ing with preClock. With this setup, the write pulse ends at the same time the main clock ticks. You are depending upon the prop time from clock to address (probably the clk-out of the FFs in IOBs) to cover any hold time (typically 0) and skew. You may be able to get similar results with one of the magic zero-delay type PLL clock generator chips. Some of them have early outputs, or you can shift things by using different length traces on the PCB. Keep in mind that rise and fall times may be slightly different. That may shrink or expand a write pulse slightly. This may cause troubles if you need close to 1/2 cycle to meet the min write pulse width. -- These are my opinions, not necessarily my employers.Article: 10174
John,
> (...) ISA board for the PC (...)
> (...) ispLSI1016-110 (...)
> (...) the chip is too slow
Certainly doesn't look right to me !
Plain vanilla ISA is a very old and s_l_o_w_ bus, and you have
to do things real wrong to miss the data altogether !
(EISA & E-ISA were faster)
I just finished designing an ISA board with a single
Lattice 1048E-90 doing all the job (including the buffers !)
For that design, I used Mixed Abel + Schematics (the final
customer will use the very cheap Synario sold by Lattice
to do the maintainance of this design).
I guess you're playing with either this Synario, or even
the free version from the Lattice isp CD-Rom.
If so, you might zip your source files & post them.
If you're using Synario, then you might find useful
to take a look at my Web pages :
http://ourworld.compuserve.com/homepages/alse
The address decode section in my design is so trivial
that I don't think it can really help you :
" ----------------------------
MODULE ADDECOD
" ----------------------------
" ADDECOD.ABL
" (c) 1998 ALSE / Bertrand CUZEAU
"
TITLE 'I/O Address Decoder'
" --- Inputs
A9..A2 pin;
SW1,SW0 pin;
AEN pin;
" --- Outputs
CS pin istype 'com';
" --- Nodes
A1,A0 node; // dummy "nodes"
" --- Sets
Ad = [A9..A0];
X10= [.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.,.X.];
X = .X.;
" ----------------------------
Equations
" ----------------------------
[A1,A0]=0; // so we can write plain hex in the table below...
" ----------------------------
Truth_Table
" ----------------------------
([ Ad, SW1,SW0, AEN] -> CS);
[ X10, X, X, 0 ] -> 0;
[^h230, 0, 0, 1 ] -> 1;
[^h240, 0, 1, 1 ] -> 1;
[^h250, 1, 0, 1 ] -> 1;
[^h260, 1, 1, 1 ] -> 1;
END
I had no special problem, except I refrained from using signals
other than the ones really necessary. I even removed RESETDRV
(ISA signal) from my internal reset equations, and used a
"software reset" to init the chip (I built a Fifo & control logic so
a software command to reset the chip is a good idea anyway).
I did not use BALE nor AEN, just nIORD & nIOWR (I'm doing only
in the I/O space).
There are some things to know about Abel Truth tables, but my
support experience makes me guess that your problem is very
likely a very obvious one. (like signal polarity or something alike).
As often when customers ask questions, you don't say quite
enough for us to give you the right answer :
- Are you decoding in the I/O space or Memory space ?
- What Bus signals are you combining with your address decode
to obtain the final enable signal ?
- Are you doing 8 bits ISA or 16 bits ?
- Have you looked at the final reduced equations before fit ?
- Are you registering your signals ? What clock are you using ?
What reset ? etc...
Hope it helps,
Bert Cuzeau
FPGA Design Expert
Paris - France
to defeat junk mail,
remove the "y" in the following address :
AyLSE@compuserve.com
Web :
http://ourworld.compuserve.com/homepages/alse
-----------------------------------------------------------------------
John Chambers wrote <3548727B.C9D5F60B@ihr.mrc.ac.uk>...
>I'm currently designing an ISA board for the PC. I'm using a Lattice
>ispLSI1016-110 for the address decode for a couple of '245 and '574
>devices. Everything works fine if I hardwire the addresses of the
>decoded signals in the device. If however I try to get the base address
>from four I/O pins (so I can move the board in the PC memory map) then
>the chip goes silent on me - no output signals at all. I've put the
>output of my base address decoder onto a spare pin and it's working fine
>so I'm assuming that the chip is too slow.
>
>Has anyone used this chip to do something similar and if so could they
>provide an example. Alternatively any advice as to how to decode
>variable address would be appreciated (I've tried both schematic and
>ABEL decoders without success)
>
>John
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