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Hi all, When using Xilinx iMPACT to program an PROM, one has the option to enter a Usercode. Is there any way to predefine this Usercode in a .bit file or .mcs file, so that one doesn't have to enter the Usercode manually? I tried adding the option "-g UserID:48161000" to the bitgen command, but that didn't do the trick. Is there anything else one needs to do? The PROM is an xc18v02 and the FPGA is a Spartan IIE. Thanks in advance, /JerkerArticle: 72351
Can anyone point me to a tutorial or explanation of the IO standards? And how to set the default? Seems as if the synthesis tool has assigned LVCMOS25 as the default setting although I don't recall setting this standard. As my IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33? Additionally in the PACE windows under Design Object List there is a section with Groups listed. Not sure what this is for, however, I have a group listed with no ( # 0) items in the group for a symbol I recall that I deleted from the VHDL code a long time ago. How do I get rid of this old group? Thanks, BradArticle: 72352
In article <411f0666$0$306$ba620e4c@news.skynet.be>, Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote: >Hi > >> >> Not sure what you mean by "the FPGA, not the Flash yet". Can you explain? >> Does this imply that we can now use the $99 board that Xilinx is selling >> with Linux now? What limitations are implied by "not the Flash yet"? >> > >The flash is the little PROM on board, the non-volatile memory. The FPGA >need to reload its config each time it's powered. It can download it's >config from a little flash on the board (so that the board is >autonomous) and this PROM is on the JTAG chain too, but you can't >program it with this application yet. Ok, so in otherwords its merely an inconvenience, not a show stopper. > > >Personnaly, I'm now doing all my Xilinx work under Linux. good to hear. Up till now I was hesitant to buy the Spartan3 starter kit (the $99 board) because I didn't want to waste my money on something that would just sit around because I couldn't get it working under Linux. Now I'm probably goint to order it in the next few days. Thanks for your work on this! > >I use wine for the WebPack. That's sometimes a little slow when >"compiling" but that's OK. And this prog to program the bitstream. >The only thing I can't do is program the PROM. > Isn't there a free Linux version of the WebPack that only lacks the Impact programming tool? (maybe not, as I recall someone said that Xilinx used to the MainWin tool to port to Linux and MainWin requires a per/seat license). Is there a particular version of Wine that you're running the Xilinx tools under? Any special tweaks to know about? PhilArticle: 72353
I still like my feeble attempts at poetry: If your homework is too tough, and the time just flies away, thinking hard is not enough, click: comp.arch.fpga. > There you find those friendly souls, Austin, Philip, Peter, Ray filling in your knowledge holes, making problems go away. > But learning is for you to do, even if it hurts the brain. The one that has to learn is you. There's no substitute for pain. > If you want to learn design don't treat homework just as play. Real life is not benign, and you'll have to earn your pay! > sooner or later... > Peter Alfke, Xilinx Applications >Article: 72354
Has anyone managed to find the VQ100 package drawings on the Xilinx web site? It doesn't appear to be with the other package drawings, and a search of the web site turned up nothing. The VQ100 is one of the packages for the Spartan 3. Thanks, EricArticle: 72355
As far as I know, there is no way to convert schematics from Foundation 2.1i to ISE 6.2i. The one tool that imports Foundation schematics is Active-HDL from Aldec. I think that the reason is that several companies, not only Xilinx, were involved in the development of Foundation, and the schematics editor was not Xilinx' part. So I can only give the advice that others already gave - leave your schematics behind and rewrite them in a HDL. That's what I did. /JerkerArticle: 72356
http://www.xilinx.com/bvdocs/packages/vq100.pdfArticle: 72357
For the xilinx xc2c256 cpld tq-144 package, when connecting to a jtag header, according to the table in the datasheet pin 8 is Vaux(jtag supply). My question is do you need to connect the other vcc pins too, 1,37,84,etc... or is pin 8 the only one needed? On the xc9572 all vcc pin are connected together... TIAArticle: 72358
"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qh3c2mkfwr.fsf@ruckus.brouhaha.com... > Has anyone managed to find the VQ100 package drawings > on the Xilinx web site? It doesn't appear to be with > the other package drawings, and a search of the web > site turned up nothing. > > The VQ100 is one of the packages for the Spartan 3. > > Thanks, > Eric You can find the mechanical drawings for the VQ100 package at the following link. http://www.xilinx.com/bvdocs/packages/vq100.pdf Links to mechanical drawings for all the Spartan-3 packages are provided in Module 4 of the Spartan-3 data sheet, on page 22. http://www.xilinx.com/bvdocs/publications/ds099-4.pdf Module 4 also contains footprint drawings for all the available packages, showing the common footprint between the different Spartan-3 FPGAs available in that specific package. The PDF diagrams are also color coded so you can quickly see the various VCC inputs, grounds, clock pins, dedicated configuration pins, etc. See page 26 for the VQ100 footprint, which is common between the XC3S50 and the XC3S200 FPGAs. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72359
The MCS and EXO PROM file formats define only the programming of the data memory space of the PROM. Since the USERCODE value exists outside this space, it cannot be represented in a standard MCS or EXO file. The bitstream option will set the USERCODE value in the target FPGA and not the PROM. IF this is sufficient for you then you can leave the PROM USERCODE value unspecified. Another option is to allow iMPACT to automatically select and program the PROM USERCODE value as PROM data checksum (Automatically Checksum Insertion option under Edit->Preferences) Jerker Hammarberg (DST) wrote: >Hi all, > >When using Xilinx iMPACT to program an PROM, one has the option to enter a >Usercode. Is there any way to predefine this Usercode in a .bit file or .mcs >file, so that one doesn't have to enter the Usercode manually? > >I tried adding the option "-g UserID:48161000" to the bitgen command, but >that didn't do the trick. Is there anything else one needs to do? > >The PROM is an xc18v02 and the FPGA is a Spartan IIE. > >Thanks in advance, >/Jerker > > > >Article: 72360
Hi All We are currently involved in some DSP work where by we need to do further analysis on the final results. The final result is 16bits which is being captured at 48kHz. Currently I am using SignalTap and using this I'm able to capture a max of 8k samples, however this is not enough (as RAM is finite) and I was wondering is there anyway of real-time spooling this data back to PC? I'm using Nios Development Board (Cyclone FPGA) and ByteBlaster II. Pls Advice RegardsArticle: 72361
>The final result is 16bits which is being captured at 48kHz. >Currently I am using SignalTap and using this I'm able to capture a max of >8k samples, however this is not enough (as RAM is finite) and I was >wondering is there anyway of real-time spooling this data back to PC? That's 960 K bits/second. Some serial cards go that fast. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 72362
Can you guys help me where to post job for Hardware Design Engineer to be based in Shenzhen for person with FPGA experience to help development of new architecture? philip@asiapeople.com -- Regards Philip Bowden Asia People tel Hong Kong 852 22349371Article: 72363
>>The final result is 16bits which is being captured at 48kHz. >>Currently I am using SignalTap and using this I'm able to capture a max of >>8k samples, however this is not enough (as RAM is finite) and I was >>wondering is there anyway of real-time spooling this data back to PC? > > > That's 960 K bits/second. Some serial cards go that fast. > You can use the parallel port of the computer. in ECP mode. I once reached 4Mbit/sec in an PC to PC communication without using DMA. You can find my program (Delphi 3.0) when searching for FastTransfer.zip. Well, even EPP should do it (theoreticaly 2Mbps).Article: 72364
How to download USENET News **in-spite** of firewall blocks or How to circumvent firewall blocks ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [reposted as my earlier post did not show up after 8 hours. Sorry if repeated] Hi Members Forgive my intrusion into your in-box I'm working from behind a company firewall and looks like my Admin has blocked port 119 or done something to avoid me getting to any news server. All I can do for the moment is to use Google's web facility to read and post to the USENET Here's my statistics ------------------------------------------------- OS : Win XP Browsers tried : Mozilla 1.7.x, Mozilla Firefox 0.9.x Mail clients available / tried : Outlook 2003, Outlook express 5.x News readers Tried : Gravity (from SOurceforge) and OE 5 My situation ------------------------------------------------- I can - easily browse and send web mail, - read and send POP, IMAP mail, but cannot get connected to news servers (I've tried a few from Newzbot.com) I can ping yahoo from my command prompt but can't ping news servers from my command prompt I've tried to set up news servers on Mozilla and Outlook Exp newsreaders but get a time out message - I guess because of something on my firewall questions ------------------------------------------------- ****Is there a way out ??****. i.e. Is there a way to - Check which ports are blocked by my firewall - Connect to some news-server in spite of the firewall blocking - Read and post to the Usenet - I don't need binaries - are there servers that convert specific groups post to mail ? (reverse of mail2news) What should I do and where should I begin I tried a few port scanners like the free ones at http://www.grc.com/x/ne.dll?rh1dkyd2 But I suspect that they are NOT effective as I am behind a firewall Regards ........./...........Article: 72365
"Subroto Datta" <sdatta@altera.com> wrote in message news:o_3Tc.936$xT.202@newssvr15.news.prodigy.com... > You can use the free Quartus II Web Edition which has a good schematic > editor for Altera parts. The Quartus II Web Edition can be downloaded from: > > https://www.altera.com/support/software/download/altera_design/quartus_we/dn l-quartus_we.jsp > But I cannot use Xilinx chip as target - is any possible way to do it? Regard Buke > Subroto Datta > Altera Corp. > > "buke2" <cubah@tlen.pl> wrote in message > news:cfhsd0$3e6$1@atlantis.news.tpi.pl... > > The question is result of experience in designing Xilinx chip with Xilinx > > Foundation 2.1i (very old tool)and ISE6.2. > > The first have not good enough VHDL creating tool, the socond is newest > but > > schematic editor has many...many bugs!! > > > > Anybody has experience with other free GOOD schematic tools ? > > > > THX > > Buke > > > > > >Article: 72366
Gerd <gerd?NO?SPAM@rzaix530.rz.uni-leipzig.de> wrote: > that I wouldn't consider it _better_ than the PPC. In fact with the PPC, > you only loose the couple columns associated with that PPC (and you can Have to correct myself on this one. I'm not sure you'ld "loose" these columns at all - I simply haven't tried reconfiguring these columns with the PPC active. Has anybody? regards, -gArticle: 72367
Hi Michael,
I've just sent the manual of the SDRAM chip on the AFX V2P board to your
email mwd24@thompson.cl.cam.ac.uk
Hope that you can receive it (it's about 1.7M : )
Cheers,
Tyrone
"Michael Dales" <mwd24@thompson.cl.cam.ac.uk> ???
news:yqmpt5rxft7.fsf@thompson.cl.cam.ac.uk ???...
> ramntn@yahoo.com (ram) writes:
>
> > The following is the snippet of C code to test SDRAM connected to OPB
> > from MEMEC design resources.
>
> Thanks for the reply, but what I was really after was advice relating
> to the design I've implemented. I'd already implemented my own code to
> verify that either the SDRAM was failing or my design wasn't using the
> SDRAM connectly. What I'm trying to understand if *why* the SDRAM
> isn't working, despite having done everything the documentation
> suggests (to the best of my knowledge).
>
> The design practically left everything up to the base system builder,
> and the only thing I did was correct the pin definitions in the UCF
> board, and ensure that I was using the correct oscillator socket, and
> that the DRAM enable pin was set corrently.
>
> I'm told that SDRAM chips are very sensitive to the clock they're
> given, and that if it says it is to be clocked at a specific frequency
> it really means that. I failed to find appropriate documentation for
> the SDRAM chip on the AFX board we have - the URL in the board
> documentation is no longer valid, and searching the web site the for
> the makings on the chip (1QE42 ZVCGC) didn't turn up anything either.
>
> >
> > // Type casting
> > unsigned int* sdram_location = (unsigned int *) XPAR_SDRAM1_BASEADDR;
> > int sdram_data_read, sdram_data_read_error;
> > unsigned int* temp;
> >
> > //Store values
> > temp = sdram_location;
> > for (loop_count = 0; loop_count < 4194304; loop_count++) {
> > *sdram_location = loop_count;
> > sdram_location++;
> > }
> >
> > //Retrieve values
> > sdram_location = temp;
> > for (loop_count = 0; loop_count < 4194304; loop_count++) {
> > sdram_data_read = *sdram_location;
> >
> > if (sdram_data_read != loop_count) {
> > printf_uart(" SDRAM Test Failed\n\r");
> > loop_count = 4194305;
>
> Whoever wrote this code needs to be introduced to the C keyword
> "break" :)
>
> > }
> > else {
> > sdram_location++;
> > }
> > }
> >
> > hope this helps
> > Ram
>
> Cheers,
>
> --
> Michael Dales
> University of Cambridge Computer Laboratory
> http://www.cl.cam.ac.uk/~mwd24/
Article: 72368Hi, Select any pin under "Design Object List - I/O Pin" window in PACE and then right-click. You'd then get an option to set the I/O standard for that pin. You can do the same by selecting multiple signals. Narasimha. "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i1rel5f76hm67@corp.supernews.com>... > Can anyone point me to a tutorial or explanation of the IO standards? And > how to set the default? Seems as if the synthesis tool has assigned LVCMOS25 > as the default setting although I don't recall setting this standard. As my > IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33? > > Additionally in the PACE windows under Design Object List there is a section > with Groups listed. Not sure what this is for, however, I have a group > listed with no ( # 0) items in the group for a symbol I recall that I > deleted from the VHDL code a long time ago. How do I get rid of this old > group? > > Thanks, > > BradArticle: 72369
Thank you, that's what I needed to know! /Jerker "Neil Glenn Jacobson" <n.e.i.l.j.a.c.o.b.s.o.n@x.i.l.i.n.x.c.o.m> skrev i meddelandet news:412151E2.9050306@x.i.l.i.n.x.c.o.m... > The MCS and EXO PROM file formats define only the programming of the > data memory space of the PROM. Since the USERCODE value exists outside > this space, it cannot be represented in a standard MCS or EXO file. > > The bitstream option will set the USERCODE value in the target FPGA and > not the PROM. IF this is sufficient for you then you can leave the PROM > USERCODE value unspecified. Another option is to allow iMPACT to > automatically select and program the PROM USERCODE value as PROM data > checksum (Automatically Checksum Insertion option under Edit->Preferences)Article: 72370
Gerd wrote: > First, don't use bus macros unless really necessary. For what you > describe here, directed routing combined with a few placement constraints > is probably an easier and more reliable solution than bus macros. Directed routing requires FPGA Editor, which I think has an Anti-Sean-mode built in, no matter if I try to draw bus macros or directed routing. :) > Depends on the size of your module. You could put it on the right hand > side of the PPC - on a 2vp7, you can get about 1000..1200 slices there > (with space left for cross-routing - read on). Right, but that wasn't enough in my case, so that wasn't an option... > If you put it in the middle, you obviously have pretty much as many > slices as you want, within the limits of the chosen device of cause. > Now, there is a very simple trick to getting around of having to > build all those bus macros: divide the reconfigurable frames into > parts for your module, and parts reserved for cross-routing. How do you do that? Constrain the logic specifically to an area inside the module? And how do you prevent the tools from routing where they shouldn't? > Fair enough. But unless you specially design a board for reconfigurable > applications, you'll most likely always end up having cross-routing in > one way or another. Exactly. But as long as it's not dozens of signals, it's not really a problem. > [ICAP at higher frequencies] > Well, who says you can't? Just watch the BUSY signal. Of course I can watch the BUSY signal, but still noone has been able to tell me *WHY* that should even be necessary if the clock I use is less than the maximum 50/66MHz I can use for SelectMAP without handshaking. It's not a problem per se, but "back in the days" it took me while to find the little tiny footnote in one of the appnotes stating the fact... > Well, yes and no. I have multiple modules on top of each other working, > 'on top' like SLICE_XiY8:SLICE_XjY31 and SLICE_XiY40:SLICE_XjY71 for > example. They can be reconfigured without interference - as long as > you don't have SRL16s and LUT-RAMs in the columns, of cause. ... which again restricts you in what you can do with it... But how do you create a partial bitstream for a module spanning only half the height? In Virtex-I-days you could just "cut frames in half" and put them back together pretty much every way you wanted to, so that wasn't a problem, but how do you do that in a Virtex II-Pro? I was thinking along the lines of building modules-inside-modules, and then keeping e.g. the lower "sub-module" static while changing the upper part. But when I tried it the tools didn't support that. Might be different now, I just don't have to time to try that any more. > That's not exactly true, either. Of cause one has to look a bit harder > for this information, but it is actually contained to some degree in > the EDK6.2 icap drivers, and there is quite some information strewn > across various appnotes and answer records as well. No single source > covers it all, though - agreed. Well, when I worked at this kind of thing, there was no EDK6.2... part of my job was to design sort of an OPB_hwicap, which became pretty useless just about when I was done, because EDK6 came out. That was some time well-spent. ;) > It should be faster than that, with a bit of XDL hacking :) Didn't they stop developing XDL after ISE5? I tried it a couple of times with ISE6, and got a warning about it not supporting some of the device-specific properties, so that's where I decided to stop. I imagine you could do some really fun stuff with XDL, but only if you have the time to really get into it, which I don't... > Real life as in space applications - check out Carl Carmichaels papers > about irradiation testing, there is a note about in-situ repair using > partial reconfiguration (although to be really useful here requires a > bit harsher environments than simple space). SEU-correction was something I looked into when researching that, but at the time it all seemed more or less theoretical... there were a lot of papers where this and that was suggested and planned, but none of it (except some Xilinx Appnotes based on older architectures) was actually implemented and working, at least not on a Virtex II-Pro. Virtex I and II are different stories... And another problem is detecting the SEUs in the first place, since you can't just read back whatever you want to without the risk of locking up the PPC or corrupting your design. Ray Andraka wrote something about this awhile back, but I can't find the link right now... > Some people supposedly use genetic algorithms to program FPGAs and > using partial reconfiguration can signifcantly speed up this process > (and the evaluation of the results). In what way? The process of creating a new design should be what takes up most of the time... in all the papers I read on this subject, it either involved generating HDL-code and feeding that to the regular design tools, or using something like JBits. Either way, evolving a new generation takes quite a lot of time, and I can't imagine the few ms to load that into the FPGA to be of any significance... unless you have really huge FPGAs and a really fast way to create new designs (i.e. not using the tools from Xilinx, but manipulating the bits yourself, which still doesn't seem feasible to me with a Virtex II-Pro). What really would be interesting is do have the PPC do the genetic algorithm, and reconfigure the FPGA it sits on, giving you a black box that adapts to its environment, all on one chip. That could be fun, but doesn't seem possible at the moment... > There are also several useful applications which 'only' require the > reconfiguration of routing, though I guess I shouldn't go into any > details about these. That's one I looked into as well... interesting for all sorts of image or audio processing... just put the building blocks inside the FPGA and connect them whichever way you want to create whatever algorithm you need, without disrupting other channels. Same for network processing... Kind of like a higher-level FPGA, that offers you FFT and whatnot as a "primitive"... use the thing as a coprocessor that serves just your computational needs, whatever they might be... And the reconfiguring of routing should be extremely fast, compared to reconfiguring modules... > Oh and if you happen to be on FPL in two weeks, maybe there will be > a presentation of a simple case of the 'on top' modules. It could be > arranged, anyway. Even though it still interests me, I'm pretty much done with partial reconfiguration... The whole thing was my master's thesis, and that's done and over with. Now that I'm not in research anymore (or at least not primarily), I don't have the time or the application for partial reconfiguration anymore... cu, SeanArticle: 72371
I have a new cache. Researched it as best as possible and it appears to be new. Anyone interested? Address matching in less than 10% overhead of the cache RAM size in implementation for any size. Not really interested in developing it myself. Useful for gigahertz CPUs, missiles, supercomputers, mobile phones, graphics cards, encryption, compression, and so on. One or two months to modify vhdl of a 6502 or something like that to see it working, and then tape it out as fast as your legs can carry. Its 2 or 3 pages to describe it in full in English. One hour to do a presentation. I'm interested in serious proposal.Article: 72372
Sean Durkin <smd@despammed.com> wrote: > How do you do that? Constrain the logic specifically to an area inside > the module? And how do you prevent the tools from routing where they > shouldn't? Creative use of area constraints in combination with apropriate levels of design hierarchy. area_group module_all range=....; inst module_0/* area_group=module_all; area_group module_sub1 range=....; inst module_0/sub1/* area_group=module_sub1; inst module_0/sub1/ff_0 loc=...; .. that's the general idea. As for the tools and routing: you don't. Leave a buffer zone between your modules and any adjacent logic. If you can't for whatever reason, use a bit of fpga_editor tweaking to get all signals within the boundaries of your module, but you really want that buffer zone. > > [ICAP at higher frequencies] > > Well, who says you can't? Just watch the BUSY signal. > Of course I can watch the BUSY signal, but still noone has been able to > tell me *WHY* that should even be necessary if the clock I use is less > than the maximum 50/66MHz I can use for SelectMAP without handshaking. > It's not a problem per se, but "back in the days" it took me while to > find the little tiny footnote in one of the appnotes stating the fact... The footnote probably only says that the ICAP is 'specified' to 33 MHz, or something like this, right? Well, I say don't worry about it. Go with whathever you'ld use with SelectMAP, and keep an eye on the busy line. OTOH, why would you want to exceed 33 MHz anyway? There's not much you gain from going beyond that. > > Well, yes and no. I have multiple modules on top of each other working, > > 'on top' like SLICE_XiY8:SLICE_XjY31 and SLICE_XiY40:SLICE_XjY71 for > > example. They can be reconfigured without interference - as long as > > you don't have SRL16s and LUT-RAMs in the columns, of cause. > ... which again restricts you in what you can do with it... Well, the issue with SRL16s and LUT-RAMs is a general problem with active reconfiguration and certainly beyond the scope of this thread. > But how do you create a partial bitstream for a module spanning only > half the height? In Virtex-I-days you could just "cut frames in half" > and put them back together pretty much every way you wanted to, so that > wasn't a problem, but how do you do that in a Virtex II-Pro? I was 1) you can still do it the same way, cutting portions of the frames and piecing them back together. Worked fine for me, at least, and dynamically as well (that is: no .bit files involved at all). 2) if you don't feel like cutting bits and bytes, go with XDL, or synthesize/map/par all possible combinations. Lot's of work, but has been done for small numbers of modules, by people without any knowledge of, or consideration for, bitstream details. > thinking along the lines of building modules-inside-modules, and then > keeping e.g. the lower "sub-module" static while changing the upper > part. But when I tried it the tools didn't support that. Might be > different now, I just don't have to time to try that any more. Except for XDL and the 'all combinations' approach, the tools won't help you with that, correct. Any piece of software (or hardware) that gives you access to raw configuration frames will help you (and there are several of those, some indeed included in EDK 6.2, others in JBits, still others... well, somewhere else). > > It should be faster than that, with a bit of XDL hacking :) > Didn't they stop developing XDL after ISE5? I tried it a couple of times > with ISE6, and got a warning about it not supporting some of the > device-specific properties, so that's where I decided to stop. Supposedly it's being abandoned soon, or so the rumors say. I know it's being successfully used on v2pro, regardless of the warnings. > SEU-correction was something I looked into when researching that, but at > the time it all seemed more or less theoretical... there were a lot of > papers where this and that was suggested and planned, but none of it > (except some Xilinx Appnotes based on older architectures) was actually > implemented and working, at least not on a Virtex II-Pro. Virtex I and > II are different stories... About V2Pro, ask me again in 10 days :) > And another problem is detecting the SEUs in the first place, since you > can't just read back whatever you want to without the risk of locking up > the PPC or corrupting your design. Ray Andraka wrote something about > this awhile back, but I can't find the link right now... SRL16s and LUT-RAMs again, yes. Just replace them with normal FF-based aequivalents, and you should be fine (not sure about the PPC, so far). > > [genetic algorithms] > In what way? The process of creating a new design should be what takes [...] The guy I talked to created bitstreams directly without the tools. Which is where the speed of reconfiguration and recovery of results matter. > What really would be interesting is do have the PPC do the genetic > algorithm, and reconfigure the FPGA it sits on, giving you a black box > that adapts to its environment, all on one chip. That could be fun, but > doesn't seem possible at the moment... It is possible. Use a device >= 2vp7, with opb_hwicap, opb_ethernet and Linux running on it and have fun. The 7 is a bit crowded, but starting with a 2vp20 you should have plenty of free area. regards, -gArticle: 72373
Hi, Refer to.... http://www1.idt.com/pcms/tempDocs/AN_230.pdf It gives a fairly good introduction to different I/O standards. Narasimha. "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i1rel5f76hm67@corp.supernews.com>... > Can anyone point me to a tutorial or explanation of the IO standards? And > how to set the default? Seems as if the synthesis tool has assigned LVCMOS25 > as the default setting although I don't recall setting this standard. As my > IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33? > > Additionally in the PACE windows under Design Object List there is a section > with Groups listed. Not sure what this is for, however, I have a group > listed with no ( # 0) items in the group for a symbol I recall that I > deleted from the VHDL code a long time ago. How do I get rid of this old > group? > > Thanks, > > BradArticle: 72374
Gerd wrote: > As for the tools and routing: you don't. Leave a buffer zone between > your modules and any adjacent logic. If you can't for whatever reason, > use a bit of fpga_editor tweaking to get all signals within the > boundaries of your module, but you really want that buffer zone. Ah, the "let's try and hope for the best"-approach. :) > The footnote probably only says that the ICAP is 'specified' to 33 MHz, > or something like this, right? Yes... but at frequencies higher than about 38MHz (that's what I tested in my particular case) it gives you invalid data, so 33MHz seems to be a reasonable, if somewhat conservative limit. > Well, I say don't worry about it. Go with > whathever you'ld use with SelectMAP, and keep an eye on the busy line. > OTOH, why would you want to exceed 33 MHz anyway? There's not much you > gain from going beyond that. It's not about speed, it's about keeping it simple. If I have a bus clock of 50MHz, and ICAP supposedly works up to 66MHz like SelectMAP, why should I even bother with watching the BUSY-signal? The thought never even crossed my mind until I ended up with strange data when reading back and with not-working designs after reconfiguration... ICAP not being able to handle that speed just was about the last place I looked when implementing this... and it didn't show up in xapp661 (or 662 or 660, can't remember which one) until AFTER I found out about it... then they released a new revision with that little footnote in it... > 1) you can still do it the same way, cutting portions of the frames > and piecing them back together. Worked fine for me, at least, and > dynamically as well (that is: no .bit files involved at all). Sounds good... never dared to try that, though (because of all the warnings about the possibility of frying the thing when you download invalid bitstreams), and didn't have the time to. > Supposedly it's being abandoned soon, or so the rumors say. I know > it's being successfully used on v2pro, regardless of the warnings. Good to know, should I ever decide to to dive into the subject again. :) > SRL16s and LUT-RAMs again, yes. Just replace them with normal FF-based > aequivalents, and you should be fine (not sure about the PPC, so far). BRAMs are a problem, too, especially when they contain the program you run on your PPC. When you read back BRAM contents, the instruction fetches can get corrupted, causing your program to hang or behave abnormally, like exiting loops after a more or less random number of cycles and such. That gave me some headaches as well... > It is possible. Use a device >= 2vp7, with opb_hwicap, opb_ethernet > and Linux running on it and have fun. The 7 is a bit crowded, but > starting with a 2vp20 you should have plenty of free area. Maybe, if you have the corresponding hardware. :) Anyway, good to get some feedback on this, some new ideas... now if I only had the time... :) cu, Sean
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