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Messages from 44725

Article: 44725
Subject: Re: VIRTEX II DCM Question
From: kayrock66@yahoo.com (Jay)
Date: 27 Jun 2002 22:07:37 -0700
Links: << >>  << T >>  << A >>
Yes, you will be able to get the phase relationship you desire using 2
DCMs.  The whole point of the feedback control system is that it
doesn't matter what the particular route is from the DCM to the output
pin, it gets servoed out when the DCMs are locking.  The burden is
shifted to the consistency of the feedback path.

Regards

"Bill" <not@home.com> wrote in message news:<3d1b73b4_6@news.uncensored-news.com>...
> Hi,
> 
> I need to use some DCM's for clocks which are external to the virtex II
> chip.   I need to output the 0 and 180 (two output pins worth).   My
> question is this:   Will I be able to keep an exact 180 degree period after
> routing, or does the routing cause delays such that the true signals might
> be different by several degrees?
> 
> Thanks,
> 
> Bill
> 
> 
> 
> ______________________________________________________________________
> Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
>       <><><><><><><>   The Worlds Uncensored News Source   <><><><><><><><>

Article: 44726
Subject: Re: 5V tolerance
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 28 Jun 2002 06:05:39 GMT
Links: << >>  << T >>  << A >>
On Thu, 27 Jun 2002 15:36:11 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>Peter Alfke wrote:
>> 
>> rickman wrote:
>> 
>> > I think people have misunderstandings of how the Xilinx software is
>> > licensed.  I am pretty sure I have read in this newsgroup postings from
>> > Xilinx representatives that the Xilinx software will continue to operate
>> > after the license has run out.  Only the support is ended.
>> 
>> That is correct.
>> The expiration of the software is only in the wording of the license agreement.
>> 
>> There is *no* physical licensing mechanism that might prevent a user from
>> continuing to maintain existing designs in the indefinite future, as long as
>> you need it, as long as you want. No problem!
>> 
>> Peter Alfke, Xilinx Applications
>
>
>I don't mean to offend you or anyone else at Xilinx, but this is a
>pretty silly licensing scheme.  Does anyone at Xilinx have an
>explanation for why they word the license this way?  How does this
>benefit Xilinx?  Support has always been optional at extra charge after
>the first year.  Heck, with some EDA vendors, support is optional the
>FIRST year!  So what motivated Xilinx to "word" the license for time
>limited rights? 

I think it is a legal liability issue. If they license it for one year
only, you can't come back sue them 5 years later. The same logic
applies to versions. I don't think you can even pay to get a license
for an earlier version so they can't be legally liable for not
supporting old versions indefinitely. IOW, if you don't upgrade to the
latest version and if it stops working for any reason, you're on your
own. It is a sensible position for Xilinx IMO, but doesn't help us
poor schmucks who have to support an existing design for more than a
year.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 44727
Subject: Re: VIRTEX II DCM Question
From: Peter Alfke <palfke@earthlink.net>
Date: Fri, 28 Jun 2002 06:17:46 GMT
Links: << >>  << T >>  << A >>
You don't need two DCMs, one is enough. It generates the two phases (0 and 180 ) with
as good a precision as is possible ( 50 ps resolution). Then you can route these
signals on two glabal clocks.
Thiis more accurate than doing local inversion in ths I/O.

Peter Alfke, Xilinx Applications
========================
Jay wrote:

> Yes, you will be able to get the phase relationship you desire using 2
> DCMs.  The whole point of the feedback control system is that it
> doesn't matter what the particular route is from the DCM to the output
> pin, it gets servoed out when the DCMs are locking.  The burden is
> shifted to the consistency of the feedback path.
>
> Regards
>
> "Bill" <not@home.com> wrote in message news:<3d1b73b4_6@news.uncensored-news.com>...
> > Hi,
> >
> > I need to use some DCM's for clocks which are external to the virtex II
> > chip.   I need to output the 0 and 180 (two output pins worth).   My
> > question is this:   Will I be able to keep an exact 180 degree period after
> > routing, or does the routing cause delays such that the true signals might
> > be different by several degrees?
> >
> > Thanks,
> >
> > Bill
> >
> >
> >
> > ______________________________________________________________________
> > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
> >       <><><><><><><>   The Worlds Uncensored News Source   <><><><><><><><>


Article: 44728
Subject: variable decimation filter with rational sampling factors
From: "Dirk Sütterlin @ newsgroups" <dsuetterlin.newsgroup@gmx.net>
Date: Fri, 28 Jun 2002 13:15:59 +0200
Links: << >>  << T >>  << A >>
Hi,
following problem: I have to design a FIR filter which changes the incoming
sample rate into an ouput sample rate by a rational sampling factor. The
sampling factor shall be changed on the fly. There is some time (10us) to
adjust the new sampling factor before a new sample block has to be filtered.
Incoming sampling rate is about 40Mhz, outgoing sampling rate is 8...32MHz.
Question: Which architecture is preferable for such an filter? I studied
some polyphase architectures, but it seems to me, that this kind of filter
is preferable for a fixed sample rate converter. Has anybody a hint for me,
how to built an adjustable sample rate converter?

Many thanks

Dirk




Article: 44729
Subject: Re: variable decimation filter with rational sampling factors
From: Ray Andraka <ray@andraka.com>
Date: Fri, 28 Jun 2002 12:52:19 GMT
Links: << >>  << T >>  << A >>
A polyphase resampler is the way to do it...no need to be computing terms you
don't need.  THe filter structure is going to be dependent on how many ratios
and exactly what they are.  To some degree the number of taps in your model
filter is also going to affect implementation.  If the rates have a common
denominator, for example 1/5, 2/5, 3/5, 5/5, then it is fairly easy to use fixed
filter banks with reloaded coefficients and an add/mux structure on the back
end  (We did one that did exactly that and were able to use distributed
arithmetic filter banks).  You can also cascade two or more sections that each
have a common denominator.  The advantage to doing this is that the distributed
arithmetic makes for a very compact filter and you don't get the internal
rounding/truncation errors you get with a traditional MAC approach.

If that proves to be too complicated, the other option is to use one or more
multiply=accumulates (MACs) and pull the coefficients out of block RAM in the
sequence you need.  Changing rates in this case is simply a matter of changing
the addressing to the block RAM and altering the timing to the accumulator.  The
state machine can get hairy if you are not clever in the design.  When designing
the sequencer thing in terms of general filtering rather than your specific
ratios.  The number of MACs needed depends on your sample rate.  One helpful
note as far as the accumulator goes:  YOu can use a single accumulator per MAC
and introduce a delay in the feedback equal to the number of branches that MAC
handles so that the branches are serviced in sequence.  Changing the number of
branches serviced by that MAC is then a matter of adjusting the feedback delay
(SRL16's are great for that) and the stride of the coefficient address counter.

Best of luck.



"Dirk Sütterlin @ newsgroups" wrote:

> Hi,
> following problem: I have to design a FIR filter which changes the incoming
> sample rate into an ouput sample rate by a rational sampling factor. The
> sampling factor shall be changed on the fly. There is some time (10us) to
> adjust the new sampling factor before a new sample block has to be filtered.
> Incoming sampling rate is about 40Mhz, outgoing sampling rate is 8...32MHz.
> Question: Which architecture is preferable for such an filter? I studied
> some polyphase architectures, but it seems to me, that this kind of filter
> is preferable for a fixed sample rate converter. Has anybody a hint for me,
> how to built an adjustable sample rate converter?
>
> Many thanks
>
> Dirk

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44730
Subject: Re: Multiple XC_PROPS attributes
From: francoischoquette@hotmail.com (Francois Choquette)
Date: 28 Jun 2002 06:39:52 -0700
Links: << >>  << T >>  << A >>
Ok, a co-worker found a solution.  To use two XC_PROPS on a same net
name, you must append the second attribute under the value field,
separated by a comma e.g.

instance   databus_fpga*   xc_props   maxdelay=1.8ns, maxskew=0.2ns


Francois Choquette


francoischoquette@hotmail.com (Francois Choquette) wrote in message news:<e93e26d6.0206261643.53b94e0c@posting.google.com>...
> Using the SCOPE Editor of Synplify Pro 7.1, I can't use two XC_PROPS
> attributes for the same net e.g. :
> 
> instance databus_fpga* xc_props maxdelay=1.8ns
> instance databus_fpga* xc_props maxskew=0.2ns
> 
> The EDF netlist contains only the last attribute, in this example, the
> maxskew attribute.
> 
> If I edit the UCF and add the two constraints, the PAR process will
> use these two attributes.
> 
> Anyone have an idea on how to tell Synplify to use multiple
> constraints for a same net?  Thanks!

Article: 44731
Subject: Re: blank CPLD
From: "M. Randelzhofer" <mrandelzhofer@uumail.de>
Date: Fri, 28 Jun 2002 16:20:56 +0200
Links: << >>  << T >>  << A >>
Depends on the manufacturer.
Xilinx 95xx have pullups in the programming state which is default on new
devices.
Xilinx recommends to switch off any clocks or fast signals on any pin for
programming the device.
In practice this seems to be necessary only for already programmed parts or
very full parts.
So take care in your XC95xx designs if you use a free running clock and
consider switching off the clock oscillator with an output enable for device
programming.

MIKE


"Minlin Fan" <minlinf@hotmail.com> schrieb im Newsbeitrag
news:3d1ad654$0$27308$afc38c87@news.easynet.co.uk...
> Hi all,
>
> Before being programmed, will a blank CPLD affect the rest of the circuit
on
> a board? What status are all the pins with such a blank CPLD?
>
> Cheers.
> Minlin
>
>



Article: 44732
Subject: Re: Silly questions about configuring Spartan 2's
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 28 Jun 2002 16:46:48 +0200
Links: << >>  << T >>  << A >>

"John Larkin" <John@0.com> schrieb im Newsbeitrag
news:4tpnhu0urd0eab0hat7a90ql78d95vg6fs@4ax.com...

> OK so far. So, if we cut over to the ISE software and use a Spartan2,
> does this all still work? I looked over the S2 config app notes, and
> they seem immensely complex. Does the RBT file contain the entire
> serial bit stream we need, commands and all, just like in the good old
> days?

You are on the right way. Configuration of Spartan-II is even easier than
4K. Just pull PROG low (>300ns), wait for >100us or INIT going HIGH (open
drain), then start shifting in data. After all bit have been shifted in,
apply additional 6 clock cycles for power up. Thats all.

--
MfG
Falk





Article: 44733
Subject: Re: VIRTEX II DCM Question
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Jun 2002 09:14:45 -0700
Links: << >>  << T >>  << A >>
Here is an even better answer from one of the Xilinx experts ( who wants to remain
anonymous...)

I think the best thing to do is :

CLK--+--DCM-----BUFG---internal clock
     |
     +--DCM-----BUFG---to FDDRRSE primitive(s)

The top DCM and BUFG are used for the internal clock. The bottom DCM
and BUFG are used to drive FDDRRSE primitives. Each BUFG feeds back
to it's own DCM. The bottom BUFG can also then be phase-adjusted to
move the clock where he needs it. By connecting the D0 and D1 inputs
to the FDDRRSE primitives to VCC and GND (or vice-versa), you will
get an exact copy of the clock, or it's inverse (180 degree phase
shift). Of course, there will be the clock-to-out delay of the IOB
DDR flop, but that can be adjusted/corrected with the phase shift
of the bottom DCM that drives these IOB flops.

There will be a slightly better duty cycle if two BUFGs are used
with the bottom DCM -- one for CLK0 and one for CLK180 vs. the
single BUFG method that I described above.







Peter Alfke wrote:

> You don't need two DCMs, one is enough. It generates the two phases (0 and 180 ) with
> as good a precision as is possible ( 50 ps resolution). Then you can route these
> signals on two glabal clocks.
> Thiis more accurate than doing local inversion in ths I/O.
>
> Peter Alfke, Xilinx Applications
> ========================
> J


Article: 44734
Subject: Problem: Designing for older FPGAs
From: "David Langmann" <david@dalSPAMNOTanco.com>
Date: Fri, 28 Jun 2002 12:44:30 -0400
Links: << >>  << T >>  << A >>

Hi,

We've been selling a Virtex 1 based board (eg:XCV50) for a few years. At one
time, customers who wanted to do their own designs could buy the design
software for this chip rather cheaply. The basic Foundation was $500 if I
recall, and there was a Students' edition for university users.

Right now there is Webpack, which does not support the older chips, and the
full Foundation which does, but which at $2495 is probably beyond many
budgets.

So my question is:
Can one start a design in Webpack (on the customer's computer) , and then
transfer the design output to Foundation (on my PC) for implementation?

If so, any pointers as to how this would be done ?

Thanks very much,

David L.



Article: 44735
Subject: Re: Problem: Designing for older FPGAs
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 28 Jun 2002 20:00:24 +0200
Links: << >>  << T >>  << A >>
"David Langmann" <david@dalSPAMNOTanco.com> schrieb im Newsbeitrag
news:uhp3ri8ek4jv22@corp.supernews.com...
>
> Hi,
>
> We've been selling a Virtex 1 based board (eg:XCV50) for a few years. At
one
> time, customers who wanted to do their own designs could buy the design
> software for this chip rather cheaply. The basic Foundation was $500 if I
> recall, and there was a Students' edition for university users.
>
> Right now there is Webpack, which does not support the older chips, and
the
> full Foundation which does, but which at $2495 is probably beyond many
> budgets.
>
> So my question is:
> Can one start a design in Webpack (on the customer's computer) , and then
> transfer the design output to Foundation (on my PC) for implementation?

Yes. But why not change the Virtex into a Spartan-II? They are AFAIK pin and
bitstream compatible.
And Spartan-II is well supported by Webpack.

--
MfG
Falk







Article: 44736
Subject: Re: Silly questions about configuring Spartan 2's
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 28 Jun 2002 14:02:34 -0400
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> "John Larkin" <John@0.com> schrieb im Newsbeitrag
> news:4tpnhu0urd0eab0hat7a90ql78d95vg6fs@4ax.com...
> 
> > OK so far. So, if we cut over to the ISE software and use a Spartan2,
> > does this all still work? I looked over the S2 config app notes, and
> > they seem immensely complex. Does the RBT file contain the entire
> > serial bit stream we need, commands and all, just like in the good old
> > days?
> 
> You are on the right way. Configuration of Spartan-II is even easier than
> 4K. Just pull PROG low (>300ns), wait for >100us or INIT going HIGH (open
> drain), then start shifting in data. After all bit have been shifted in,
> apply additional 6 clock cycles for power up. Thats all.
> 
> --
> MfG
> Falk

How is this different from the XC4000?  I think what the OP is asking is
if there is any added work on his part to generate the file and/or
format is for sending since there seems to be a lot more complexity in
the file contents.  The data sheet describes commands and such which the
XC4000 did not have.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 44737
Subject: Re: blank CPLD
From: "Jim Raynor" <chris_cheung66@hotmail.com>
Date: Fri, 28 Jun 2002 18:35:45 GMT
Links: << >>  << T >>  << A >>
Hi,


"M. Randelzhofer" <mrandelzhofer@uumail.de> wrote in message
news:afhr7s$qgr$06$1@news.t-online.com...
> Depends on the manufacturer.
> Xilinx 95xx have pullups in the programming state which is default on new
> devices.
> Xilinx recommends to switch off any clocks or fast signals on any pin for
> programming the device.
> In practice this seems to be necessary only for already programmed parts
or
> very full parts.
> So take care in your XC95xx designs if you use a free running clock and
> consider switching off the clock oscillator with an output enable for
device
> programming.
>
> MIKE
>

I am wondering if what will happen if I don't do that..............
Please response.

Thanks





>
> "Minlin Fan" <minlinf@hotmail.com> schrieb im Newsbeitrag
> news:3d1ad654$0$27308$afc38c87@news.easynet.co.uk...
> > Hi all,
> >
> > Before being programmed, will a blank CPLD affect the rest of the
circuit
> on
> > a board? What status are all the pins with such a blank CPLD?
> >
> > Cheers.
> > Minlin
> >
> >
>
>



Article: 44738
Subject: Re: amplify and xilinx : map error 679
From: Steven Elzinga <steven.elzinga@xilinx.com>
Date: Fri, 28 Jun 2002 12:53:06 -0600
Links: << >>  << T >>  << A >>
Charles,

If possible contact Synplicity support for this problem.  Xilinx and
Synplicity will work together to resolve these kinds of issues.  These
types of problems that I have seen in the past require the design
files/project to debug exactly what is going wrong.

regards

Steve


Charles Wagner wrote:

> I am using Amplify with block regions to optimize a Virtex  XCV800
> implementation with TOP.
> Compiling is OK : no error in  Synplify log file.
> (.... Region regrgn5 : TOPS successfull.....)
>
> But when running  Xilinx tools  i get this messages in map.mrp
>
> Anyone know what's wrong?
>
> Charles
>
> Section 1 - Errors
> ------------------
> ERROR:Pack:679 - Unable to obey design constraints (LOC=CLB_R40C60.S1)
> which
>    require the combination of the following symbols into a single slice
>    component:
>         XORCY symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_s_1"
> (Output Signal
>    = Target.Design.DESIGN.CONNECT.y2_0<1>)
>         LUT symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_0"
> (Output Signal
>    = Target.Design.DESIGN.CONNECT.y2_0<0>)
>         LUT symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_1"
> (Output Signal
>    = rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_1)
>         MUXCY symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_cry_1"
> (Output
>    Signal = rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_cry_1/O)
>    The function generator
> rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_0 is
>    unable to be placed in the F position because the output signal
> doesn't match
>    other symbols' use of the F signal.  The signal
>    rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_1 already uses F.
> Please
>    correct the design constraints accordingly.


Article: 44739
Subject: Re: 5V tolerance
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Fri, 28 Jun 2002 19:48:27 GMT
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> ha scritto nel messaggio
news:3D1B692B.C87FA423@yahoo.com...

> I don't mean to offend you or anyone else at Xilinx, but
> this is a
> pretty silly licensing scheme.  Does anyone at Xilinx have
> an
> explanation for why they word the license this way?

I suppose that Xilinx makes a lot more money by selling FPGAs and CPLDs
rather than selling development kits. One developer (and one devkit) ->
a lot of devices.

--
Lorenzo



Article: 44740
Subject: State machine and syncronous inputs
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Fri, 28 Jun 2002 19:48:28 GMT
Links: << >>  << T >>  << A >>
I implemented a state machine on a Xilinx CPLD by using the Foundation
tools and ABEL. Since it stopped to work few seconds after the power up,
I did some experiments. I placed a flip-flop, triggered by the state
machine's clock itself, on every input; now the machine works without a
mistake.

Is this behavior correct? I supposed that the syncronous sampling of the
inputs should be done by the state machine itself.

--
Lorenzo



Article: 44741
Subject: Foundation and ISE
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Fri, 28 Jun 2002 19:48:29 GMT
Links: << >>  << T >>  << A >>
Until now, I've programmed only CPLDs and I am very happy with
Foundation 2.1i. Now I have to upgrade to FPGAs.

First question: are there some good introductory books on FPGAs (on
either electronic and programming topics)? A long time ago I used to
know VHDL :-) but until now I only used the Foundation graphical tools;
I suppose they are rather inadequate for FPGA.

Second question: can I continue using Foundation 2.1i? I consider it one
of the finest design tools ever made, it's a real shame that Xilinx
dismissed it. I downloaded the service packs, but a lot of new FPGAs are
missing, and even the existing ones don't seem to compile correctly.

--
Lorenzo



Article: 44742
Subject: Re: Problem: Designing for older FPGAs
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Jun 2002 13:38:14 -0700
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

> "Yes. But why not change the Virtex into a Spartan-II? They are AFAIK pin and
>
> bitstream compatible.
> And Spartan-II is well supported by Webpack.

There are package, pin-out, and speeds-file differences which might preclude
that for an existing board.  :-(

But help is on its way. I have it from insiders that this problem will be
addressed.
Yes, we make most of our money from chip sales, but we also realize that
silicon tends to live longer than a software generation...

Peter Alfke


Article: 44743
Subject: Programming a Xilinx CPDL with a Microcontroller
From: Martin Sauer <msauer@gmx.net>
Date: Fri, 28 Jun 2002 22:42:33 +0200
Links: << >>  << T >>  << A >>
Hello,


do you know if there any literature which describe the programming of a 
Xilinx CoolRunnerII CPLD? I want to program this CPLD with a 
Microcontroller via the JTAG interface.

Thank you for your Answer.

bye

martin


Article: 44744
Subject: Re: State machine and syncronous inputs
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Jun 2002 13:43:23 -0700
Links: << >>  << T >>  << A >>
CPLDs like to implement encoded state machines ( unlike FPGAs that prefer
one-hot)

If any asynchronous input is decoded to "simultaneously" drive several
flip-flops, erroneous operation is very likely. Well, it is guaranteed!
Metastabilty is not even the issue, just different decode times for the
different flip-flops.

An asynchronous input should NEVER drive more than one flip-flop.

Peter Alfke, Xilinx Applications
==================================
Lorenzo Lutti wrote:

> I implemented a state machine on a Xilinx CPLD by using the Foundation
> tools and ABEL. Since it stopped to work few seconds after the power up,
> I did some experiments. I placed a flip-flop, triggered by the state
> machine's clock itself, on every input; now the machine works without a
> mistake.
>
> Is this behavior correct? I supposed that the syncronous sampling of the
> inputs should be done by the state machine itself.
>
> --
> Lorenzo


Article: 44745
Subject: Re: State machine and syncronous inputs
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 28 Jun 2002 22:44:50 +0200
Links: << >>  << T >>  << A >>
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> schrieb im Newsbeitrag
news:g43T8.79989$Kt3.1923784@twister2.libero.it...
> I implemented a state machine on a Xilinx CPLD by using the Foundation
> tools and ABEL. Since it stopped to work few seconds after the power up,
> I did some experiments. I placed a flip-flop, triggered by the state
> machine's clock itself, on every input; now the machine works without a
> mistake.
>
> Is this behavior correct? I supposed that the syncronous sampling of the
> inputs should be done by the state machine itself.

No. The control inputs of a state machine must meet setup times. If the
inputs are asynchronus, setup times are violated -> state machine is messed
up.
Synchronized (sampled) inputs avoid this problem.

--
MfG
Falk





Article: 44746
Subject: Re: Silly questions about configuring Spartan 2's
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 28 Jun 2002 22:49:05 +0200
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:3D1CA4BA.D2B8B9C5@yahoo.com...

> How is this different from the XC4000?  I think what the OP is asking is

Not much. On the 4K you need to wait a few microseconds after INIT goes high
before you can start shifting in data. With Spartan-II, you dont need this
delay.
Also the 4K has a length count in the datasteam, which the Spartan-II doesnt
have.

--
MfG
Falk







Article: 44747
Subject: XC9572 VCCIO change
From: Joerg Schneide <JSchneide@t-online.de>
Date: Fri, 28 Jun 2002 23:14:58 +0200
Links: << >>  << T >>  << A >>
Hello,

is it possible to change the VCCIO (without damage or other negative effects)
in the range of 3.3-5V of a XC9572 when it is powered up?

thanks,

Jörg.





Article: 44748
Subject: Re: State machine and syncronous inputs
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 29 Jun 2002 09:27:11 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> CPLDs like to implement encoded state machines ( unlike FPGAs that prefer
> one-hot)
> 
> If any asynchronous input is decoded to "simultaneously" drive several
> flip-flops, erroneous operation is very likely. Well, it is guaranteed!
> Metastabilty is not even the issue, just different decode times for the
> different flip-flops.
> 
> An asynchronous input should NEVER drive more than one flip-flop.

 This is correct, some more clarifications -  
We call this effect 'aperture time', and whilst it is not (yet) 
in any data sheets, there is a finite practical spread in all 
FlipFlips CLK -> D sampling time. 
Decode in front of the D, even single level logic, with 
different Tphl and Tphl, and path delays, can only widen this aperture. 
 Real Aperture time is less than Th-Ts, but still finite.

 Whilst it is possible to construct a state engine with direct async IP,
it needs extreme care to ensure only ONE flipflop is 'async dependant'
in each state, as Peter mentions.

 If a full clock sample delay is a problem, you can use opposite edge
clocking on the syncronising registers. (HW dependant)

 If registers are available, and state clock is not high, you can
also use multiple sampling registers, and a majority vote scheme.

-jg

Article: 44749
Subject: Re: VIRTEX II DCM Question
From: jeff@mock.com (Jeff Mock)
Date: 28 Jun 2002 14:42:54 -0700
Links: << >>  << T >>  << A >>
Wow, that's super cool, I like the innovative use of the DDR
flip-flops!

jeff

Peter Alfke <peter@xilinx.com> wrote in message news:<3D1C8B75.E615B134@xilinx.com>...
> Here is an even better answer from one of the Xilinx experts ( who wants to remain
> anonymous...)
> 
> I think the best thing to do is :
> 
> CLK--+--DCM-----BUFG---internal clock
>      |
>      +--DCM-----BUFG---to FDDRRSE primitive(s)
> 
> The top DCM and BUFG are used for the internal clock. The bottom DCM
> and BUFG are used to drive FDDRRSE primitives. Each BUFG feeds back
> to it's own DCM. The bottom BUFG can also then be phase-adjusted to
> move the clock where he needs it. By connecting the D0 and D1 inputs
> to the FDDRRSE primitives to VCC and GND (or vice-versa), you will
> get an exact copy of the clock, or it's inverse (180 degree phase
> shift). Of course, there will be the clock-to-out delay of the IOB
> DDR flop, but that can be adjusted/corrected with the phase shift
> of the bottom DCM that drives these IOB flops.
> 
> There will be a slightly better duty cycle if two BUFGs are used
> with the bottom DCM -- one for CLK0 and one for CLK180 vs. the
> single BUFG method that I described above.
> 
> 
> 
> 
> 
> 
> 
> Peter Alfke wrote:
> 
> > You don't need two DCMs, one is enough. It generates the two phases (0 and 180 ) with
> > as good a precision as is possible ( 50 ps resolution). Then you can route these
> > signals on two glabal clocks.
> > Thiis more accurate than doing local inversion in ths I/O.
> >
> > Peter Alfke, Xilinx Applications
> > ========================
> > J



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