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On 5/25/2016 12:59 PM, Tim Wescott wrote: > On Tue, 24 May 2016 19:17:51 -0400, rickman wrote: > >> On 5/24/2016 1:20 PM, Tim Wescott wrote: >>> >>> I am equally inept in either one. Really, I think that at my level it >>> has less to do with the language and more to do with not having an >>> intuitive grasp of what's going to fit well with a given FPGA structure >>> vs. what's not, and if I'm not careful I start to think sequentially, >>> which translates to long if-then-else chains in either language, which >>> get synthesized as these really wide-to-one MUX's with high delays in >>> the chip. >> >> Yeah, I know what you mean. The one guy I know who was able to complete >> a design without going over to the "dark" side (thinking hardware) >> needed to do a not too complex project in a very large FPGA. So he >> didn't care about size but needed to get it done quickly. I gave him >> some help off the group, but not a lot and he was able to get the job >> done. He was appreciative since we had talked about my coming to town >> to help formally, but management turned it down. He ended up showing >> his appreciation by getting them to send me a check for my troubles, >> which was not necessary at all. It was only a few hours which I chalked >> up to good will. So I sent him a polo shirt with my company logo, lol. >> >> If you would like any assistance or review of code, I'd be happy to help >> on the books or if it isn't too many hours, off the books. I'm having >> my hip done in two weeks, so I'll have plenty of time recouping when I'm >> bored and looking for something to do. Likely I won't really find much >> truly wrong with your code, but maybe I'll have suggestions on >> techniques that might make it simpler. >> >> The funny part is I can do this stuff easily, but I would have a very >> hard time writing it down. I just put together a brief presentation to >> go with a presentation Dr. Ting is doing for the Sunnyvale Forth Users >> Group (SVFIG) on a VHDL 8080 design. His example code is an 8080, >> memory and a UART. He verifies it runs by running Forth on it and >> getting an OK> prompt. So I wrote a testbench that reads commands from >> a text file to instruct it to write data on the data bus and verify the >> addresses and returned data. With just an 11 line test program I found >> a flaw in the increment/decrement instructions. I guess I got lucky. >> >> I prepared some slides^H^H^H^H^H^H uh, a power point presentation, but I >> don't know it is so good. I should stick to writing code I think. > > When I started I had hopes of founding a vast design engineering bureau, > but it turns out that my sales & marketing chops simply aren't up to it. > So it's just me. > > Should a project cross my desk that requires combined FPGA & software > work I'll give you a call -- should one cross my desk that requires > _just_ FPGA work, I may well just give the prospect your name. I was rereading my post and I should clarify that the 11 line (not counting comments) program is the test command file. The VHDL file is around 250 lines with the heaeder. Here is the command file -- This is a comment RESET 02 FETCH 0000 00 -- NOP FETCH 0001 AF -- CLR ACCUM FETCH 0002 3D -- DCR A FETCH 0003 67 -- MOV H,A FETCH 0004 6F -- MOV L,A FETCH 0005 77 -- MOV M,A WRITE FFFF FF -- verify address and data -- Write command shows DCR is not correct FETCH 0006 46 -- MOV B,M READ FFFF BE -- verify address, provide data FETCH 0007 00 -- NOP VHDL text IO is a bit crude, so I had to write routines to read the hex numbers and parse the fields. Not so hard because I kept it simple. -- Rick CArticle: 158926
Hello,
my question is probably best explained on a piece of code (the snippet is V=
erilog, but the question should be mostly language-agnostic)
reg memory_access;
reg[1:0] memory_access_size;
always @ (posedge clk) begin
if (clk_en && should_decode_input) begin
memory_access_size <=3D 2'bxx; // <---
case(some_input_data)
ACTION_1: begin
memory_access <=3D 1;
memory_access_size <=3D 2'b10;
end
ACTION_2: begin
memory_access <=3D 1;
memory_access_size <=3D 2'b01;
end
ACTION_3: begin
memory_access <=3D 0;
end
endcase
end
end
(the actual scenario is a Thumb instruction decoder)
My question is about the line marked with "// <---". If I understand the se=
mantics correctly, including this line should make the compiler's job easie=
r, by basically saying "unless I assign a new value to memory_access_size, =
do whatever with it". Thus, in the ACTION_3 case, it doesn't have to care a=
bout preserving its previous value (which is no longer relevant), presumabl=
y reducing the logic complexity.
I'm wondering whether this really is the case, in particular:
- Will this actually lead to more efficient logic realization with generall=
y available (Altera, Xilinx) tools?
- Does this introduce any caveats to be aware of?
- Would you generally consider this a good coding practice?
Thanks in advance
-M
Article: 158927In article <f2fbb4be-84a9-48cc-8210-1c9ef0830ea9@googlegroups.com>, <minexew@gmail.com> wrote: >Hello, >my question is probably best explained on a piece of code (the snippet is Verilog, but the question should be mostly language-agnostic) > >reg memory_access; >reg[1:0] memory_access_size; > >always @ (posedge clk) begin > if (clk_en && should_decode_input) begin > memory_access_size <= 2'bxx; // <--- > > case(some_input_data) > ACTION_1: begin > memory_access <= 1; > memory_access_size <= 2'b10; > end > ACTION_2: begin > memory_access <= 1; > memory_access_size <= 2'b01; > end > ACTION_3: begin > memory_access <= 0; > end > endcase > end >end > >(the actual scenario is a Thumb instruction decoder) > >My question is about the line marked with "// <---". If I understand the semantics correctly, including this line should make the compiler's job easier, by basically saying >"unless I assign a new value to memory_access_size, do whatever with it". Thus, in the ACTION_3 case, it doesn't have to care about preserving its previous value (which is no >longer relevant), presumably reducing the logic complexity. > >I'm wondering whether this really is the case, in particular: >- Will this actually lead to more efficient logic realization with generally available (Altera, Xilinx) tools? >- Does this introduce any caveats to be aware of? >- Would you generally consider this a good coding practice? I *AGGRESSIVELY* avoid introducing Xs, and work hard to eliminate ANY sources of X in my design. Goggle search term "X-optimism", and "X-pessimism". Any logic optimization's going to me TINY in the grand scheme of things. The hazards waiting to bite you are not worth it. I'd "eye" optimize it, by just assigning it to one of the other values you've already assigned in the other qualifications. It'll likely come out darn near equivalent. Regards, MarkArticle: 158928
Dne st=C5=99eda 25. kv=C4=9Btna 2016 20:16:39 UTC+2 Mark Curry napsal(a): > In article <f2fbb4be-84a9-48cc-8210-1c9ef0830ea9@googlegroups.com>, > <minexew@gmail.com> wrote: > >Hello, > >my question is probably best explained on a piece of code (the snippet i= s Verilog, but the question should be mostly language-agnostic) > > > >reg memory_access; > >reg[1:0] memory_access_size; > > > >always @ (posedge clk) begin > > if (clk_en && should_decode_input) begin > > memory_access_size <=3D 2'bxx; // <--- > > > > case(some_input_data) > > ACTION_1: begin > > memory_access <=3D 1; > > memory_access_size <=3D 2'b10; > > end > > ACTION_2: begin > > memory_access <=3D 1; > > memory_access_size <=3D 2'b01; > > end > > ACTION_3: begin > > memory_access <=3D 0; > > end > > endcase > > end > >end > > > >(the actual scenario is a Thumb instruction decoder) > > > >My question is about the line marked with "// <---". If I understand the= semantics correctly, including this line should make the compiler's job ea= sier, by basically saying > >"unless I assign a new value to memory_access_size, do whatever with it"= . Thus, in the ACTION_3 case, it doesn't have to care about preserving its = previous value (which is no > >longer relevant), presumably reducing the logic complexity. > > > >I'm wondering whether this really is the case, in particular: > >- Will this actually lead to more efficient logic realization with gener= ally available (Altera, Xilinx) tools? > >- Does this introduce any caveats to be aware of? > >- Would you generally consider this a good coding practice? >=20 > I *AGGRESSIVELY* avoid introducing Xs, and work hard to eliminate ANY sou= rces of=20 > X in my design. Goggle search term "X-optimism", and "X-pessimism". > Any logic optimization's going to me TINY in the grand scheme of things. > The hazards waiting to bite you are not worth it. >=20 > I'd "eye" optimize it, by just assigning it to one of the other values > you've already assigned in the other qualifications. It'll likely > come out darn near equivalent. >=20 > Regards, >=20 > Mark Isn't that exactly the point, though? The variable at that point really bec= omes undefined - and if any other code assumes it to be defined, it is a bu= g. If the X ends up propagating where it shouldn't, it means there is somet= hing wrong with the logic. I'll look into the terms you mentioned. They seem to be what I was looking = for, but couldn't find. Thank you, M.Article: 158929
In article <10bd1028-a05c-45aa-a9db-ed43392e0b14@googlegroups.com>, <minexew@gmail.com> wrote: >Dne středa 25. května 2016 20:16:39 UTC+2 Mark Curry napsal(a): >> In article <f2fbb4be-84a9-48cc-8210-1c9ef0830ea9@googlegroups.com>, >> <minexew@gmail.com> wrote: >> >Hello, >> >my question is probably best explained on a piece of code (the snippet is Verilog, but the question should be mostly language-agnostic) >> > >> >reg memory_access; >> >reg[1:0] memory_access_size; >> > >> >always @ (posedge clk) begin >> > if (clk_en && should_decode_input) begin >> > memory_access_size <= 2'bxx; // <--- >> > >> > case(some_input_data) >> > ACTION_1: begin >> > memory_access <= 1; >> > memory_access_size <= 2'b10; >> > end >> > ACTION_2: begin >> > memory_access <= 1; >> > memory_access_size <= 2'b01; >> > end >> > ACTION_3: begin >> > memory_access <= 0; >> > end >> > endcase >> > end >> >end >> > >> >(the actual scenario is a Thumb instruction decoder) >> > >> >My question is about the line marked with "// <---". If I understand the semantics correctly, including this line should make the compiler's job easier, by basically saying >> >"unless I assign a new value to memory_access_size, do whatever with it". Thus, in the ACTION_3 case, it doesn't have to care about preserving its previous value (which is no >> >longer relevant), presumably reducing the logic complexity. >> > >> >I'm wondering whether this really is the case, in particular: >> >- Will this actually lead to more efficient logic realization with generally available (Altera, Xilinx) tools? >> >- Does this introduce any caveats to be aware of? >> >- Would you generally consider this a good coding practice? >> >> I *AGGRESSIVELY* avoid introducing Xs, and work hard to eliminate ANY sources of >> X in my design. Goggle search term "X-optimism", and "X-pessimism". >> Any logic optimization's going to me TINY in the grand scheme of things. >> The hazards waiting to bite you are not worth it. >> >> I'd "eye" optimize it, by just assigning it to one of the other values >> you've already assigned in the other qualifications. It'll likely >> come out darn near equivalent. >> >> Regards, >> >> Mark > >Isn't that exactly the point, though? The variable at that point really becomes undefined > - and if any other code assumes it to be defined, it is a bug. If the X ends up >propagating where it shouldn't, it means there is something wrong with the logic. There's finding bugs and creating the most optimal design. The second goal is way behind the first, IMHO. I'll not introduce X's to get a more optimal design. Ever. As a matter of fact I go extensively out of my way to avoid hidden bugs at sometimes significant costs to Quality of Results. Xilinx likes to preach "Don't reset everything. Reset should be the exception not the rule." My design style is exacty the opposite. Reset everything (to avoid initialization Xs), with some exceptions. I'm of the opinion that Xilinx is hopelessly wrong in this regard, and is advocating wreckless guidance. As to finding bugs, your mileage may vary. I avoid introducing X's. I don't think they buy me anything actually, and may hinder. Read the papers - there's a lot out there. There's no easy answer. Regards, MarkArticle: 158930
On 5/25/2016 2:30 PM, minexew@gmail.com wrote: > Dne středa 25. května 2016 20:16:39 UTC+2 Mark Curry napsal(a): >> In article <f2fbb4be-84a9-48cc-8210-1c9ef0830ea9@googlegroups.com>, >> <minexew@gmail.com> wrote: >>> Hello, >>> my question is probably best explained on a piece of code (the snippet is Verilog, but the question should be mostly language-agnostic) >>> >>> reg memory_access; >>> reg[1:0] memory_access_size; >>> >>> always @ (posedge clk) begin >>> if (clk_en && should_decode_input) begin >>> memory_access_size <= 2'bxx; // <--- >>> >>> case(some_input_data) >>> ACTION_1: begin >>> memory_access <= 1; >>> memory_access_size <= 2'b10; >>> end >>> ACTION_2: begin >>> memory_access <= 1; >>> memory_access_size <= 2'b01; >>> end >>> ACTION_3: begin >>> memory_access <= 0; >>> end >>> endcase >>> end >>> end >>> >>> (the actual scenario is a Thumb instruction decoder) >>> >>> My question is about the line marked with "// <---". If I understand the semantics correctly, including this line should make the compiler's job easier, by basically saying >>> "unless I assign a new value to memory_access_size, do whatever with it".. Thus, in the ACTION_3 case, it doesn't have to care about preserving its previous value (which is no >>> longer relevant), presumably reducing the logic complexity. >>> >>> I'm wondering whether this really is the case, in particular: >>> - Will this actually lead to more efficient logic realization with generally available (Altera, Xilinx) tools? >>> - Does this introduce any caveats to be aware of? >>> - Would you generally consider this a good coding practice? >> >> I *AGGRESSIVELY* avoid introducing Xs, and work hard to eliminate ANY sources of >> X in my design. Goggle search term "X-optimism", and "X-pessimism". >> Any logic optimization's going to me TINY in the grand scheme of things. >> The hazards waiting to bite you are not worth it. >> >> I'd "eye" optimize it, by just assigning it to one of the other values >> you've already assigned in the other qualifications. It'll likely >> come out darn near equivalent. >> >> Regards, >> >> Mark > > Isn't that exactly the point, though? The variable at that point really becomes undefined - and if any other code assumes it to be defined, it is a bug. If the X ends up propagating where it shouldn't, it means there is something wrong with the logic. > > I'll look into the terms you mentioned. They seem to be what I was looking for, but couldn't find. I'm not sure what you intend. I think you are saying the "some_input_data" can have values other than the defined cases in normal operation. But they should only occur at times the following logic won't care. I would normally say check your input data, but it seems you are allowing undefined states. memory_access_size only takes the values 'b01 or 'b10. I would assign a value of say 'b11 and have the downstream logic check for that. If the downstream logic is using that input when it is in the wrong value it can explicitly throw a flag. Can you define those times easily? -- Rick CArticle: 158931
Dne st=C5=99eda 25. kv=C4=9Btna 2016 20:51:33 UTC+2 rickman napsal(a): > On 5/25/2016 2:30 PM, minexew@gmail.com wrote: > > Dne st=C5=99eda 25. kv=C4=9Btna 2016 20:16:39 UTC+2 Mark Curry napsal(a= ): > >> In article <f2fbb4be-84a9-48cc-8210-1c9ef0830ea9@googlegroups.com>, > >> <minexew@gmail.com> wrote: > >>> Hello, > >>> my question is probably best explained on a piece of code (the snippe= t is Verilog, but the question should be mostly language-agnostic) > >>> > >>> reg memory_access; > >>> reg[1:0] memory_access_size; > >>> > >>> always @ (posedge clk) begin > >>> if (clk_en && should_decode_input) begin > >>> memory_access_size <=3D 2'bxx; // <--- > >>> > >>> case(some_input_data) > >>> ACTION_1: begin > >>> memory_access <=3D 1; > >>> memory_access_size <=3D 2'b10; > >>> end > >>> ACTION_2: begin > >>> memory_access <=3D 1; > >>> memory_access_size <=3D 2'b01; > >>> end > >>> ACTION_3: begin > >>> memory_access <=3D 0; > >>> end > >>> endcase > >>> end > >>> end > >>> > >>> (the actual scenario is a Thumb instruction decoder) > >>> > >>> My question is about the line marked with "// <---". If I understand = the semantics correctly, including this line should make the compiler's job= easier, by basically saying > >>> "unless I assign a new value to memory_access_size, do whatever with = it".. Thus, in the ACTION_3 case, it doesn't have to care about preserving = its previous value (which is no > >>> longer relevant), presumably reducing the logic complexity. > >>> > >>> I'm wondering whether this really is the case, in particular: > >>> - Will this actually lead to more efficient logic realization with ge= nerally available (Altera, Xilinx) tools? > >>> - Does this introduce any caveats to be aware of? > >>> - Would you generally consider this a good coding practice? > >> > >> I *AGGRESSIVELY* avoid introducing Xs, and work hard to eliminate ANY = sources of > >> X in my design. Goggle search term "X-optimism", and "X-pessimism". > >> Any logic optimization's going to me TINY in the grand scheme of thing= s. > >> The hazards waiting to bite you are not worth it. > >> > >> I'd "eye" optimize it, by just assigning it to one of the other values > >> you've already assigned in the other qualifications. It'll likely > >> come out darn near equivalent. > >> > >> Regards, > >> > >> Mark > > > > Isn't that exactly the point, though? The variable at that point really= becomes undefined - and if any other code assumes it to be defined, it is = a bug. If the X ends up propagating where it shouldn't, it means there is s= omething wrong with the logic. > > > > I'll look into the terms you mentioned. They seem to be what I was look= ing for, but couldn't find. >=20 > I'm not sure what you intend. I think you are saying the=20 > "some_input_data" can have values other than the defined cases in normal= =20 > operation. But they should only occur at times the following logic=20 > won't care. I would normally say check your input data, but it seems=20 > you are allowing undefined states. >=20 > memory_access_size only takes the values 'b01 or 'b10. I would assign a= =20 > value of say 'b11 and have the downstream logic check for that. If the= =20 > downstream logic is using that input when it is in the wrong value it=20 > can explicitly throw a flag. Can you define those times easily? >=20 > --=20 >=20 > Rick C Maybe it isn't as obvious as I hoped - in the case of ACTION_3, no memory a= ccess will take place and no other code should attempt to make decisions ba= sed on this memory access' size (because there isn't any!) Also, from the synthesizer's point of view, the logic for setting memory_ac= cess_size should become simpler. I believe, however, that I'm starting to understand one of the deeper probl= em with X's. I didn't realize that if (1'b1 =3D=3D 1'bx) will evaluate to false, instead of immediately aborting the simulation with= an error, which would be the right thing to do IMO. Of course, it's not as simple as it may seem, because an expression like (1= 'b0 && 1'bx) is perfectly valid. I'm not even sure if determining the valid= ity of these expressions would be trivial. Now I see how X-values can mask actual errors in the design and I'll probab= ly start to avoid them too. -M.Article: 158932
On 5/25/2016 3:07 PM, minexew@gmail.com wrote: > Dne středa 25. května 2016 20:51:33 UTC+2 rickman napsal(a): >> On 5/25/2016 2:30 PM, minexew@gmail.com wrote: >>> Dne středa 25. května 2016 20:16:39 UTC+2 Mark Curry napsal(a): >>>> In article <f2fbb4be-84a9-48cc-8210-1c9ef0830ea9@googlegroups.com>, >>>> <minexew@gmail.com> wrote: >>>>> Hello, >>>>> my question is probably best explained on a piece of code (the snippet is Verilog, but the question should be mostly language-agnostic) >>>>> >>>>> reg memory_access; >>>>> reg[1:0] memory_access_size; >>>>> >>>>> always @ (posedge clk) begin >>>>> if (clk_en && should_decode_input) begin >>>>> memory_access_size <= 2'bxx; // <--- >>>>> >>>>> case(some_input_data) >>>>> ACTION_1: begin >>>>> memory_access <= 1; >>>>> memory_access_size <= 2'b10; >>>>> end >>>>> ACTION_2: begin >>>>> memory_access <= 1; >>>>> memory_access_size <= 2'b01; >>>>> end >>>>> ACTION_3: begin >>>>> memory_access <= 0; >>>>> end >>>>> endcase >>>>> end >>>>> end >>>>> >>>>> (the actual scenario is a Thumb instruction decoder) >>>>> >>>>> My question is about the line marked with "// <---". If I understand the semantics correctly, including this line should make the compiler's job easier, by basically saying >>>>> "unless I assign a new value to memory_access_size, do whatever with it".. Thus, in the ACTION_3 case, it doesn't have to care about preserving its previous value (which is no >>>>> longer relevant), presumably reducing the logic complexity. >>>>> >>>>> I'm wondering whether this really is the case, in particular: >>>>> - Will this actually lead to more efficient logic realization with generally available (Altera, Xilinx) tools? >>>>> - Does this introduce any caveats to be aware of? >>>>> - Would you generally consider this a good coding practice? >>>> >>>> I *AGGRESSIVELY* avoid introducing Xs, and work hard to eliminate ANY sources of >>>> X in my design. Goggle search term "X-optimism", and "X-pessimism". >>>> Any logic optimization's going to me TINY in the grand scheme of things. >>>> The hazards waiting to bite you are not worth it. >>>> >>>> I'd "eye" optimize it, by just assigning it to one of the other values >>>> you've already assigned in the other qualifications. It'll likely >>>> come out darn near equivalent. >>>> >>>> Regards, >>>> >>>> Mark >>> >>> Isn't that exactly the point, though? The variable at that point really becomes undefined - and if any other code assumes it to be defined, it is a bug. If the X ends up propagating where it shouldn't, it means there is something wrong with the logic. >>> >>> I'll look into the terms you mentioned. They seem to be what I was looking for, but couldn't find. >> >> I'm not sure what you intend. I think you are saying the >> "some_input_data" can have values other than the defined cases in normal >> operation. But they should only occur at times the following logic >> won't care. I would normally say check your input data, but it seems >> you are allowing undefined states. >> >> memory_access_size only takes the values 'b01 or 'b10. I would assign a >> value of say 'b11 and have the downstream logic check for that. If the >> downstream logic is using that input when it is in the wrong value it >> can explicitly throw a flag. Can you define those times easily? >> >> -- >> >> Rick C > > Maybe it isn't as obvious as I hoped - in the case of ACTION_3, no memory access will take place and no other code should attempt to make decisions based on this memory access' size (because there isn't any!) > Also, from the synthesizer's point of view, the logic for setting memory_access_size should become simpler. > > I believe, however, that I'm starting to understand one of the deeper problem with X's. I didn't realize that > > if (1'b1 == 1'bx) > > will evaluate to false, instead of immediately aborting the simulation with an error, which would be the right thing to do IMO. > Of course, it's not as simple as it may seem, because an expression like (1'b0 && 1'bx) is perfectly valid. I'm not even sure if determining the validity of these expressions would be trivial. > > Now I see how X-values can mask actual errors in the design and I'll probably start to avoid them too. I'm a bit unclear. In your synthesizable code, you don't have a comparison like this do you? I'm not so familiar with Verilog as I am VHDL. In VHDL they have an assert statement that can throw an error flag. But I think the issue is that there will be logic that uses the memory access size, but when the size is not valid, the logic should not be used. I'm not sure how you would distinguish those two states. That's the issue, is that logic in use when there is no memory access? Why can't you define this in terms of logic and detect it either in your test bench or in the synthesized code? -- Rick CArticle: 158933
On 05/25/2016 10:58 AM, minexew@gmail.com wrote: > Hello, > my question is probably best explained on a piece of code (the snippet is Verilog, but the question should be mostly language-agnostic) > > reg memory_access; > reg[1:0] memory_access_size; > > always @ (posedge clk) begin > if (clk_en && should_decode_input) begin > memory_access_size <= 2'bxx; // <--- > > case(some_input_data) > ACTION_1: begin > memory_access <= 1; > memory_access_size <= 2'b10; > end > ACTION_2: begin > memory_access <= 1; > memory_access_size <= 2'b01; > end > ACTION_3: begin > memory_access <= 0; > end > endcase > end > end > > (the actual scenario is a Thumb instruction decoder) > > My question is about the line marked with "// <---". If I understand the semantics correctly, including this line should make the compiler's job easier, by basically saying "unless I assign a new value to memory_access_size, do whatever with it". Thus, in the ACTION_3 case, it doesn't have to care about preserving its previous value (which is no longer relevant), presumably reducing the logic complexity. > > I'm wondering whether this really is the case, in particular: > - Will this actually lead to more efficient logic realization with generally available (Altera, Xilinx) tools? > - Does this introduce any caveats to be aware of? > - Would you generally consider this a good coding practice? > > Thanks in advance > -M > Other than the creeping red cancer eating your simulation viewer, I don't think you will get much notice of the X values in a simulation. Stylistically, I would put a default in the case statement. I have seen enough state machines go wrong in unpleasant and difficult to identify ways due to not completely specifying results. I think that a static value would result in the optimization results you want without the risks. Good Luck, BobHArticle: 158934
On Wednesday, May 25, 2016 at 1:58:21 PM UTC-4, min...@gmail.com wrote: <snip>Thus, in the ACTION_3 case, it doesn't have to care about preserving= =20 > its previous value (which is no longer relevant), presumably reducing the= =20 > logic complexity. That's an assumption. When you go to validate that assumption, I think you= 'll find that there is no benefit, you'll likely get the exact same output = binary file. >=20 > I'm wondering whether this really is the case, in particular: > - Will this actually lead to more efficient logic realization with genera= lly available (Altera, Xilinx) tools? No (or at least it didn't used to with Altera). What Quartus would do is r= eplace the don't care (and any other metavalues) with a 0. This gets repor= ted in the transcript window as a note. > - Does this introduce any caveats to be aware of? Not really. If it simulates properly (and it should), then it will work th= e same in real hardware. > - Would you generally consider this a good coding practice? >=20 Here are some yay/nays - No, because it does not produce any actual benefit. - Yes, if you try it out and find that all of the latest releases of the to= ols from whoever you would tend to target parts does actually benefit. - Maybe, if you are producing code that is intended for others to use and y= ou have no idea whether the tools that they may use would benefit. In this= case though, as long as their is no harm (like the tool erroring out) then= it's OK since code that you are providing is typically not meant to be mon= keyed around with by the user. Kevin JenningsArticle: 158935
http://www.xess.com/blog/extinction-level-event/ The synopsis of the guy's argument is: Given Intel bought Altera, and rumors that *comm is eyeing Xilinx, that's likely to shift the focus of both tier 1 FPGA companies to datacenters and away from traditional programmable logic. We need a good Friday thread, it's been a while. What do y'all think? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 158936
On Friday, May 27, 2016 at 1:01:13 PM UTC-4, Rob Gaddi wrote: > http://www.xess.com/blog/extinction-level-event/ > > The synopsis of the guy's argument is: Given Intel bought Altera, and > rumors that *comm is eyeing Xilinx, that's likely to shift the focus of > both tier 1 FPGA companies to datacenters and away from traditional > programmable logic. > > We need a good Friday thread, it's been a while. What do y'all think? People need FPGAs. You can't economically produce flexible, workable products which are true hardware IC, and completely variable, without them. You'd be back to the model we had in the 80s and 90s where you must hire firms to design things for you, and that's an expense that companies won't want ... so someone would follow-on with an FPGA, even if it's slower because it has to work around patents. Someone will maintain that industry because it's essential to both design, and use in real products. There are also several other FPGA manufacturers that make lesser products that may immediately be viable alternatives, or are then targets in the industry for immediate growth into larger, more capable products. Best regards, Rick C. HodginArticle: 158937
I a retired person with limited resources and I've always been interested in CPU design, so now that I have time I wanted to give it a go using FPGAs to design simple CPUs. I would like some advice on several topics, one being which HDL language to learn first, although Verilog seems simpler I've read articles that encourages beginners to start with VHDL, although it seems more wordy, I believe it will help eliminate more dumb mistakes so I'm leaning that way. What is your advice? Another is which logic families/companies make products that are inexpensive and have good features useful in creating CPUs and DSP type products as I also am interested in Software Defined Radios. I have purchase for a starter kit a Lattice Brevia2 kit as it was inexpensive and has low power consumption, so I assume will be easier to use in the beginning. It's a simple device with 5K LUTs which seems to be enough for some of the simple processors that I'm interested in to start with, CPUs such as the J1 for starters. From some time back I've have a Xilinx Spartan 3 Started kit that I have not used, I plan to use it later for more complex designs. Your opinions and advice is welcomed. -- Cecil - k5nwaArticle: 158938
On Fri, 27 May 2016 13:00:28 -0500, Cecil Bayona wrote: > I a retired person with limited resources and I've always been > interested in CPU design, so now that I have time I wanted to give it a > go using FPGAs to design simple CPUs. > > I would like some advice on several topics, one being which HDL language > to learn first, although Verilog seems simpler I've read articles that > encourages beginners to start with VHDL, although it seems more wordy, I > believe it will help eliminate more dumb mistakes so I'm leaning that > way. What is your advice? > > Another is which logic families/companies make products that are > inexpensive and have good features useful in creating CPUs and DSP type > products as I also am interested in Software Defined Radios. > > I have purchase for a starter kit a Lattice Brevia2 kit as it was > inexpensive and has low power consumption, so I assume will be easier to > use in the beginning. It's a simple device with 5K LUTs which seems to > be enough for some of the simple processors that I'm interested in to > start with, CPUs such as the J1 for starters. From some time back I've > have a Xilinx Spartan 3 Started kit that I have not used, I plan to use > it later for more complex designs. > > Your opinions and advice is welcomed. Verilog if you're on the west coast, VHDL if east. I'm not sure about Texas, though. Seriously, it's a lot more important to understand how to design than to pick the right language. You can do crappy work in either one, and you can do good work in either one. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.comArticle: 158939
On Fri, 27 May 2016 16:57:30 +0000, Rob Gaddi wrote: > http://www.xess.com/blog/extinction-level-event/ > > The synopsis of the guy's argument is: Given Intel bought Altera, and > rumors that *comm is eyeing Xilinx, that's likely to shift the focus of > both tier 1 FPGA companies to datacenters and away from traditional > programmable logic. > > We need a good Friday thread, it's been a while. What do y'all think? Someone will come and pick up the pieces, possibly at a profit. I believe that there are east Asian FPGA companies out there -- with luck, they'd see sales opportunities over here if the Big Two dropped out of the race. With bad luck, America will just export raw materials to countries who turn them into consumer goods, we'll all be dirt poor except for a very few, and we will have lost the Revolutionary War 250 years after the fact, only not to England. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.comArticle: 158940
On 5/27/2016 4:15 PM, Tim Wescott wrote: > On Fri, 27 May 2016 13:00:28 -0500, Cecil Bayona wrote: > >> I a retired person with limited resources and I've always been >> interested in CPU design, so now that I have time I wanted to give it a >> go using FPGAs to design simple CPUs. >> >> I would like some advice on several topics, one being which HDL language >> to learn first, although Verilog seems simpler I've read articles that >> encourages beginners to start with VHDL, although it seems more wordy, I >> believe it will help eliminate more dumb mistakes so I'm leaning that >> way. What is your advice? >> >> Another is which logic families/companies make products that are >> inexpensive and have good features useful in creating CPUs and DSP type >> products as I also am interested in Software Defined Radios. >> >> I have purchase for a starter kit a Lattice Brevia2 kit as it was >> inexpensive and has low power consumption, so I assume will be easier to >> use in the beginning. It's a simple device with 5K LUTs which seems to >> be enough for some of the simple processors that I'm interested in to >> start with, CPUs such as the J1 for starters. From some time back I've >> have a Xilinx Spartan 3 Started kit that I have not used, I plan to use >> it later for more complex designs. >> >> Your opinions and advice is welcomed. > > Verilog if you're on the west coast, VHDL if east. I'm not sure about > Texas, though. > > Seriously, it's a lot more important to understand how to design than to > pick the right language. You can do crappy work in either one, and you > can do good work in either one. > Hardware design I understand, I put together my own CPU design and built it with Schottky logic, and it worked rather well. But as to Verilog or VHDL I know zip. I do have a couple of books on the subject of FPGA programing but I don't think of them as any good. They go into the tiny details such on how to make an adder but contains little on the overall structure and how to design anything of consequence. Are there any books or Internet sources on the subject of overall design with FPGAs? I would be specifically interested on CPU design using HDL. Thanks -- Cecil - k5nwaArticle: 158941
On Fri, 27 May 2016 16:53:12 -0500, Cecil Bayona wrote: > On 5/27/2016 4:15 PM, Tim Wescott wrote: >> On Fri, 27 May 2016 13:00:28 -0500, Cecil Bayona wrote: >> >>> I a retired person with limited resources and I've always been >>> interested in CPU design, so now that I have time I wanted to give it >>> a go using FPGAs to design simple CPUs. >>> >>> I would like some advice on several topics, one being which HDL >>> language to learn first, although Verilog seems simpler I've read >>> articles that encourages beginners to start with VHDL, although it >>> seems more wordy, I believe it will help eliminate more dumb mistakes >>> so I'm leaning that way. What is your advice? >>> >>> Another is which logic families/companies make products that are >>> inexpensive and have good features useful in creating CPUs and DSP >>> type products as I also am interested in Software Defined Radios. >>> >>> I have purchase for a starter kit a Lattice Brevia2 kit as it was >>> inexpensive and has low power consumption, so I assume will be easier >>> to use in the beginning. It's a simple device with 5K LUTs which seems >>> to be enough for some of the simple processors that I'm interested in >>> to start with, CPUs such as the J1 for starters. From some time back >>> I've have a Xilinx Spartan 3 Started kit that I have not used, I plan >>> to use it later for more complex designs. >>> >>> Your opinions and advice is welcomed. >> >> Verilog if you're on the west coast, VHDL if east. I'm not sure about >> Texas, though. >> >> Seriously, it's a lot more important to understand how to design than >> to pick the right language. You can do crappy work in either one, and >> you can do good work in either one. >> > Hardware design I understand, I put together my own CPU design and built > it with Schottky logic, and it worked rather well. But as to Verilog or > VHDL I know zip. I do have a couple of books on the subject of FPGA > programing but I don't think of them as any good. They go into the tiny > details such on how to make an adder but contains little on the overall > structure and how to design anything of consequence. > > Are there any books or Internet sources on the subject of overall design > with FPGAs? I would be specifically interested on CPU design using HDL. Look for books with "Computer Systems Architecture" either in or as the title. they will not and should not mention FPGAs -- by the time you're making architectural decisions you probably shouldn't be too worried about what the underlying technology is. Then, get your hands on data sheets for as many different processors as you can and see how they did it. Think of strengths and weaknesses, and why the designers might have done what they did. And let me indulge myself with a shout-out to the RCA COSMAC 1802 processor. It was the first thing I ever wrote assembly for, and you could practically draw the control logic from the instruction set. I dimly remember (meaning that I saw it between two days and two decades ago) that there's an FPGA version of the core that's at least byte- accurate, if maybe not clock-cycle accurate. In these days of RISC computers, it's nice to be familiar with a NHISC (Never Had an Instruction Set) computer. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 158942
Cecil, here's a very simple 8-bit CPU I designed, called Oppie-1. It
compiles in Verilog and in Altera's Quartus II software. I have not
validated it, so it's probably buggy. But, it may be interesting to
look at it.
https://github.com/RickCHodgin/libsf/tree/master/li386/oppie/oppie1
Best regards,
Rick C. Hodgin
Article: 158943On 5/27/2016 5:35 PM, Tim Wescott wrote: > On Fri, 27 May 2016 16:53:12 -0500, Cecil Bayona wrote: > >> On 5/27/2016 4:15 PM, Tim Wescott wrote: >>> On Fri, 27 May 2016 13:00:28 -0500, Cecil Bayona wrote: >>> >>>> I a retired person with limited resources and I've always been >>>> interested in CPU design, so now that I have time I wanted to give it >>>> a go using FPGAs to design simple CPUs. >>>> >>>> I would like some advice on several topics, one being which HDL >>>> language to learn first, although Verilog seems simpler I've read >>>> articles that encourages beginners to start with VHDL, although it >>>> seems more wordy, I believe it will help eliminate more dumb mistakes >>>> so I'm leaning that way. What is your advice? >>>> >>>> Another is which logic families/companies make products that are >>>> inexpensive and have good features useful in creating CPUs and DSP >>>> type products as I also am interested in Software Defined Radios. >>>> >>>> I have purchase for a starter kit a Lattice Brevia2 kit as it was >>>> inexpensive and has low power consumption, so I assume will be easier >>>> to use in the beginning. It's a simple device with 5K LUTs which seems >>>> to be enough for some of the simple processors that I'm interested in >>>> to start with, CPUs such as the J1 for starters. From some time back >>>> I've have a Xilinx Spartan 3 Started kit that I have not used, I plan >>>> to use it later for more complex designs. >>>> >>>> Your opinions and advice is welcomed. >>> >>> Verilog if you're on the west coast, VHDL if east. I'm not sure about >>> Texas, though. >>> >>> Seriously, it's a lot more important to understand how to design than >>> to pick the right language. You can do crappy work in either one, and >>> you can do good work in either one. >>> >> Hardware design I understand, I put together my own CPU design and built >> it with Schottky logic, and it worked rather well. But as to Verilog or >> VHDL I know zip. I do have a couple of books on the subject of FPGA >> programing but I don't think of them as any good. They go into the tiny >> details such on how to make an adder but contains little on the overall >> structure and how to design anything of consequence. >> >> Are there any books or Internet sources on the subject of overall design >> with FPGAs? I would be specifically interested on CPU design using HDL. > > Look for books with "Computer Systems Architecture" either in or as the > title. they will not and should not mention FPGAs -- by the time you're > making architectural decisions you probably shouldn't be too worried > about what the underlying technology is. > > Then, get your hands on data sheets for as many different processors as > you can and see how they did it. Think of strengths and weaknesses, and > why the designers might have done what they did. > > And let me indulge myself with a shout-out to the RCA COSMAC 1802 > processor. It was the first thing I ever wrote assembly for, and you > could practically draw the control logic from the instruction set. I > dimly remember (meaning that I saw it between two days and two decades > ago) that there's an FPGA version of the core that's at least byte- > accurate, if maybe not clock-cycle accurate. In these days of RISC > computers, it's nice to be familiar with a NHISC (Never Had an > Instruction Set) computer. > It looks like I didn't make myself clear enough on what I was looking for, I was looking for books or articles on FPGA programming that discusses how to use the software to program the FPGA to create CPU features. I already own a few books and have many articles on CPU architecture, plus books and literature on CPU instruction sets. Is there literature,basically a primer on how to create a simple CPU in HDL, preferably in VHDL? The alternative is that I will need to do it on my own by looking at a simple example such as the J1 , ep16, or the B16 CPUs and see what they are doing to create the CPU hardware blocks. The J1 is a pretty simple CPU done in less than 250 Verilog statements, the instructions are are bits controlling the various hardware features with no decoding of the instructions.The J16 is done in VHDL using a Lattice Brevia2 so it should run as is, the disadvantage is that it's more complex plus it's created by someone who is not very experienced. All three already have a compiler available to write software to test them. The disadvantage to all these simple CPUs is that there is no documentation to the software that creates the devices so as a rank beginner it will be difficult to see what they are doing. Thanks -- Cecil - k5nwaArticle: 158944
On 5/27/2016 8:27 PM, Cecil Bayona wrote: > On 5/27/2016 5:35 PM, Tim Wescott wrote: >> On Fri, 27 May 2016 16:53:12 -0500, Cecil Bayona wrote: >> >>> On 5/27/2016 4:15 PM, Tim Wescott wrote: >>>> On Fri, 27 May 2016 13:00:28 -0500, Cecil Bayona wrote: >>>> >>>>> I a retired person with limited resources and I've always been >>>>> interested in CPU design, so now that I have time I wanted to give it >>>>> a go using FPGAs to design simple CPUs. >>>>> >>>>> I would like some advice on several topics, one being which HDL >>>>> language to learn first, although Verilog seems simpler I've read >>>>> articles that encourages beginners to start with VHDL, although it >>>>> seems more wordy, I believe it will help eliminate more dumb mistakes >>>>> so I'm leaning that way. What is your advice? >>>>> >>>>> Another is which logic families/companies make products that are >>>>> inexpensive and have good features useful in creating CPUs and DSP >>>>> type products as I also am interested in Software Defined Radios. >>>>> >>>>> I have purchase for a starter kit a Lattice Brevia2 kit as it was >>>>> inexpensive and has low power consumption, so I assume will be easier >>>>> to use in the beginning. It's a simple device with 5K LUTs which seems >>>>> to be enough for some of the simple processors that I'm interested in >>>>> to start with, CPUs such as the J1 for starters. From some time back >>>>> I've have a Xilinx Spartan 3 Started kit that I have not used, I plan >>>>> to use it later for more complex designs. >>>>> >>>>> Your opinions and advice is welcomed. >>>> >>>> Verilog if you're on the west coast, VHDL if east. I'm not sure about >>>> Texas, though. >>>> >>>> Seriously, it's a lot more important to understand how to design than >>>> to pick the right language. You can do crappy work in either one, and >>>> you can do good work in either one. >>>> >>> Hardware design I understand, I put together my own CPU design and built >>> it with Schottky logic, and it worked rather well. But as to Verilog or >>> VHDL I know zip. I do have a couple of books on the subject of FPGA >>> programing but I don't think of them as any good. They go into the tiny >>> details such on how to make an adder but contains little on the overall >>> structure and how to design anything of consequence. >>> >>> Are there any books or Internet sources on the subject of overall design >>> with FPGAs? I would be specifically interested on CPU design using HDL. >> >> Look for books with "Computer Systems Architecture" either in or as the >> title. they will not and should not mention FPGAs -- by the time you're >> making architectural decisions you probably shouldn't be too worried >> about what the underlying technology is. >> >> Then, get your hands on data sheets for as many different processors as >> you can and see how they did it. Think of strengths and weaknesses, and >> why the designers might have done what they did. >> >> And let me indulge myself with a shout-out to the RCA COSMAC 1802 >> processor. It was the first thing I ever wrote assembly for, and you >> could practically draw the control logic from the instruction set. I >> dimly remember (meaning that I saw it between two days and two decades >> ago) that there's an FPGA version of the core that's at least byte- >> accurate, if maybe not clock-cycle accurate. In these days of RISC >> computers, it's nice to be familiar with a NHISC (Never Had an >> Instruction Set) computer. >> > It looks like I didn't make myself clear enough on what I was looking > for, I was looking for books or articles on FPGA programming that > discusses how to use the software to program the FPGA to create CPU > features. I already own a few books and have many articles on CPU > architecture, plus books and literature on CPU instruction sets. > > Is there literature,basically a primer on how to create a simple CPU in > HDL, preferably in VHDL? > > The alternative is that I will need to do it on my own by looking at a > simple example such as the J1 , ep16, or the B16 CPUs and see what they > are doing to create the CPU hardware blocks. The J1 is a pretty simple > CPU done in less than 250 Verilog statements, the instructions are are > bits controlling the various hardware features with no decoding of the > instructions.The J16 is done in VHDL using a Lattice Brevia2 so it > should run as is, the disadvantage is that it's more complex plus it's > created by someone who is not very experienced. All three already have a > compiler available to write software to test them. Sorry it the ep16 instead of the J16 that is in VHDL and uses a Lattice Brevia2 board. > > The disadvantage to all these simple CPUs is that there is no > documentation to the software that creates the devices so as a rank > beginner it will be difficult to see what they are doing. > > Thanks -- Cecil - k5nwaArticle: 158945
On 5/27/2016 12:57 PM, Rob Gaddi wrote: > http://www.xess.com/blog/extinction-level-event/ > > The synopsis of the guy's argument is: Given Intel bought Altera, and > rumors that *comm is eyeing Xilinx, that's likely to shift the focus of > both tier 1 FPGA companies to datacenters and away from traditional > programmable logic. > > We need a good Friday thread, it's been a while. What do y'all think? I think the article overstates the dichotomy of supporting the traditional FPGA market and the datacenter market. Will FPGAs need to vary so much to support one market vs. the other? They are hugely programmable. Neither X nor A have pushed much on alternate architectures that might be a significant advantage in a particular market. I think it will mostly be steady as she goes with most of the changes in marketing rather than engineering. -- Rick CArticle: 158946
On 5/27/2016 2:00 PM, Cecil Bayona wrote: > I a retired person with limited resources and I've always been > interested in CPU design, so now that I have time I wanted to give it a > go using FPGAs to design simple CPUs. > > I would like some advice on several topics, one being which HDL language > to learn first, although Verilog seems simpler I've read articles that > encourages beginners to start with VHDL, although it seems more wordy, I > believe it will help eliminate more dumb mistakes so I'm leaning that > way. What is your advice? > > Another is which logic families/companies make products that are > inexpensive and have good features useful in creating CPUs and DSP type > products as I also am interested in Software Defined Radios. > > I have purchase for a starter kit a Lattice Brevia2 kit as it was > inexpensive and has low power consumption, so I assume will be easier to > use in the beginning. It's a simple device with 5K LUTs which seems to > be enough for some of the simple processors that I'm interested in to > start with, CPUs such as the J1 for starters. From some time back I've > have a Xilinx Spartan 3 Started kit that I have not used, I plan to use > it later for more complex designs. > > Your opinions and advice is welcomed. This does not directly address your stated issues, but there is a workshop Saturday. Notable is that it will use the same starter kit you have. I believe you can participate via the Internet. It might be interesting to you since it is about CPU design. Here is a post I made about this in another group. Dr. Ting will be leading a workshop on using a Lattice FPGA to implement an emulation of the 8080 instruction set which will run Forth. http://www.meetup.com/SV-FIG/events/229926249/ I believe you need to be a member of Meetup to see this page. I'm not sure but you may need to be a member of the SVFIG meetup group as well. There is no charge to join either. -- Rick CArticle: 158947
On Friday, May 27, 2016 at 8:27:34 PM UTC-5, Cecil Bayona wrote: > On 5/27/2016 5:35 PM, Tim Wescott wrote: > > On Fri, 27 May 2016 16:53:12 -0500, Cecil Bayona wrote: > > > >> On 5/27/2016 4:15 PM, Tim Wescott wrote: > >>> On Fri, 27 May 2016 13:00:28 -0500, Cecil Bayona wrote: > >>> > >>>> I a retired person with limited resources and I've always been > >>>> interested in CPU design, so now that I have time I wanted to give it > >>>> a go using FPGAs to design simple CPUs. > >>>> > >>>> I would like some advice on several topics, one being which HDL > >>>> language to learn first, although Verilog seems simpler I've read > >>>> articles that encourages beginners to start with VHDL, although it > >>>> seems more wordy, I believe it will help eliminate more dumb mistakes > >>>> so I'm leaning that way. What is your advice? > >>>> > >>>> Another is which logic families/companies make products that are > >>>> inexpensive and have good features useful in creating CPUs and DSP > >>>> type products as I also am interested in Software Defined Radios. > >>>> > >>>> I have purchase for a starter kit a Lattice Brevia2 kit as it was > >>>> inexpensive and has low power consumption, so I assume will be easier > >>>> to use in the beginning. It's a simple device with 5K LUTs which seems > >>>> to be enough for some of the simple processors that I'm interested in > >>>> to start with, CPUs such as the J1 for starters. From some time back > >>>> I've have a Xilinx Spartan 3 Started kit that I have not used, I plan > >>>> to use it later for more complex designs. > >>>> > >>>> Your opinions and advice is welcomed. > >>> > >>> Verilog if you're on the west coast, VHDL if east. I'm not sure about > >>> Texas, though. > >>> > >>> Seriously, it's a lot more important to understand how to design than > >>> to pick the right language. You can do crappy work in either one, and > >>> you can do good work in either one. > >>> > >> Hardware design I understand, I put together my own CPU design and built > >> it with Schottky logic, and it worked rather well. But as to Verilog or > >> VHDL I know zip. I do have a couple of books on the subject of FPGA > >> programing but I don't think of them as any good. They go into the tiny > >> details such on how to make an adder but contains little on the overall > >> structure and how to design anything of consequence. > >> > >> Are there any books or Internet sources on the subject of overall design > >> with FPGAs? I would be specifically interested on CPU design using HDL. > > > > Look for books with "Computer Systems Architecture" either in or as the > > title. they will not and should not mention FPGAs -- by the time you're > > making architectural decisions you probably shouldn't be too worried > > about what the underlying technology is. > > > > Then, get your hands on data sheets for as many different processors as > > you can and see how they did it. Think of strengths and weaknesses, and > > why the designers might have done what they did. > > > > And let me indulge myself with a shout-out to the RCA COSMAC 1802 > > processor. It was the first thing I ever wrote assembly for, and you > > could practically draw the control logic from the instruction set. I > > dimly remember (meaning that I saw it between two days and two decades > > ago) that there's an FPGA version of the core that's at least byte- > > accurate, if maybe not clock-cycle accurate. In these days of RISC > > computers, it's nice to be familiar with a NHISC (Never Had an > > Instruction Set) computer. > > > It looks like I didn't make myself clear enough on what I was looking > for, I was looking for books or articles on FPGA programming that > discusses how to use the software to program the FPGA to create CPU > features. I already own a few books and have many articles on CPU > architecture, plus books and literature on CPU instruction sets. > > Is there literature,basically a primer on how to create a simple CPU in > HDL, preferably in VHDL? > > The alternative is that I will need to do it on my own by looking at a > simple example such as the J1 , ep16, or the B16 CPUs and see what they > are doing to create the CPU hardware blocks. The J1 is a pretty simple > CPU done in less than 250 Verilog statements, the instructions are are > bits controlling the various hardware features with no decoding of the > instructions.The J16 is done in VHDL using a Lattice Brevia2 so it > should run as is, the disadvantage is that it's more complex plus it's > created by someone who is not very experienced. All three already have a > compiler available to write software to test them. > > The disadvantage to all these simple CPUs is that there is no > documentation to the software that creates the devices so as a rank > beginner it will be difficult to see what they are doing. > > Thanks > -- > Cecil - k5nwa ]>The disadvantage to all these simple CPUs is that there is no ]> documentation to the software that creates the devices so as a rank ]> beginner it will be difficult to see what they are doing. Did a presentation in March directed towards this problem. The idea is to do the simplest possible soft core processor (done here in VHDL). It helps to use the fewest lines of code. The PDF of the slides is at: http://opencores.org/project,rois,downloads "DIY soft-core processor" Full VHDL code is available on the Overview section. Only four instructions are implemented (didn't want to make it too easy for students). If you enjoy doing test cases and would like to help, send an e-mail. Jim BrakefieldArticle: 158948
On 5/27/2016 10:10 PM, rickman wrote: >> Your opinions and advice is welcomed. > > This does not directly address your stated issues, but there is a > workshop Saturday. Notable is that it will use the same starter kit you > have. I believe you can participate via the Internet. It might be > interesting to you since it is about CPU design. Here is a post I made > about this in another group. > > Dr. Ting will be leading a workshop on using a Lattice FPGA to implement > an emulation of the 8080 instruction set which will run Forth. > > http://www.meetup.com/SV-FIG/events/229926249/ > > I believe you need to be a member of Meetup to see this page. I'm not > sure but you may need to be a member of the SVFIG meetup group as well. > There is no charge to join either. > Thanks, I already joined, that is the reason for buying the Lattice Brevia2, I will be watching the meeting, but the video is supposed to be available afterwards so I can take my time afterwards and go through the course at my pace. I loaded Diamond on a Virtual Windows 7 partition and setup the ep8080 project and noticed that the software warned of a clock issue, Dr Ting mentioned that he was having issues where if he made changes things would break so that clock issue might be related. I been looking at some video courses and they had a lot of information on translating a set of hardware into VHDL code, so over the next few weeks I will be trying the lessons to become familiar with VHDL. In the meantime I will also be looking for books on VHDL and how to use it to create hardware. I have done hardware design some time back and I still like doing so but I'm hoping that once I become more familiar with FPGAs I can do more experimenting as buy once and try out many times is perfect for experimenting. -- Cecil - k5nwaArticle: 158949
On 5/27/2016 10:46 PM, jim.brakefield@ieee.org wrote: > On Friday, May 27, 2016 at 8:27:34 PM UTC-5, Cecil Bayona wrote: >> The disadvantage to all these simple CPUs is that there is no >> documentation to the software that creates the devices so as a rank >> beginner it will be difficult to see what they are doing. >> >> Thanks >> -- >> Cecil - k5nwa > > ]>The disadvantage to all these simple CPUs is that there is no > ]> documentation to the software that creates the devices so as a rank > ]> beginner it will be difficult to see what they are doing. > > Did a presentation in March directed towards this problem. The idea is to do > the simplest possible soft core processor (done here in VHDL). It helps to > use the fewest lines of code. The PDF of the slides is at: > http://opencores.org/project,rois,downloads "DIY soft-core processor" > Full VHDL code is available on the Overview section. Only four instructions > are implemented (didn't want to make it too easy for students). > > If you enjoy doing test cases and would like to help, send an e-mail. > > Jim Brakefield > Thanks for the link, I will look at it this weekend, every little bit helps. I watched a series of YouTube videos and there is hope, a small project but not idiot simple and done by hand, it didn't seen as alien as I thought it would be. The person basically designed the hardware and then proceeded to generate the program with explanation of what he was doing, of course the devil hides in the details but still it looked logical and not difficult. So after the weekend I will try it out. This weekend I will be following a seminar on the ep8080 CPU, a high performance clone of the 8080 CPU not only does it run at higher speed but most instructions execute in one clock cycle, it should be interesting. -- Cecil - k5nwa
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